Re: [PATCH 2/3] powerpc: Avoid load hit store in setup_sigcontext()

[Michael Neuling <mikey@neuling.org>]

On Sun, 2016-05-29 at 22:03 +1000, Anton Blanchard wrote:
> From: Anton Blanchard <anton@samba.org>
>=20
> In setup_sigcontext(), we set current->thread.vrsave then use it
> straight after. Since current is hidden from the compiler via inline
> assembly, it cannot optimise this and we end up with a load hit store.

Is setup_sigcontext() really a fast path we need to optimise?

Mikey

> Fix this by using a temporary.
>=20
> Signed-off-by: Anton Blanchard <anton@samba.org>
> ---
> =C2=A0arch/powerpc/kernel/signal_64.c | 11 ++++++++---
> =C2=A01 file changed, 8 insertions(+), 3 deletions(-)
>=20
> diff --git a/arch/powerpc/kernel/signal_64.c
> b/arch/powerpc/kernel/signal_64.c
> index 2552079..7e49984 100644
> --- a/arch/powerpc/kernel/signal_64.c
> +++ b/arch/powerpc/kernel/signal_64.c
> @@ -104,6 +104,7 @@ static long setup_sigcontext(struct sigcontext __user
> *sc, struct pt_regs *regs,
> =C2=A0	=C2=A0*/
> =C2=A0#ifdef CONFIG_ALTIVEC
> =C2=A0	elf_vrreg_t __user *v_regs =3D sigcontext_vmx_regs(sc);
> +	unsigned long vrsave;
> =C2=A0#endif
> =C2=A0	unsigned long msr =3D regs->msr;
> =C2=A0	long err =3D 0;
> @@ -125,9 +126,13 @@ static long setup_sigcontext(struct sigcontext
> __user *sc, struct pt_regs *regs,
> =C2=A0	/* We always copy to/from vrsave, it's 0 if we don't have or
> don't
> =C2=A0	=C2=A0* use altivec.
> =C2=A0	=C2=A0*/
> -	if (cpu_has_feature(CPU_FTR_ALTIVEC))
> -		current->thread.vrsave =3D mfspr(SPRN_VRSAVE);
> -	err |=3D __put_user(current->thread.vrsave, (u32 __user
> *)&v_regs[33]);
> +	vrsave =3D 0;
> +	if (cpu_has_feature(CPU_FTR_ALTIVEC)) {
> +		vrsave =3D mfspr(SPRN_VRSAVE);
> +		current->thread.vrsave =3D vrsave;
> +	}
> +
> +	err |=3D __put_user(vrsave, (u32 __user *)&v_regs[33]);
> =C2=A0#else /* CONFIG_ALTIVEC */
> =C2=A0	err |=3D __put_user(0, &sc->v_regs);
> =C2=A0#endif /* CONFIG_ALTIVEC */