diff for duplicates of <14646641.DlFrJR068n@diego> diff --git a/a/1.txt b/N1/1.txt index 51b9301..a88137d 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,7 +1,7 @@ Node definitions shared by all rk3288 based boards. -Signed-off-by: Heiko Stuebner <heiko@sntech.de> -Tested-by: Will Deacon <will.deacon@arm.com> +Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> +Tested-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> --- arch/arm/boot/dts/rk3288.dtsi | 552 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 552 insertions(+) @@ -55,22 +55,22 @@ index 0000000..c8e387e + #address-cells = <1>; + #size-cells = <0>; + -+ cpu at 500 { ++ cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x500>; + }; -+ cpu at 501 { ++ cpu@501 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x501>; + }; -+ cpu at 502 { ++ cpu@502 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x502>; + }; -+ cpu at 503 { ++ cpu@503 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x503>; @@ -92,7 +92,7 @@ index 0000000..c8e387e + clock-frequency = <24000000>; + }; + -+ i2c1: i2c at ff140000 { ++ i2c1: i2c@ff140000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff140000 0x1000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; @@ -103,7 +103,7 @@ index 0000000..c8e387e + status = "disabled"; + }; + -+ i2c3: i2c at ff150000 { ++ i2c3: i2c@ff150000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff150000 0x1000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; @@ -114,7 +114,7 @@ index 0000000..c8e387e + status = "disabled"; + }; + -+ i2c4: i2c at ff160000 { ++ i2c4: i2c@ff160000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff160000 0x1000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; @@ -125,7 +125,7 @@ index 0000000..c8e387e + status = "disabled"; + }; + -+ i2c5: i2c at ff170000 { ++ i2c5: i2c@ff170000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff170000 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; @@ -136,7 +136,7 @@ index 0000000..c8e387e + status = "disabled"; + }; + -+ uart0: serial at ff180000 { ++ uart0: serial@ff180000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0xff180000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -147,7 +147,7 @@ index 0000000..c8e387e + status = "disabled"; + }; + -+ uart1: serial at ff190000 { ++ uart1: serial@ff190000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0xff190000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; @@ -158,7 +158,7 @@ index 0000000..c8e387e + status = "disabled"; + }; + -+ uart2: serial at ff690000 { ++ uart2: serial@ff690000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0xff690000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; @@ -169,7 +169,7 @@ index 0000000..c8e387e + status = "disabled"; + }; + -+ uart3: serial at ff1b0000 { ++ uart3: serial@ff1b0000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0xff1b0000 0x100>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; @@ -180,7 +180,7 @@ index 0000000..c8e387e + status = "disabled"; + }; + -+ uart4: serial at ff1c0000 { ++ uart4: serial@ff1c0000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0xff1c0000 0x100>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; @@ -191,7 +191,7 @@ index 0000000..c8e387e + status = "disabled"; + }; + -+ i2c0: i2c at ff650000 { ++ i2c0: i2c@ff650000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff650000 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; @@ -202,7 +202,7 @@ index 0000000..c8e387e + status = "disabled"; + }; + -+ i2c2: i2c at ff660000 { ++ i2c2: i2c@ff660000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff660000 0x1000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; @@ -213,17 +213,17 @@ index 0000000..c8e387e + status = "disabled"; + }; + -+ pmu: power-management at ff730000 { ++ pmu: power-management@ff730000 { + compatible = "rockchip,rk3288-pmu", "syscon"; + reg = <0xff730000 0x100>; + }; + -+ sgrf: syscon at ff740000 { ++ sgrf: syscon@ff740000 { + compatible = "rockchip,rk3288-sgrf", "syscon"; + reg = <0xff740000 0x1000>; + }; + -+ cru: clock-controller at ff760000 { ++ cru: clock-controller@ff760000 { + compatible = "rockchip,rk3288-cru"; + reg = <0xff760000 0x1000>; + rockchip,grf = <&grf>; @@ -231,19 +231,19 @@ index 0000000..c8e387e + #reset-cells = <1>; + }; + -+ grf: syscon at ff770000 { ++ grf: syscon@ff770000 { + compatible = "rockchip,rk3288-grf", "syscon"; + reg = <0xff770000 0x1000>; + }; + -+ watchdog at ff800000 { ++ watchdog@ff800000 { + compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; + reg = <0xff800000 0x100>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + -+ gic: interrupt-controller at ffc01000 { ++ gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; @@ -264,7 +264,7 @@ index 0000000..c8e387e + #size-cells = <1>; + ranges; + -+ gpio0: gpio0 at ff750000 { ++ gpio0: gpio0@ff750000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff750000 0x100>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; @@ -277,7 +277,7 @@ index 0000000..c8e387e + #interrupt-cells = <2>; + }; + -+ gpio1: gpio1 at ff780000 { ++ gpio1: gpio1@ff780000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff780000 0x100>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; @@ -290,7 +290,7 @@ index 0000000..c8e387e + #interrupt-cells = <2>; + }; + -+ gpio2: gpio2 at ff790000 { ++ gpio2: gpio2@ff790000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff790000 0x100>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; @@ -303,7 +303,7 @@ index 0000000..c8e387e + #interrupt-cells = <2>; + }; + -+ gpio3: gpio3 at ff7a0000 { ++ gpio3: gpio3@ff7a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7a0000 0x100>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; @@ -316,7 +316,7 @@ index 0000000..c8e387e + #interrupt-cells = <2>; + }; + -+ gpio4: gpio4 at ff7b0000 { ++ gpio4: gpio4@ff7b0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7b0000 0x100>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; @@ -329,7 +329,7 @@ index 0000000..c8e387e + #interrupt-cells = <2>; + }; + -+ gpio5: gpio5 at ff7c0000 { ++ gpio5: gpio5@ff7c0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7c0000 0x100>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; @@ -342,7 +342,7 @@ index 0000000..c8e387e + #interrupt-cells = <2>; + }; + -+ gpio6: gpio6 at ff7d0000 { ++ gpio6: gpio6@ff7d0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7d0000 0x100>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; @@ -355,7 +355,7 @@ index 0000000..c8e387e + #interrupt-cells = <2>; + }; + -+ gpio7: gpio7 at ff7e0000 { ++ gpio7: gpio7@ff7e0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7e0000 0x100>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; @@ -368,7 +368,7 @@ index 0000000..c8e387e + #interrupt-cells = <2>; + }; + -+ gpio8: gpio8 at ff7f0000 { ++ gpio8: gpio8@ff7f0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7f0000 0x100>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; @@ -567,3 +567,9 @@ index 0000000..c8e387e +}; -- 1.9.0 + + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index cda9695..9a5acb1 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,14 +1,17 @@ "ref\04868343.UFgjaXesOn@diego\0" - "From\0heiko@sntech.de (Heiko St\303\274bner)\0" + "From\0Heiko St\303\274bner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\0" "Subject\0[PATCH v2 6/7] ARM: dts: rockchip: add core rk3288 dtsi\0" "Date\0Fri, 18 Jul 2014 02:21:25 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" + "Cc\0olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org" + eddie.cai-TNX95d0MmH7DzftRWevZcw@public.gmane.org + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" "Node definitions shared by all rk3288 based boards.\n" "\n" - "Signed-off-by: Heiko Stuebner <heiko@sntech.de>\n" - "Tested-by: Will Deacon <will.deacon@arm.com>\n" + "Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "Tested-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\n" "---\n" " arch/arm/boot/dts/rk3288.dtsi | 552 ++++++++++++++++++++++++++++++++++++++++++\n" " 1 file changed, 552 insertions(+)\n" @@ -62,22 +65,22 @@ "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tcpu at 500 {\n" + "+\t\tcpu@500 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a12\";\n" "+\t\t\treg = <0x500>;\n" "+\t\t};\n" - "+\t\tcpu at 501 {\n" + "+\t\tcpu@501 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a12\";\n" "+\t\t\treg = <0x501>;\n" "+\t\t};\n" - "+\t\tcpu at 502 {\n" + "+\t\tcpu@502 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a12\";\n" "+\t\t\treg = <0x502>;\n" "+\t\t};\n" - "+\t\tcpu at 503 {\n" + "+\t\tcpu@503 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a12\";\n" "+\t\t\treg = <0x503>;\n" @@ -99,7 +102,7 @@ "+\t\tclock-frequency = <24000000>;\n" "+\t};\n" "+\n" - "+\ti2c1: i2c at ff140000 {\n" + "+\ti2c1: i2c@ff140000 {\n" "+\t\tcompatible = \"rockchip,rk3288-i2c\";\n" "+\t\treg = <0xff140000 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -110,7 +113,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c3: i2c at ff150000 {\n" + "+\ti2c3: i2c@ff150000 {\n" "+\t\tcompatible = \"rockchip,rk3288-i2c\";\n" "+\t\treg = <0xff150000 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -121,7 +124,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c4: i2c at ff160000 {\n" + "+\ti2c4: i2c@ff160000 {\n" "+\t\tcompatible = \"rockchip,rk3288-i2c\";\n" "+\t\treg = <0xff160000 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -132,7 +135,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c5: i2c at ff170000 {\n" + "+\ti2c5: i2c@ff170000 {\n" "+\t\tcompatible = \"rockchip,rk3288-i2c\";\n" "+\t\treg = <0xff170000 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -143,7 +146,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tuart0: serial at ff180000 {\n" + "+\tuart0: serial@ff180000 {\n" "+\t\tcompatible = \"rockchip,rk3288-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0xff180000 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -154,7 +157,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tuart1: serial at ff190000 {\n" + "+\tuart1: serial@ff190000 {\n" "+\t\tcompatible = \"rockchip,rk3288-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0xff190000 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -165,7 +168,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tuart2: serial at ff690000 {\n" + "+\tuart2: serial@ff690000 {\n" "+\t\tcompatible = \"rockchip,rk3288-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0xff690000 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -176,7 +179,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tuart3: serial at ff1b0000 {\n" + "+\tuart3: serial@ff1b0000 {\n" "+\t\tcompatible = \"rockchip,rk3288-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0xff1b0000 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -187,7 +190,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tuart4: serial at ff1c0000 {\n" + "+\tuart4: serial@ff1c0000 {\n" "+\t\tcompatible = \"rockchip,rk3288-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0xff1c0000 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -198,7 +201,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c0: i2c at ff650000 {\n" + "+\ti2c0: i2c@ff650000 {\n" "+\t\tcompatible = \"rockchip,rk3288-i2c\";\n" "+\t\treg = <0xff650000 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -209,7 +212,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c2: i2c at ff660000 {\n" + "+\ti2c2: i2c@ff660000 {\n" "+\t\tcompatible = \"rockchip,rk3288-i2c\";\n" "+\t\treg = <0xff660000 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -220,17 +223,17 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tpmu: power-management at ff730000 {\n" + "+\tpmu: power-management@ff730000 {\n" "+\t\tcompatible = \"rockchip,rk3288-pmu\", \"syscon\";\n" "+\t\treg = <0xff730000 0x100>;\n" "+\t};\n" "+\n" - "+\tsgrf: syscon at ff740000 {\n" + "+\tsgrf: syscon@ff740000 {\n" "+\t\tcompatible = \"rockchip,rk3288-sgrf\", \"syscon\";\n" "+\t\treg = <0xff740000 0x1000>;\n" "+\t};\n" "+\n" - "+\tcru: clock-controller at ff760000 {\n" + "+\tcru: clock-controller@ff760000 {\n" "+\t\tcompatible = \"rockchip,rk3288-cru\";\n" "+\t\treg = <0xff760000 0x1000>;\n" "+\t\trockchip,grf = <&grf>;\n" @@ -238,19 +241,19 @@ "+\t\t#reset-cells = <1>;\n" "+\t};\n" "+\n" - "+\tgrf: syscon at ff770000 {\n" + "+\tgrf: syscon@ff770000 {\n" "+\t\tcompatible = \"rockchip,rk3288-grf\", \"syscon\";\n" "+\t\treg = <0xff770000 0x1000>;\n" "+\t};\n" "+\n" - "+\twatchdog at ff800000 {\n" + "+\twatchdog@ff800000 {\n" "+\t\tcompatible = \"rockchip,rk3288-wdt\", \"snps,dw-wdt\";\n" "+\t\treg = <0xff800000 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tgic: interrupt-controller at ffc01000 {\n" + "+\tgic: interrupt-controller@ffc01000 {\n" "+\t\tcompatible = \"arm,gic-400\";\n" "+\t\tinterrupt-controller;\n" "+\t\t#interrupt-cells = <3>;\n" @@ -271,7 +274,7 @@ "+\t\t#size-cells = <1>;\n" "+\t\tranges;\n" "+\n" - "+\t\tgpio0: gpio0 at ff750000 {\n" + "+\t\tgpio0: gpio0@ff750000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg =\t<0xff750000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -284,7 +287,7 @@ "+\t\t\t#interrupt-cells = <2>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio1: gpio1 at ff780000 {\n" + "+\t\tgpio1: gpio1@ff780000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0xff780000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -297,7 +300,7 @@ "+\t\t\t#interrupt-cells = <2>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio2: gpio2 at ff790000 {\n" + "+\t\tgpio2: gpio2@ff790000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0xff790000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -310,7 +313,7 @@ "+\t\t\t#interrupt-cells = <2>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio3: gpio3 at ff7a0000 {\n" + "+\t\tgpio3: gpio3@ff7a0000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0xff7a0000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -323,7 +326,7 @@ "+\t\t\t#interrupt-cells = <2>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio4: gpio4 at ff7b0000 {\n" + "+\t\tgpio4: gpio4@ff7b0000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0xff7b0000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -336,7 +339,7 @@ "+\t\t\t#interrupt-cells = <2>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio5: gpio5 at ff7c0000 {\n" + "+\t\tgpio5: gpio5@ff7c0000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0xff7c0000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -349,7 +352,7 @@ "+\t\t\t#interrupt-cells = <2>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio6: gpio6 at ff7d0000 {\n" + "+\t\tgpio6: gpio6@ff7d0000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0xff7d0000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -362,7 +365,7 @@ "+\t\t\t#interrupt-cells = <2>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio7: gpio7 at ff7e0000 {\n" + "+\t\tgpio7: gpio7@ff7e0000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0xff7e0000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -375,7 +378,7 @@ "+\t\t\t#interrupt-cells = <2>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio8: gpio8 at ff7f0000 {\n" + "+\t\tgpio8: gpio8@ff7f0000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0xff7f0000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -573,6 +576,12 @@ "+\t};\n" "+};\n" "-- \n" - 1.9.0 + "1.9.0\n" + "\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -8132c0c84f008a0d7fbbe8580840f9050b12a0e4f0655d2fc36e965072b920a4 +8199aa5fd5d8f525428a24ecf966a3701f888221730e19aee61d117ef84907d3
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.