From: <gregkh@linuxfoundation.org>
To: james.hogan@imgtec.com, gregkh@linuxfoundation.org,
paul.burton@imgtec.com, ralf@linux-mips.org
Cc: <stable@vger.kernel.org>, <stable-commits@vger.kernel.org>
Subject: Patch "MIPS: Fix MSA ld_*/st_* asm macros to use PTR_ADDU" has been added to the 4.4-stable tree
Date: Sat, 04 Jun 2016 11:40:53 -0700 [thread overview]
Message-ID: <14650656531354@kroah.com> (raw)
This is a note to let you know that I've just added the patch titled
MIPS: Fix MSA ld_*/st_* asm macros to use PTR_ADDU
to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-fix-msa-ld_-st_-asm-macros-to-use-ptr_addu.patch
and it can be found in the queue-4.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From ea1688573426adc2587ed52d086b51c7c62eaca3 Mon Sep 17 00:00:00 2001
From: James Hogan <james.hogan@imgtec.com>
Date: Fri, 15 Apr 2016 10:07:24 +0100
Subject: MIPS: Fix MSA ld_*/st_* asm macros to use PTR_ADDU
From: James Hogan <james.hogan@imgtec.com>
commit ea1688573426adc2587ed52d086b51c7c62eaca3 upstream.
The MSA ld_*/st_* assembler macros for when the toolchain doesn't
support MSA use addu to offset the base address. However it is a virtual
memory pointer so fix it to use PTR_ADDU which expands to daddu for
64-bit kernels.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13062/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/mips/include/asm/asmmacro.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -393,7 +393,7 @@
.set push
.set noat
SET_HARDFLOAT
- addu $1, \base, \off
+ PTR_ADDU $1, \base, \off
.word LDB_MSA_INSN | (\wd << 6)
.set pop
.endm
@@ -402,7 +402,7 @@
.set push
.set noat
SET_HARDFLOAT
- addu $1, \base, \off
+ PTR_ADDU $1, \base, \off
.word LDH_MSA_INSN | (\wd << 6)
.set pop
.endm
@@ -411,7 +411,7 @@
.set push
.set noat
SET_HARDFLOAT
- addu $1, \base, \off
+ PTR_ADDU $1, \base, \off
.word LDW_MSA_INSN | (\wd << 6)
.set pop
.endm
@@ -420,7 +420,7 @@
.set push
.set noat
SET_HARDFLOAT
- addu $1, \base, \off
+ PTR_ADDU $1, \base, \off
.word LDD_MSA_INSN | (\wd << 6)
.set pop
.endm
@@ -429,7 +429,7 @@
.set push
.set noat
SET_HARDFLOAT
- addu $1, \base, \off
+ PTR_ADDU $1, \base, \off
.word STB_MSA_INSN | (\wd << 6)
.set pop
.endm
@@ -438,7 +438,7 @@
.set push
.set noat
SET_HARDFLOAT
- addu $1, \base, \off
+ PTR_ADDU $1, \base, \off
.word STH_MSA_INSN | (\wd << 6)
.set pop
.endm
@@ -447,7 +447,7 @@
.set push
.set noat
SET_HARDFLOAT
- addu $1, \base, \off
+ PTR_ADDU $1, \base, \off
.word STW_MSA_INSN | (\wd << 6)
.set pop
.endm
@@ -456,7 +456,7 @@
.set push
.set noat
SET_HARDFLOAT
- addu $1, \base, \off
+ PTR_ADDU $1, \base, \off
.word STD_MSA_INSN | (\wd << 6)
.set pop
.endm
Patches currently in stable-queue which might be from james.hogan@imgtec.com are
queue-4.4/mips64-r6-r2-emulation-bugfix.patch
queue-4.4/mips-fix-uapi-include-in-exported-asm-siginfo.h.patch
queue-4.4/mips-disable-preemption-during-prctl-pr_set_fp_mode.patch
queue-4.4/mips-fix-sigreturn-via-vdso-on-micromips-kernel.patch
queue-4.4/mips-fix-siginfo.h-to-use-strict-posix-types.patch
queue-4.4/mips-don-t-unwind-to-user-mode-with-eva.patch
queue-4.4/mips-vdso-build-with-fno-strict-aliasing.patch
queue-4.4/mips-fix-watchpoint-restoration.patch
queue-4.4/mips-build-micromips-vdso-for-micromips-kernels.patch
queue-4.4/mips-math-emu-fix-jalr-emulation-when-rd-0.patch
queue-4.4/mips-fix-msa-ld_-st_-asm-macros-to-use-ptr_addu.patch
queue-4.4/mips-avoid-using-unwind_stack-with-usermode.patch
queue-4.4/mips-prevent-restoration-of-msa-context-in-non-msa-kernels.patch
queue-4.4/mips-use-copy_s.fmt-rather-than-copy_u.fmt.patch
reply other threads:[~2016-06-04 18:40 UTC|newest]
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