From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:33193 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751281AbcFDTQE (ORCPT ); Sat, 4 Jun 2016 15:16:04 -0400 Subject: Patch "clk: bcm2835: divider value has to be 1 or more" has been added to the 4.5-stable tree To: kernel@martin.sperl.org, eric@anholt.net, gregkh@linuxfoundation.org Cc: , From: Date: Sat, 04 Jun 2016 12:16:03 -0700 Message-ID: <146506776323547@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled clk: bcm2835: divider value has to be 1 or more to the 4.5-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: clk-bcm2835-divider-value-has-to-be-1-or-more.patch and it can be found in the queue-4.5 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From 997f16bd5d2e9b3456027f96fcadfe1e2bf12f4e Mon Sep 17 00:00:00 2001 From: Martin Sperl Date: Mon, 29 Feb 2016 11:39:20 +0000 Subject: clk: bcm2835: divider value has to be 1 or more From: Martin Sperl commit 997f16bd5d2e9b3456027f96fcadfe1e2bf12f4e upstream. Current clamping of a normal divider allows a value < 1 to be valid. A divider of < 1 would actually only be possible if we had a PLL... So this patch clamps the divider to 1. Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") Signed-off-by: Martin Sperl Signed-off-by: Eric Anholt Reviewed-by: Eric Anholt Signed-off-by: Greg Kroah-Hartman --- drivers/clk/bcm/clk-bcm2835.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1193,8 +1193,9 @@ static u32 bcm2835_clock_choose_div(stru div += unused_frac_mask + 1; div &= ~unused_frac_mask; - /* Clamp to the limits. */ - div = max(div, unused_frac_mask + 1); + /* clamp to min divider of 1 */ + div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS); + /* clamp to the highest possible fractional divider */ div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, CM_DIV_FRAC_BITS - data->frac_bits)); Patches currently in stable-queue which might be from kernel@martin.sperl.org are queue-4.5/clk-bcm2835-correctly-enable-fractional-clock-support.patch queue-4.5/clk-bcm2835-pll_off-should-only-update-cm_pll_anarst.patch queue-4.5/clk-bcm2835-divider-value-has-to-be-1-or-more.patch