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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: "Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	"David Gibson" <david@gibson.dropbear.id.au>,
	"Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] ppc: complete the new HV mode
Date: Mon, 06 Jun 2016 17:04:06 +1000	[thread overview]
Message-ID: <1465196646.4274.35.camel@kernel.crashing.org> (raw)
In-Reply-To: <57551851.6000306@ilande.co.uk>

On Mon, 2016-06-06 at 07:29 +0100, Mark Cave-Ayland wrote:
> 
> The best reproducer is to run from David's ppc-for-2.7 branch with
> the above patch applied manually and then try booting the following
> ISOs which now panic on boot with the split I/D MMU mode enabled:

So at least HelenOS is fixed by this:

--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1969,6 +1969,11 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
         /* XXX: this case should be optimized,
          * giving a mask to tlb_flush_page
          */
+        /* This is broken, some CPUs invalidate a whole congruence
+         * class on an even smaller subset of bits and some OSes take
+         * advantage of this. Just blow the whole thing away.
+         */
+#if 0
         tlb_flush_page(cs, addr | (0x0 << 28));
         tlb_flush_page(cs, addr | (0x1 << 28));
         tlb_flush_page(cs, addr | (0x2 << 28));
@@ -1985,6 +1990,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
         tlb_flush_page(cs, addr | (0xD << 28));
         tlb_flush_page(cs, addr | (0xE << 28));
         tlb_flush_page(cs, addr | (0xF << 28));
+#else
+        tlb_flush(cs, 1);
+#endif
         break;
 #if defined(TARGET_PPC64)
     case POWERPC_MMU_64B:

I'll check Darwin...

Cheers,
Ben.


  reply	other threads:[~2016-06-06  7:04 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-03 12:11 [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode Cédric Le Goater
2016-06-03 12:11 ` [Qemu-devel] [PATCH 1/3] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV Cédric Le Goater
2016-06-03 12:11 ` [Qemu-devel] [PATCH 2/3] ppc: Better figure out if processor has HV mode Cédric Le Goater
2016-06-03 12:11 ` [Qemu-devel] [PATCH 3/3] ppc: fix hrfid, tlbia and slbia privilege Cédric Le Goater
2016-06-04  8:24   ` Thomas Huth
2016-06-06  1:10     ` David Gibson
2016-06-03 13:52 ` [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode Mark Cave-Ayland
2016-06-03 14:00   ` Cédric Le Goater
2016-06-03 14:06     ` Mark Cave-Ayland
2016-06-03 14:06     ` Cedric Le Goater
2016-06-03 14:14       ` Mark Cave-Ayland
2016-06-03 15:47         ` Mark Cave-Ayland
2016-06-03 17:54           ` Cédric Le Goater
2016-06-05 17:41   ` Cédric Le Goater
2016-06-05 22:26     ` Mark Cave-Ayland
2016-06-06  6:27       ` Cédric Le Goater
2016-06-06  6:30         ` Cedric Le Goater
2016-06-06  6:38           ` Mark Cave-Ayland
2016-06-07  7:04             ` Cédric Le Goater
2016-06-07  8:24               ` Mark Cave-Ayland
2016-06-06  1:47     ` David Gibson
2016-06-06  4:17     ` [Qemu-devel] [Qemu-ppc] " Benjamin Herrenschmidt
2016-06-06  7:28       ` Cédric Le Goater
2016-06-06  1:17 ` [Qemu-devel] " David Gibson
2016-06-06  3:55   ` Benjamin Herrenschmidt
2016-06-06  4:20     ` [Qemu-devel] [Qemu-ppc] " Benjamin Herrenschmidt
2016-06-06  6:29       ` Mark Cave-Ayland
2016-06-06  7:04         ` Benjamin Herrenschmidt [this message]
2016-06-06  7:06           ` Benjamin Herrenschmidt

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