From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, David Gibson <david@gibson.dropbear.id.au>,
Cedric Le Goater <clg@kaod.org>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Subject: [Qemu-devel] [PATCH 7/9] ppc: Fix slbia decode
Date: Tue, 7 Jun 2016 12:50:26 +1000 [thread overview]
Message-ID: <1465267828-10326-7-git-send-email-benh@kernel.crashing.org> (raw)
In-Reply-To: <1465267828-10326-1-git-send-email-benh@kernel.crashing.org>
Since at least the 2.05 architecture, the slbia instruction takes an
IH field in the opcode to provide some control on the effect of the
slbia on the ERATs (level-1 TLB).
We can safely ignore it as we always flush the whole qemu TLB but
we should allow the bits in the decode.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
target-ppc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3255184..33a9223 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9980,7 +9980,7 @@ GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
-GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
+GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
--
2.5.5
next prev parent reply other threads:[~2016-06-07 3:32 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-07 2:50 [Qemu-devel] [PATCH 1/9] ppc: Properly tag the translation cache based on MMU mode Benjamin Herrenschmidt
2016-06-07 2:50 ` [Qemu-devel] [PATCH 2/9] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors Benjamin Herrenschmidt
2016-06-07 2:50 ` [Qemu-devel] [PATCH 3/9] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode Benjamin Herrenschmidt
2016-06-07 2:50 ` [Qemu-devel] [PATCH 4/9] ppc: POWER7 had ACOP and PID registers Benjamin Herrenschmidt
2016-06-07 2:50 ` [Qemu-devel] [PATCH 5/9] ppc: POWER7 has lq/stq instructions and stq need to check ISA Benjamin Herrenschmidt
2016-06-07 2:50 ` [Qemu-devel] [PATCH 6/9] ppc: Fix mtmsr decoding Benjamin Herrenschmidt
2016-06-07 2:50 ` Benjamin Herrenschmidt [this message]
2016-06-07 2:50 ` [Qemu-devel] [PATCH 8/9] ppc: Add missing slbfee. instruction on ppc64 BookS processors Benjamin Herrenschmidt
2016-07-05 17:23 ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2016-07-05 22:10 ` Benjamin Herrenschmidt
2016-07-06 6:57 ` Cédric Le Goater
2016-07-06 7:24 ` Benjamin Herrenschmidt
2016-07-06 7:53 ` Cédric Le Goater
2016-07-06 8:14 ` Benjamin Herrenschmidt
2016-06-07 2:50 ` [Qemu-devel] [PATCH 9/9] ppc: Do not take exceptions on unknown SPRs in privileged mode Benjamin Herrenschmidt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1465267828-10326-7-git-send-email-benh@kernel.crashing.org \
--to=benh@kernel.crashing.org \
--cc=clg@kaod.org \
--cc=david@gibson.dropbear.id.au \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.