From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55564) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCvkg-0001vq-Cp for qemu-devel@nongnu.org; Tue, 14 Jun 2016 17:20:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bCvkb-0004SS-Rd for qemu-devel@nongnu.org; Tue, 14 Jun 2016 17:20:02 -0400 Message-ID: <1465939179.30200.19.camel@kernel.crashing.org> From: Benjamin Herrenschmidt Date: Wed, 15 Jun 2016 07:19:39 +1000 In-Reply-To: <20160614062505.GP4882@voom.fritz.box> References: <1465795496-15071-1-git-send-email-clg@kaod.org> <1465795496-15071-4-git-send-email-clg@kaod.org> <20160614062505.GP4882@voom.fritz.box> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 03/10] ppc: Rework POWER7 & POWER8 exception model (part 2) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson , =?ISO-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On Tue, 2016-06-14 at 16:25 +1000, David Gibson wrote: > > Properly implement LPES0/1 handling for HV vs. !HV mode. > >=C2=A0 > > Signed-off-by: Benjamin Herrenschmidt > > [clg: AIL implementation was fixed in commit 5c94b2a5e5ef > >=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 fixed checkpatch.pl errors ] >=20 > Code looks ok, but the short description really needs an update, > since > this has been taken out of its original series context. This is still what this does. It properly implements support for LPCR0 (LPCR1 isn't supported). It also fixes how the HV bit is handled when taking interrupts and which set of SRR's are used in some cases. Cheers, Ben.