From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Jarkko Nikula <jarkko.nikula@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
linux-i2c@vger.kernel.org, Wolfram Sang <wsa@the-dreams.de>
Subject: Re: [PATCH v1 2/3] i2c: designware-pci: Introduce Merrifield support
Date: Wed, 15 Jun 2016 17:09:54 +0300 [thread overview]
Message-ID: <1465999794.30123.122.camel@linux.intel.com> (raw)
In-Reply-To: <ffcdc682-1948-f048-b8df-4f3360fbe501@linux.intel.com>
On Wed, 2016-06-15 at 16:48 +0300, Jarkko Nikula wrote:
> On 06/15/2016 01:55 AM, Andy Shevchenko wrote:
> > This patch enables I2C controllers found on Intel Edison board.
> > +static int mrfld_setup(struct pci_dev *pdev, struct
> > dw_pci_controller *c)
> > +{
> > + switch (PCI_SLOT(pdev->devfn)) {
> > + case 8:
> > + c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
> > + return 0;
> > + case 9:
> > + c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
> > + return 0;
> > + }
> > + return -ENODEV;
> > +}
> > +
>
> What kind of bus numbers we are expected to see here and what offsets
> these magic numbers represent?
Official bus numbers are [1..7]. Thus, this + 1 at the end. First PCI
device provides 4 functions, that's why +0 and +4.
Do I need to add a comment there?
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
next prev parent reply other threads:[~2016-06-15 14:09 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-14 22:55 [PATCH v1 1/3] i2c: designware-pci: Make bus number allocation robust Andy Shevchenko
2016-06-14 22:55 ` [PATCH v1 2/3] i2c: designware-pci: Introduce Merrifield support Andy Shevchenko
2016-06-15 13:48 ` Jarkko Nikula
2016-06-15 14:09 ` Andy Shevchenko [this message]
2016-06-14 22:56 ` [PATCH v1 3/3] i2c: designware-pci: Sort header block alphabetically Andy Shevchenko
2016-06-15 13:49 ` Jarkko Nikula
2016-06-15 13:42 ` [PATCH v1 1/3] i2c: designware-pci: Make bus number allocation robust Jarkko Nikula
2016-06-15 14:15 ` Andy Shevchenko
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