[PATCH v02 0/5] fix MSR_LAST_BRANCH_FROM Haswell support

[David Carrillo-Cisneros <davidcc@google.com>]

commit 338b522ca43c ("perf/x86/intel: Protect LBR and extra_regs against
KVM lying")
introduced an extra test for LBR support but did not move the dmesg
accordingly. This problem is fixed in first patch in this series.

When a machine that used LBR is rebooted using kexec, the extra test
for LBR support may fail due to a hw bug/quirk in Haswell that generates
a #GPF when restoring a value of MSR_LAST_BRANCH_FROM_* msrs that
has sign extension (e.g. kernel addresses). This hw bug/quirk currently
does not manifest in the context switch of LBR callstack mode because of
a workaround for another LBR bug (bug in FREEZE_LBRS_ON_PMI,
more details in second patch of this series). The workaround deactivates
LBR callstack in kernel mode.

The second and fourth patches in this series contain workarounds for the
MSR_LAST_BRANCH_FROM_* hw bug/quirk.

The third patch contains a trivial format fix for aesthetic uniformity.

The last patch is not to be committed, but to test the fourth patch. It
removes the effect of the FREEZE_LBRS_ON_PMI work-around by allowing
LBR callstack for kernel addresses.

This series is rebased at torvalds/linux/master .


Changes in 2nd version:
  - Remove branch from quirk (as pointed by Peter Z.).
  - Format fixes.

David Carrillo-Cisneros (5):
  perf/x86/intel: output LBR support statement after validation
  perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x bug when no TSX
  perf/x86/intel: trivial format and style fix
  perf/x86/intel: MSR_LAST_BRANCH_FROM_x quirk for ctx switch
  not required, used to test ctxsw, do not merge

 arch/x86/events/intel/core.c | 20 ++++++++++
 arch/x86/events/intel/lbr.c  | 90 ++++++++++++++++++++++++++++++++++++--------
 arch/x86/events/perf_event.h |  2 +
 tools/perf/util/evsel.c      | 17 +++++++--
 4 files changed, 111 insertions(+), 18 deletions(-)

-- 
2.8.0.rc3.226.g39d4020