diff for duplicates of <1467232362.3733.23.camel@intel.com> diff --git a/N1/1.1.hdr b/N1/1.1.hdr new file mode 100644 index 0000000..9a40e9f --- /dev/null +++ b/N1/1.1.hdr @@ -0,0 +1,2 @@ +Content-Type: text/plain; charset="UTF-8" +Content-Transfer-Encoding: quoted-printable diff --git a/a/1.txt b/N1/1.1.txt similarity index 78% rename from a/1.txt rename to N1/1.1.txt index ea77b9c..f97bc6d 100644 --- a/a/1.txt +++ b/N1/1.1.txt @@ -1,48 +1,41 @@ On Wed, 2016-06-29 at 13:18 -0700, Greg wrote: > On Wed, 2016-06-29 at 13:05 -0700, tndave wrote: > > Hi, -> >? +> > > > Running iperf tcp test on 2 sparc systems with i40e connected back to > > back, I see huge number of 'port.rx_dropped' (on iperf server). Based > on > > past experience with ixgbe, this could very well because of PCIe RO > > (relaxed ordering) not enabled. -> >? +> > > > I am trying to confirm RO is enabled. i40e datasheet mentioned RO > > settings in 3 different sections: -> >? +> > > > 1. section 10.2.2.2.38 PCIe Global Config 2 - GLPCI_CNF2 register > > contains global status fields of PCIe configuration. The bit 0 of the > > register is "RO_DIS". If this bit is set to 1 RO is disabled. -> >? +> > > > RO_DIS in my setup is 0 imply RO is not disabled. -> >? +> > > > 2. section 12.3.5.5 Device Control Register (0xA8; RW) has bit 4 > > that enable/disable RO. This is pcie cap register. -> >? +> > > > In my i40e pcie config space value at offset 0xA8 is "2110". i.e 4th > bit > > set to 1 imply RO is enabled. -> >? +> > > > 3. section 3.1.2.7.2 mentions some relaxed ordering rules > > e.g. "The GLLAN_RCTL.RXDESCRDROEN bit (loaded from NVM) enables relaxed > > ordering for Rx descriptor reads" -> >? +> > > > However, GLLAN_RCTL register definition has not bit like RXDESCRDROEN. > > Same goes for GLLAN_TCTL.TXDESCRDROEN. -> >? +> > > > Am I missing anything? please advise. > > I would try posting this question to the e1000 developer list over at -> Source Forge.? The Intel customer support folks used to monitor that +> Source Forge. The Intel customer support folks used to monitor that > list closely when I was there, hopefully they still are. We are supposed to be monitoring both lists, but just in case I have added e1000-devel list... --------------- next part -------------- -A non-text attachment was scrubbed... -Name: signature.asc -Type: application/pgp-signature -Size: 819 bytes -Desc: This is a digitally signed message part -URL: <http://lists.osuosl.org/pipermail/intel-wired-lan/attachments/20160629/401d5a31/attachment.asc> diff --git a/N1/1.2.bin b/N1/1.2.bin new file mode 100644 index 0000000..8514bf7 --- /dev/null +++ b/N1/1.2.bin @@ -0,0 +1,17 @@ +-----BEGIN PGP SIGNATURE----- +Version: GnuPG v2 + +iQIcBAABCgAGBQJXdDBrAAoJEOVv75VaS+3OwJkQAKQKZv9QiPk3wDYgMRxAY0eS +ebyiiG0l709UgM3c8a5twZUwpMFoHlUI7kWwhnQfISu0EFhaxNI+VyDxiEnJHVKc +Ey8QNzHc1oi+/FmLy+KYA4+xhWPaffaoVoFkkrgH4TtcjHOrL6jl9g8la66ivwbJ +XIkY3SLiBt21oeg/5Q5WmzMrOduyxaQ8NpkibamNknU79EKUReMyzwmbyAVTn8Bb +y2jOhP7Ubq27jsxFx6j8f6Sy7rlgbmy5S+sGxZmSyikrWhwMWoXy51e9pAS4qMYq +4hKBXmaRXyWD2tCWPxqom/cV/UwOlq7IC1IcrppVYWO9iiP0si7B8ZtFs5I26Jof +9oAxloQSNUgEudukqGklVWhCXrGVgz3h+R/jH5NVsE1Pbud3qZvQtYtXaks4FKuE +kPv7bDXiHXg15sNQxfB0svG/oxHejBtM/pxEZj3ciMxQzBVfh/3t/2yV8p+JFGV5 +F3CRWpS4EPjvLMFsBdGHWLwhsOv51y0uDHs5CBPaD2OEI8gZ4IUWQkQ5z+8oGsJ1 +Y6FsaLT86guRHUuxC5Z4l4U7G8gIk/tZtjPvepByyKSCx0yN3GQWL4I8AFnmBRWB +W6PbDZgMuOnA+xCqQFZIb5tUKJGx28+L0ktmOHJBAbZJd0ZRU+DIDJV9AgaHFTE9 +2grZap5BuK9+KyzI+Rek +=AvI9 +-----END PGP SIGNATURE----- diff --git a/N1/1.2.hdr b/N1/1.2.hdr new file mode 100644 index 0000000..da6d245 --- /dev/null +++ b/N1/1.2.hdr @@ -0,0 +1,3 @@ +Content-Type: application/pgp-signature; name="signature.asc" +Content-Description: This is a digitally signed message part +Content-Transfer-Encoding: 7bit diff --git a/N1/2.hdr b/N1/2.hdr new file mode 100644 index 0000000..4b86001 --- /dev/null +++ b/N1/2.hdr @@ -0,0 +1,4 @@ +Content-Type: text/plain; charset="us-ascii" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Content-Disposition: inline diff --git a/N1/2.txt b/N1/2.txt new file mode 100644 index 0000000..2872662 --- /dev/null +++ b/N1/2.txt @@ -0,0 +1,6 @@ +------------------------------------------------------------------------------ +Attend Shape: An AT&T Tech Expo July 15-16. Meet us at AT&T Park in San +Francisco, CA to explore cutting-edge tech and listen to tech luminaries +present their vision of the future. This family event has something for +everyone, including kids. Get more information and register today. +http://sdm.link/attshape diff --git a/N1/3.hdr b/N1/3.hdr new file mode 100644 index 0000000..4b86001 --- /dev/null +++ b/N1/3.hdr @@ -0,0 +1,4 @@ +Content-Type: text/plain; charset="us-ascii" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Content-Disposition: inline diff --git a/N1/3.txt b/N1/3.txt new file mode 100644 index 0000000..d563f81 --- /dev/null +++ b/N1/3.txt @@ -0,0 +1,5 @@ +_______________________________________________ +E1000-devel mailing list +E1000-devel@lists.sourceforge.net +https://lists.sourceforge.net/lists/listinfo/e1000-devel +To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired diff --git a/a/content_digest b/N1/content_digest index a052100..4e36b25 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,58 +1,91 @@ "ref\057742A27.5040207@oracle.com\0" "ref\01467231519.3404.11.camel@gmail.com\0" "From\0Jeff Kirsher <jeffrey.t.kirsher@intel.com>\0" - "Subject\0[Intel-wired-lan] Question on i40e PCIe relaxed ordering (RO)\0" + "Subject\0Re: Question on i40e PCIe relaxed ordering (RO)\0" "Date\0Wed, 29 Jun 2016 13:32:42 -0700\0" - "To\0intel-wired-lan@osuosl.org\0" - "\00:1\0" + "To\0Greg <gvrose8192@gmail.com>" + " tndave <tushar.n.dave@oracle.com>\0" + "Cc\0netdev <netdev@vger.kernel.org>" + e1000-devel@lists.sf.net <e1000-devel@lists.sf.net> + " intel-wired-lan@lists.osuosl.org\0" + "\02:1.1\0" "b\0" "On Wed, 2016-06-29 at 13:18 -0700, Greg wrote:\n" "> On Wed, 2016-06-29 at 13:05 -0700, tndave wrote:\n" "> > Hi,\n" - "> >?\n" + "> >\302\240\n" "> > Running iperf tcp test on 2 sparc systems with i40e connected back to\n" "> > back, I see huge number of 'port.rx_dropped' (on iperf server). Based\n" "> on\n" "> > past experience with ixgbe, this could very well because of PCIe RO\n" "> > (relaxed ordering) not enabled.\n" - "> >?\n" + "> >\302\240\n" "> > I am trying to confirm RO is enabled. i40e datasheet mentioned RO\n" "> > settings in 3 different sections:\n" - "> >?\n" + "> >\302\240\n" "> > 1. section 10.2.2.2.38 PCIe Global Config 2 - GLPCI_CNF2 register\n" "> > contains global status fields of PCIe configuration. The bit 0 of the\n" "> > register is \"RO_DIS\". If this bit is set to 1 RO is disabled.\n" - "> >?\n" + "> >\302\240\n" "> > RO_DIS in my setup is 0 imply RO is not disabled.\n" - "> >?\n" + "> >\302\240\n" "> > 2. section 12.3.5.5 Device Control Register (0xA8; RW) has bit 4\n" "> > that enable/disable RO. This is pcie cap register.\n" - "> >?\n" + "> >\302\240\n" "> > In my i40e pcie config space value at offset 0xA8 is \"2110\". i.e 4th\n" "> bit\n" "> > set to 1 imply RO is enabled.\n" - "> >?\n" + "> >\302\240\n" "> > 3. section 3.1.2.7.2 mentions some relaxed ordering rules\n" "> > e.g. \"The GLLAN_RCTL.RXDESCRDROEN bit (loaded from NVM) enables relaxed\n" "> > ordering for Rx descriptor reads\"\n" - "> >?\n" + "> >\302\240\n" "> > However, GLLAN_RCTL register definition has not bit like RXDESCRDROEN.\n" "> > Same goes for GLLAN_TCTL.TXDESCRDROEN.\n" - "> >?\n" + "> >\302\240\n" "> > Am I missing anything? please advise.\n" "> \n" "> I would try posting this question to the e1000 developer list over at\n" - "> Source Forge.? The Intel customer support folks used to monitor that\n" + "> Source Forge.\302\240 The Intel customer support folks used to monitor that\n" "> list closely when I was there, hopefully they still are.\n" "\n" "We are supposed to be monitoring both lists, but just in case I have added\n" - "e1000-devel list...\n" - "-------------- next part --------------\n" - "A non-text attachment was scrubbed...\n" - "Name: signature.asc\n" - "Type: application/pgp-signature\n" - "Size: 819 bytes\n" - "Desc: This is a digitally signed message part\n" - URL: <http://lists.osuosl.org/pipermail/intel-wired-lan/attachments/20160629/401d5a31/attachment.asc> + e1000-devel list... + "\02:1.2\0" + "fn\0signature.asc\0" + "d\0This is a digitally signed message part\0" + "b\0" + "-----BEGIN PGP SIGNATURE-----\n" + "Version: GnuPG v2\n" + "\n" + "iQIcBAABCgAGBQJXdDBrAAoJEOVv75VaS+3OwJkQAKQKZv9QiPk3wDYgMRxAY0eS\n" + "ebyiiG0l709UgM3c8a5twZUwpMFoHlUI7kWwhnQfISu0EFhaxNI+VyDxiEnJHVKc\n" + "Ey8QNzHc1oi+/FmLy+KYA4+xhWPaffaoVoFkkrgH4TtcjHOrL6jl9g8la66ivwbJ\n" + "XIkY3SLiBt21oeg/5Q5WmzMrOduyxaQ8NpkibamNknU79EKUReMyzwmbyAVTn8Bb\n" + "y2jOhP7Ubq27jsxFx6j8f6Sy7rlgbmy5S+sGxZmSyikrWhwMWoXy51e9pAS4qMYq\n" + "4hKBXmaRXyWD2tCWPxqom/cV/UwOlq7IC1IcrppVYWO9iiP0si7B8ZtFs5I26Jof\n" + "9oAxloQSNUgEudukqGklVWhCXrGVgz3h+R/jH5NVsE1Pbud3qZvQtYtXaks4FKuE\n" + "kPv7bDXiHXg15sNQxfB0svG/oxHejBtM/pxEZj3ciMxQzBVfh/3t/2yV8p+JFGV5\n" + "F3CRWpS4EPjvLMFsBdGHWLwhsOv51y0uDHs5CBPaD2OEI8gZ4IUWQkQ5z+8oGsJ1\n" + "Y6FsaLT86guRHUuxC5Z4l4U7G8gIk/tZtjPvepByyKSCx0yN3GQWL4I8AFnmBRWB\n" + "W6PbDZgMuOnA+xCqQFZIb5tUKJGx28+L0ktmOHJBAbZJd0ZRU+DIDJV9AgaHFTE9\n" + "2grZap5BuK9+KyzI+Rek\n" + "=AvI9\n" + "-----END PGP SIGNATURE-----\n" + "\01:2\0" + "b\0" + "------------------------------------------------------------------------------\n" + "Attend Shape: An AT&T Tech Expo July 15-16. Meet us at AT&T Park in San\n" + "Francisco, CA to explore cutting-edge tech and listen to tech luminaries\n" + "present their vision of the future. This family event has something for\n" + "everyone, including kids. Get more information and register today.\n" + http://sdm.link/attshape + "\01:3\0" + "b\0" + "_______________________________________________\n" + "E1000-devel mailing list\n" + "E1000-devel@lists.sourceforge.net\n" + "https://lists.sourceforge.net/lists/listinfo/e1000-devel\n" + To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired -3246a4f78115dbc9b4899d9cb594c0dea7848f830f1eabb8f6dac4908a05da8f +d9b1d548440f603645d822dc4179b76e734737e833de41b3e8e855f246980ec6
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