From mboxrd@z Thu Jan 1 00:00:00 1970 From: oss@buserror.net (Scott Wood) Date: Fri, 01 Jul 2016 01:51:45 -0500 Subject: [PATCH v2 1/2] ARM64: arch_timer: Work around QorIQ Erratum A-008585 In-Reply-To: <5771267D.7030102@arm.com> References: <1463114260-8724-1-git-send-email-oss@buserror.net> <20160513112441.200f4349@arm.com> <1466559926.22191.203.camel@buserror.net> <5771267D.7030102@arm.com> Message-ID: <1467355905.32358.31.camel@buserror.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, 2016-06-27 at 14:13 +0100, Marc Zyngier wrote: > On 22/06/16 02:45, Scott Wood wrote: > > > > On Fri, 2016-05-13 at 11:24 +0100, Marc Zyngier wrote: > > > > > > On Thu, 12 May 2016 23:37:39 -0500 > > > Scott Wood wrote: > > > > > > > +#ifdef CONFIG_ARM64 > > > > +static __always_inline void rewrite_tval(const int access, > > > > + unsigned long evt, struct clock_event_device *clk) > > > > +{ > > > > + u64 cval_old, cval_new; > > > > + int timeout = 200; > > > > + > > > > + do { > > > > + cval_old = __arch_counter_get_cntvct(); > > > > + arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, > > > > evt, > > > > clk); > > > > + cval_new = __arch_counter_get_cntvct(); > > > Don't you need to guarantee the order of accesses here? > > I'm not 100% sure.??The erratum workaround sample code doesn't show any > > barriers, and adding more barriers could make it harder for the loop to > > successfully complete.??There's already a barrier after the write, so the > > only > > concern should be whether the timer read could be reordered after the > > timer > > write, which could cause the loop to exit even if the write was bad.??Do > > you > > know if A53 or A57 will reorder a counter read relative to a tval write? > I can't see any absolute guarantee that they wouldn't be reordered (but > I have no insight on the micro-architecture either). I'd rather err on > the side of caution here. Adding another isb() before arch_timer_reg_write() causes the loop to not complete with any reasonable timeout. ?A testing loop (that repeatedly writes to TVAL (using the workaround code), reads it back, and checks that the value read back is not greater than the value that was written) shows that the workaround without the extra isb() is effective -- lots of assertions without the workaround, and none with it -- but I'll go with the cval workaround instead. -Scott From mboxrd@z Thu Jan 1 00:00:00 1970 From: Scott Wood Subject: Re: [PATCH v2 1/2] ARM64: arch_timer: Work around QorIQ Erratum A-008585 Date: Fri, 01 Jul 2016 01:51:45 -0500 Message-ID: <1467355905.32358.31.camel@buserror.net> References: <1463114260-8724-1-git-send-email-oss@buserror.net> <20160513112441.200f4349@arm.com> <1466559926.22191.203.camel@buserror.net> <5771267D.7030102@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <5771267D.7030102@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Marc Zyngier Cc: Catalin Marinas , Will Deacon , stuart.yoder@nxp.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org T24gTW9uLCAyMDE2LTA2LTI3IGF0IDE0OjEzICswMTAwLCBNYXJjIFp5bmdpZXIgd3JvdGU6Cj4g T24gMjIvMDYvMTYgMDI6NDUsIFNjb3R0IFdvb2Qgd3JvdGU6Cj4gPiAKPiA+IE9uIEZyaSwgMjAx Ni0wNS0xMyBhdCAxMToyNCArMDEwMCwgTWFyYyBaeW5naWVyIHdyb3RlOgo+ID4gPiAKPiA+ID4g T24gVGh1LCAxMiBNYXkgMjAxNiAyMzozNzozOSAtMDUwMAo+ID4gPiBTY290dCBXb29kIDxvc3NA YnVzZXJyb3IubmV0PiB3cm90ZToKPiA+ID4gCj4gPiA+ID4gKyNpZmRlZiBDT05GSUdfQVJNNjQK PiA+ID4gPiArc3RhdGljIF9fYWx3YXlzX2lubGluZSB2b2lkIHJld3JpdGVfdHZhbChjb25zdCBp bnQgYWNjZXNzLAo+ID4gPiA+ICsJCXVuc2lnbmVkIGxvbmcgZXZ0LCBzdHJ1Y3QgY2xvY2tfZXZl bnRfZGV2aWNlICpjbGspCj4gPiA+ID4gK3sKPiA+ID4gPiArCXU2NCBjdmFsX29sZCwgY3ZhbF9u ZXc7Cj4gPiA+ID4gKwlpbnQgdGltZW91dCA9IDIwMDsKPiA+ID4gPiArCj4gPiA+ID4gKwlkbyB7 Cj4gPiA+ID4gKwkJY3ZhbF9vbGQgPSBfX2FyY2hfY291bnRlcl9nZXRfY250dmN0KCk7Cj4gPiA+ ID4gKwkJYXJjaF90aW1lcl9yZWdfd3JpdGUoYWNjZXNzLCBBUkNIX1RJTUVSX1JFR19UVkFMLAo+ ID4gPiA+IGV2dCwKPiA+ID4gPiBjbGspOwo+ID4gPiA+ICsJCWN2YWxfbmV3ID0gX19hcmNoX2Nv dW50ZXJfZ2V0X2NudHZjdCgpOwo+ID4gPiBEb24ndCB5b3UgbmVlZCB0byBndWFyYW50ZWUgdGhl IG9yZGVyIG9mIGFjY2Vzc2VzIGhlcmU/Cj4gPiBJJ20gbm90IDEwMCUgc3VyZS7CoMKgVGhlIGVy cmF0dW0gd29ya2Fyb3VuZCBzYW1wbGUgY29kZSBkb2Vzbid0IHNob3cgYW55Cj4gPiBiYXJyaWVy cywgYW5kIGFkZGluZyBtb3JlIGJhcnJpZXJzIGNvdWxkIG1ha2UgaXQgaGFyZGVyIGZvciB0aGUg bG9vcCB0bwo+ID4gc3VjY2Vzc2Z1bGx5IGNvbXBsZXRlLsKgwqBUaGVyZSdzIGFscmVhZHkgYSBi YXJyaWVyIGFmdGVyIHRoZSB3cml0ZSwgc28gdGhlCj4gPiBvbmx5Cj4gPiBjb25jZXJuIHNob3Vs ZCBiZSB3aGV0aGVyIHRoZSB0aW1lciByZWFkIGNvdWxkIGJlIHJlb3JkZXJlZCBhZnRlciB0aGUK PiA+IHRpbWVyCj4gPiB3cml0ZSwgd2hpY2ggY291bGQgY2F1c2UgdGhlIGxvb3AgdG8gZXhpdCBl dmVuIGlmIHRoZSB3cml0ZSB3YXMgYmFkLsKgwqBEbwo+ID4geW91Cj4gPiBrbm93IGlmIEE1MyBv ciBBNTcgd2lsbCByZW9yZGVyIGEgY291bnRlciByZWFkIHJlbGF0aXZlIHRvIGEgdHZhbCB3cml0 ZT8KPiBJIGNhbid0IHNlZSBhbnkgYWJzb2x1dGUgZ3VhcmFudGVlIHRoYXQgdGhleSB3b3VsZG4n dCBiZSByZW9yZGVyZWQgKGJ1dAo+IEkgaGF2ZSBubyBpbnNpZ2h0IG9uIHRoZSBtaWNyby1hcmNo aXRlY3R1cmUgZWl0aGVyKS4gSSdkIHJhdGhlciBlcnIgb24KPiB0aGUgc2lkZSBvZiBjYXV0aW9u IGhlcmUuCgpBZGRpbmcgYW5vdGhlciBpc2IoKSBiZWZvcmUgYXJjaF90aW1lcl9yZWdfd3JpdGUo KSBjYXVzZXMgdGhlIGxvb3AgdG8gbm90CmNvbXBsZXRlIHdpdGggYW55IHJlYXNvbmFibGUgdGlt ZW91dC4gwqBBIHRlc3RpbmcgbG9vcCAodGhhdCByZXBlYXRlZGx5IHdyaXRlcwp0byBUVkFMICh1 c2luZyB0aGUgd29ya2Fyb3VuZCBjb2RlKSwgcmVhZHMgaXQgYmFjaywgYW5kIGNoZWNrcyB0aGF0 IHRoZSB2YWx1ZQpyZWFkIGJhY2sgaXMgbm90IGdyZWF0ZXIgdGhhbiB0aGUgdmFsdWUgdGhhdCB3 YXMgd3JpdHRlbikgc2hvd3MgdGhhdCB0aGUKd29ya2Fyb3VuZCB3aXRob3V0IHRoZSBleHRyYSBp c2IoKSBpcyBlZmZlY3RpdmUgLS0gbG90cyBvZiBhc3NlcnRpb25zIHdpdGhvdXQKdGhlIHdvcmth cm91bmQsIGFuZCBub25lIHdpdGggaXQgLS0gYnV0IEknbGwgZ28gd2l0aCB0aGUgY3ZhbCB3b3Jr YXJvdW5kCmluc3RlYWQuCgotU2NvdHQKCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0t a2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFp bG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg==