diff for duplicates of <1467913182.32358.68.camel@buserror.net> diff --git a/a/1.txt b/N1/1.txt index a6ff22d..e902451 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -22,14 +22,19 @@ On Thu, 2016-07-07 at 20:59 +0800, Ding Tianhong wrote: > > the two reads are *always* done in the right timing window? > > > The timer counter only use 56 bits in aarch64, my chip would change one of -> the higher? +> the higher > bit(55 to 3) to a wrong value when occur bug, so there will be more than 8 > cycles between > correct value and wrong value from the timer counter. Maybe Scott's problem > is not just like > mine. -It's not like yours. ?Most errors I saw were time going backwards by 1, 3, or +It's not like yours. Most errors I saw were time going backwards by 1, 3, or 7 cycles (with occasional larger errors). -Scott + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 74051b1..59c55d1 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -5,10 +5,17 @@ "ref\0577E3EF2.9080105@huawei.com\0" "ref\0577E424C.5030908@arm.com\0" "ref\0577E524F.3030403@huawei.com\0" - "From\0oss@buserror.net (Scott Wood)\0" - "Subject\0[PATCH v3 3/3] arm64: arch_timer: Work around QorIQ Erratum A-008585\0" + "ref\0577E524F.3030403-hv44wF8Li93QT0dZR+AlfA@public.gmane.org\0" + "From\0Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>\0" + "Subject\0Re: [PATCH v3 3/3] arm64: arch_timer: Work around QorIQ Erratum A-008585\0" "Date\0Thu, 07 Jul 2016 12:39:42 -0500\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>" + Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> + Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> + " Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\0" + "Cc\0devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" + stuart.yoder-3arQi8VN3Tc@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "On Thu, 2016-07-07 at 20:59 +0800, Ding Tianhong wrote:\n" @@ -35,16 +42,21 @@ "> > the two reads are *always* done in the right timing window?\n" "> > \n" "> The timer counter only use 56 bits in aarch64, my chip would change one of\n" - "> the higher?\n" + "> the higher\302\240\n" "> bit(55 to 3) to a wrong value when occur bug, so there will be more than 8\n" "> cycles between\n" "> correct value and wrong value from the timer counter. Maybe Scott's problem\n" "> is not just like\n" "> mine.\n" "\n" - "It's not like yours. ?Most errors I saw were time going backwards by 1, 3, or\n" + "It's not like yours. \302\240Most errors I saw were time going backwards by 1, 3, or\n" "7 cycles (with occasional larger errors).\n" "\n" - -Scott + "-Scott\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -8a326d22620cf6e3b8134348fd7f547601473f332e823d6bf3c1ce28ae9e6e3d +f0add68d04b083e246fff1a2cb362330bb2e36eb30e578858be2ccd31b706511
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