diff for duplicates of <1467944442.27479.155.camel@neuling.org> diff --git a/a/1.txt b/N1/1.txt index e4fe36e..b743a34 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,13 +1,12 @@ -> diff --git a/arch/powerpc/include/asm/cpuidle.h b/arch/powerpc/include/as= -m/cpuidle.h +> diff --git a/arch/powerpc/include/asm/cpuidle.h b/arch/powerpc/include/asm/cpuidle.h > index d2f99ca..3d7fc06 100644 > --- a/arch/powerpc/include/asm/cpuidle.h > +++ b/arch/powerpc/include/asm/cpuidle.h > @@ -13,6 +13,8 @@ -> =C2=A0#ifndef __ASSEMBLY__ -> =C2=A0extern u32 pnv_fastsleep_workaround_at_entry[]; -> =C2=A0extern u32 pnv_fastsleep_workaround_at_exit[]; +> #ifndef __ASSEMBLY__ +> extern u32 pnv_fastsleep_workaround_at_entry[]; +> extern u32 pnv_fastsleep_workaround_at_exit[]; > + > +extern u64 pnv_first_deep_stop_state; @@ -15,63 +14,61 @@ mpe asked a question about this which you neither answered or addressed. "Should this have some safe initial value?" I'm thinking we could do this which is what you have in the init call. -=C2=A0 =C2=A0u64 pnv_first_deep_stop_state =3D=C2=A0MAX_STOP_STATE; + u64 pnv_first_deep_stop_state = MAX_STOP_STATE; > @@ -439,7 +540,18 @@ timebase_resync: -> =C2=A0 =C2=A0*/ -> =C2=A0 bne cr4,clear_lock -> =C2=A0 +> */ +> bne cr4,clear_lock +> > - /* Restore per core state */ > + /* -> + =C2=A0* First thread in the core to wake up and its waking up with -> + =C2=A0* complete hypervisor state loss. Restore per core hypervisor -> + =C2=A0* state. -> + =C2=A0*/ +> + * First thread in the core to wake up and its waking up with +> + * complete hypervisor state loss. Restore per core hypervisor +> + * state. +> + */ > +BEGIN_FTR_SECTION > + ld r4,_PTCR(r1) > + mtspr SPRN_PTCR,r4 > + ld r4,_RPR(r1) > + mtspr SPRN_RPR,r4 -RPR looks wrong here. =C2=A0This should be on POWER8 too. +RPR looks wrong here. This should be on POWER8 too. -This has changed since v6 and not noted in the v7 comments. =C2=A0Why are y= -ou +This has changed since v6 and not noted in the v7 comments. Why are you changing this now? > +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) > + -> =C2=A0 ld r4,_TSCR(r1) -> =C2=A0 mtspr SPRN_TSCR,r4 -> =C2=A0 ld r4,_WORC(r1) +> ld r4,_TSCR(r1) +> mtspr SPRN_TSCR,r4 +> ld r4,_WORC(r1) > @@ -461,9 +573,7 @@ common_exit: -> =C2=A0 -> =C2=A0 /* Waking up from winkle */ -> =C2=A0 +> +> /* Waking up from winkle */ +> > - /* Restore per thread state */ > - bl __restore_cpu_power8 > - > +BEGIN_MMU_FTR_SECTION -> =C2=A0 /* Restore SLB=C2=A0=C2=A0from PACA */ -> =C2=A0 ld r8,PACA_SLBSHADOWPTR(r13) -> =C2=A0 +> /* Restore SLB from PACA */ +> ld r8,PACA_SLBSHADOWPTR(r13) +> > @@ -477,6 +587,9 @@ common_exit: -> =C2=A0 slbmte r6,r5 -> =C2=A01: addi r8,r8,16 -> =C2=A0 .endr +> slbmte r6,r5 +> 1: addi r8,r8,16 +> .endr > +END_MMU_FTR_SECTION_IFCLR(MMU_FTR_RADIX) > + > + /* Restore per thread state */ -This FTR section is too big =C2=A0It ends up at 25 instructions with the lo= -op. +This FTR section is too big It ends up at 25 instructions with the loop. Probably better like this: BEGIN_MMU_FTR_SECTION b no_segments END_MMU_FTR_SECTION_IFSET(MMU_FTR_RADIX) - /* Restore SLB=C2=A0=C2=A0from PACA */ + /* Restore SLB from PACA */ ld r8,PACA_SLBSHADOWPTR(r13) .rept SLB_NUM_BOLTED diff --git a/a/content_digest b/N1/content_digest index 41280cf..d0341e2 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -14,15 +14,14 @@ "\00:1\0" "b\0" "\n" - "> diff --git a/arch/powerpc/include/asm/cpuidle.h b/arch/powerpc/include/as=\n" - "m/cpuidle.h\n" + "> diff --git a/arch/powerpc/include/asm/cpuidle.h b/arch/powerpc/include/asm/cpuidle.h\n" "> index d2f99ca..3d7fc06 100644\n" "> --- a/arch/powerpc/include/asm/cpuidle.h\n" "> +++ b/arch/powerpc/include/asm/cpuidle.h\n" "> @@ -13,6 +13,8 @@\n" - "> =C2=A0#ifndef __ASSEMBLY__\n" - "> =C2=A0extern u32 pnv_fastsleep_workaround_at_entry[];\n" - "> =C2=A0extern u32 pnv_fastsleep_workaround_at_exit[];\n" + "> \302\240#ifndef __ASSEMBLY__\n" + "> \302\240extern u32 pnv_fastsleep_workaround_at_entry[];\n" + "> \302\240extern u32 pnv_fastsleep_workaround_at_exit[];\n" "> +\n" "> +extern u64 pnv_first_deep_stop_state;\n" "\n" @@ -30,63 +29,61 @@ "\"Should this have some safe initial value?\"\n" "\n" "I'm thinking we could do this which is what you have in the init call.\n" - "=C2=A0 =C2=A0u64 pnv_first_deep_stop_state =3D=C2=A0MAX_STOP_STATE;\n" + "\302\240 \302\240u64 pnv_first_deep_stop_state =\302\240MAX_STOP_STATE;\n" "\n" "\n" "> @@ -439,7 +540,18 @@ timebase_resync:\n" - "> =C2=A0\t=C2=A0*/\n" - "> =C2=A0\tbne\tcr4,clear_lock\n" - "> =C2=A0\n" + "> \302\240\t\302\240*/\n" + "> \302\240\tbne\tcr4,clear_lock\n" + "> \302\240\n" "> -\t/* Restore per core state */\n" "> +\t/*\n" - "> +\t=C2=A0* First thread in the core to wake up and its waking up with\n" - "> +\t=C2=A0* complete hypervisor state loss. Restore per core hypervisor\n" - "> +\t=C2=A0* state.\n" - "> +\t=C2=A0*/\n" + "> +\t\302\240* First thread in the core to wake up and its waking up with\n" + "> +\t\302\240* complete hypervisor state loss. Restore per core hypervisor\n" + "> +\t\302\240* state.\n" + "> +\t\302\240*/\n" "> +BEGIN_FTR_SECTION\n" "> +\tld\tr4,_PTCR(r1)\n" "> +\tmtspr\tSPRN_PTCR,r4\n" "> +\tld\tr4,_RPR(r1)\n" "> +\tmtspr\tSPRN_RPR,r4\n" "\n" - "RPR looks wrong here. =C2=A0This should be on POWER8 too.\n" + "RPR looks wrong here. \302\240This should be on POWER8 too.\n" "\n" - "This has changed since v6 and not noted in the v7 comments. =C2=A0Why are y=\n" - "ou\n" + "This has changed since v6 and not noted in the v7 comments. \302\240Why are you\n" "changing this now?\n" "\n" "> +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)\n" "> +\n" - "> =C2=A0\tld\tr4,_TSCR(r1)\n" - "> =C2=A0\tmtspr\tSPRN_TSCR,r4\n" - "> =C2=A0\tld\tr4,_WORC(r1)\n" + "> \302\240\tld\tr4,_TSCR(r1)\n" + "> \302\240\tmtspr\tSPRN_TSCR,r4\n" + "> \302\240\tld\tr4,_WORC(r1)\n" "> @@ -461,9 +573,7 @@ common_exit:\n" - "> =C2=A0\n" - "> =C2=A0\t/* Waking up from winkle */\n" - "> =C2=A0\n" + "> \302\240\n" + "> \302\240\t/* Waking up from winkle */\n" + "> \302\240\n" "> -\t/* Restore per thread state */\n" "> -\tbl\t__restore_cpu_power8\n" "> -\n" "> +BEGIN_MMU_FTR_SECTION\n" - "> =C2=A0\t/* Restore SLB=C2=A0=C2=A0from PACA */\n" - "> =C2=A0\tld\tr8,PACA_SLBSHADOWPTR(r13)\n" - "> =C2=A0\n" + "> \302\240\t/* Restore SLB\302\240\302\240from PACA */\n" + "> \302\240\tld\tr8,PACA_SLBSHADOWPTR(r13)\n" + "> \302\240\n" "> @@ -477,6 +587,9 @@ common_exit:\n" - "> =C2=A0\tslbmte\tr6,r5\n" - "> =C2=A01:\taddi\tr8,r8,16\n" - "> =C2=A0\t.endr\n" + "> \302\240\tslbmte\tr6,r5\n" + "> \302\2401:\taddi\tr8,r8,16\n" + "> \302\240\t.endr\n" "> +END_MMU_FTR_SECTION_IFCLR(MMU_FTR_RADIX)\n" "> +\n" "> +\t/* Restore per thread state */\n" "\n" - "This FTR section is too big =C2=A0It ends up at 25 instructions with the lo=\n" - "op.\n" + "This FTR section is too big \302\240It ends up at 25 instructions with the loop.\n" "Probably better like this:\n" "\n" "BEGIN_MMU_FTR_SECTION\n" "\tb\tno_segments\n" "END_MMU_FTR_SECTION_IFSET(MMU_FTR_RADIX)\n" - "\t/* Restore SLB=C2=A0=C2=A0from PACA */\n" + "\t/* Restore SLB\302\240\302\240from PACA */\n" "\tld\tr8,PACA_SLBSHADOWPTR(r13)\n" "\n" "\t.rept\tSLB_NUM_BOLTED\n" @@ -102,4 +99,4 @@ "\n" no_segments: -8e2dbb4e9ca6d66c6af2d7c4107d8ec09f7332f02fbaa97574ceb28c9558b568 +49b285343c51c50bbdf1f037049f95772daa25ec6ff432e10555d58c4a641255
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