From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yakir Yang Subject: [PATCH v1 4/6] drm/rockchip: dw_hdmi: add RK3399 HDMI support Date: Mon, 11 Jul 2016 19:05:46 +0800 Message-ID: <1468235146-29575-1-git-send-email-ykk@rock-chips.com> References: <1468235079-29152-1-git-send-email-ykk@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1468235079-29152-1-git-send-email-ykk@rock-chips.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Mark Yao , Heiko Stuebner , Rob Herring , Russell King , Philipp Zabel , Andy Yan Cc: devicetree@vger.kernel.org, Daniel Vetter , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Kumar Gala , xhc@rock-chips.com, linux-arm-kernel@lists.infradead.org, Zheng Yang List-Id: linux-rockchip.vger.kernel.org UkszMzk5IGFuZCBSSzMyODggc2hhcmVkIHRoZSBzYW1lIEhETUkgSVAgY29udHJvbGxlciwgb25s eSBzb21lIGxpZ2h0CmRpZmZlcmVuY2Ugd2l0aCBHUkYgY29uZmlndXJlLgoKU2lnbmVkLW9mZi1i eTogWWFraXIgWWFuZyA8eWtrQHJvY2stY2hpcHMuY29tPgotLS0KIC4uLi9kZXZpY2V0cmVlL2Jp bmRpbmdzL2Rpc3BsYXkvYnJpZGdlL2R3X2hkbWkudHh0IHwgIDEgKwogLi4uL2JpbmRpbmdzL2Rp c3BsYXkvcm9ja2NoaXAvZHdfaGRtaS1yb2NrY2hpcC50eHQgfCAgMyArLQogZHJpdmVycy9ncHUv ZHJtL2JyaWRnZS9kdy1oZG1pLmMgICAgICAgICAgICAgICAgICAgfCAgMiArLQogZHJpdmVycy9n cHUvZHJtL3JvY2tjaGlwL2R3X2hkbWktcm9ja2NoaXAuYyAgICAgICAgfCA0NSArKysrKysrKysr KysrKysrKystLS0tCiBpbmNsdWRlL2RybS9icmlkZ2UvZHdfaGRtaS5oICAgICAgICAgICAgICAg ICAgICAgICB8ICA2ICsrKwogNSBmaWxlcyBjaGFuZ2VkLCA0OCBpbnNlcnRpb25zKCspLCA5IGRl bGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5n cy9kaXNwbGF5L2JyaWRnZS9kd19oZG1pLnR4dCBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9i aW5kaW5ncy9kaXNwbGF5L2JyaWRnZS9kd19oZG1pLnR4dAppbmRleCBkYzE0NTJmLi5mNTBkNGQ1 IDEwMDY0NAotLS0gYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZGlzcGxheS9i cmlkZ2UvZHdfaGRtaS50eHQKKysrIGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdz L2Rpc3BsYXkvYnJpZGdlL2R3X2hkbWkudHh0CkBAIC02LDYgKzYsNyBAQCBSZXF1aXJlZCBwcm9w ZXJ0aWVzOgogICAgKiAiZnNsLGlteDZxLWhkbWkiCiAgICAqICJmc2wsaW14NmRsLWhkbWkiCiAg ICAqICJyb2NrY2hpcCxyazMyODgtZHctaGRtaSIKKyAgICogInJvY2tjaGlwLHJrMzM5OS1kdy1o ZG1pIgogLSByZWc6IFBoeXNpY2FsIGJhc2UgYWRkcmVzcyBhbmQgbGVuZ3RoIG9mIHRoZSBjb250 cm9sbGVyJ3MgcmVnaXN0ZXJzLgogLSBpbnRlcnJ1cHRzOiBUaGUgSERNSSBpbnRlcnJ1cHQgbnVt YmVyCiAtIGNsb2NrcywgY2xvY2stbmFtZXMgOiBtdXN0IGhhdmUgdGhlIHBoYW5kbGVzIHRvIHRo ZSBIRE1JIGlhaGIgYW5kIGlzZnIgY2xvY2tzLApkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlvbi9k ZXZpY2V0cmVlL2JpbmRpbmdzL2Rpc3BsYXkvcm9ja2NoaXAvZHdfaGRtaS1yb2NrY2hpcC50eHQg Yi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZGlzcGxheS9yb2NrY2hpcC9kd19o ZG1pLXJvY2tjaGlwLnR4dAppbmRleCA2NjgwOTFmLi40ZTU3M2QyIDEwMDY0NAotLS0gYS9Eb2N1 bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZGlzcGxheS9yb2NrY2hpcC9kd19oZG1pLXJv Y2tjaGlwLnR4dAorKysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZGlzcGxh eS9yb2NrY2hpcC9kd19oZG1pLXJvY2tjaGlwLnR4dApAQCAtMiw3ICsyLDggQEAgUm9ja2NoaXAg c3BlY2lmaWMgZXh0ZW5zaW9ucyB0byB0aGUgU3lub3BzeXMgRGVzaWdud2FyZSBIRE1JCiA9PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PQogCiBSZXF1aXJlZCBwcm9wZXJ0aWVzOgotLSBj b21wYXRpYmxlOiAicm9ja2NoaXAscmszMjg4LWR3LWhkbWkiOworLSBjb21wYXRpYmxlOiAicm9j a2NoaXAscmszMjg4LWR3LWhkbWkiLAorCSAgICAgICJyb2NrY2hpcCxyazMzOTktZHctaGRtaSI7 CiAtIHJlZzogUGh5c2ljYWwgYmFzZSBhZGRyZXNzIGFuZCBsZW5ndGggb2YgdGhlIGNvbnRyb2xs ZXIncyByZWdpc3RlcnMuCiAtIGNsb2NrczogcGhhbmRsZSB0byBoZG1pIGlhaGIgYW5kIGlzZnIg Y2xvY2tzLgogLSBjbG9jay1uYW1lczogc2hvdWxkIGJlICJpYWhiIiAiaXNmciIKZGlmZiAtLWdp dCBhL2RyaXZlcnMvZ3B1L2RybS9icmlkZ2UvZHctaGRtaS5jIGIvZHJpdmVycy9ncHUvZHJtL2Jy aWRnZS9kdy1oZG1pLmMKaW5kZXggNzBiMWY3ZC4uMjlmODU1YSAxMDA2NDQKLS0tIGEvZHJpdmVy cy9ncHUvZHJtL2JyaWRnZS9kdy1oZG1pLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9k dy1oZG1pLmMKQEAgLTgzMyw3ICs4MzMsNyBAQCBzdGF0aWMgaW50IGhkbWlfcGh5X2NvbmZpZ3Vy ZShzdHJ1Y3QgZHdfaGRtaSAqaGRtaSwgdW5zaWduZWQgY2hhciBwcmVwLAogCWR3X2hkbWlfcGh5 X2dlbjJfdHhwd3JvbihoZG1pLCAxKTsKIAlkd19oZG1pX3BoeV9nZW4yX3BkZHEoaGRtaSwgMCk7 CiAKLQlpZiAoaGRtaS0+ZGV2X3R5cGUgPT0gUkszMjg4X0hETUkpCisJaWYgKGlzX3JvY2tjaGlw KGhkbWktPmRldl90eXBlKSkKIAkJZHdfaGRtaV9waHlfZW5hYmxlX3NwYXJlKGhkbWksIDEpOwog CiAJLypXYWl0IGZvciBQSFkgUExMIGxvY2sgKi8KZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2Ry bS9yb2NrY2hpcC9kd19oZG1pLXJvY2tjaGlwLmMgYi9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAv ZHdfaGRtaS1yb2NrY2hpcC5jCmluZGV4IDhjYjllZDIuLjMyOTA5OWIgMTAwNjQ0Ci0tLSBhL2Ry aXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kd19oZG1pLXJvY2tjaGlwLmMKKysrIGIvZHJpdmVycy9n cHUvZHJtL3JvY2tjaGlwL2R3X2hkbWktcm9ja2NoaXAuYwpAQCAtMjEsMTMgKzIxLDE4IEBACiAj aW5jbHVkZSAicm9ja2NoaXBfZHJtX2Rydi5oIgogI2luY2x1ZGUgInJvY2tjaGlwX2RybV92b3Au aCIKIAotI2RlZmluZSBHUkZfU09DX0NPTjYgICAgICAgICAgICAgICAgICAgIDB4MDI1YwotI2Rl ZmluZSBIRE1JX1NFTF9WT1BfTElUICAgICAgICAgICAgICAgICgxIDw8IDQpCisjZGVmaW5lIFJL MzI4OF9HUkZfU09DX0NPTjYJCTB4MDI1QworI2RlZmluZSBSSzMyODhfSERNSV9MQ0RDX1NFTAkJ QklUKDQpCisjZGVmaW5lIFJLMzM5OV9HUkZfU09DX0NPTjIwCQkweDYyNTAKKyNkZWZpbmUgUksz Mzk5X0hETUlfTENEQ19TRUwJCUJJVCg2KQorCisjZGVmaW5lIEhJV09SRF9VUERBVEUodmFsLCBt YXNrKQkodmFsIHwgKG1hc2spIDw8IDE2KQogCiBzdHJ1Y3Qgcm9ja2NoaXBfaGRtaSB7CiAJc3Ry dWN0IGRldmljZSAqZGV2OwogCXN0cnVjdCByZWdtYXAgKnJlZ21hcDsKIAlzdHJ1Y3QgZHJtX2Vu Y29kZXIgZW5jb2RlcjsKKwllbnVtIGR3X2hkbWlfZGV2dHlwZSBkZXZfdHlwZTsKIH07CiAKICNk ZWZpbmUgdG9fcm9ja2NoaXBfaGRtaSh4KQljb250YWluZXJfb2YoeCwgc3RydWN0IHJvY2tjaGlw X2hkbWksIHgpCkBAIC0xOTQsMTYgKzE5OSwzMCBAQCBzdGF0aWMgdm9pZCBkd19oZG1pX3JvY2tj aGlwX2VuY29kZXJfbW9kZV9zZXQoc3RydWN0IGRybV9lbmNvZGVyICplbmNvZGVyLAogc3RhdGlj IHZvaWQgZHdfaGRtaV9yb2NrY2hpcF9lbmNvZGVyX2VuYWJsZShzdHJ1Y3QgZHJtX2VuY29kZXIg KmVuY29kZXIpCiB7CiAJc3RydWN0IHJvY2tjaGlwX2hkbWkgKmhkbWkgPSB0b19yb2NrY2hpcF9o ZG1pKGVuY29kZXIpOworCXUzMiBsY2RzZWxfZ3JmX3JlZywgbGNkc2VsX21hc2s7CiAJdTMyIHZh bDsKIAlpbnQgbXV4OwogCisJc3dpdGNoIChoZG1pLT5kZXZfdHlwZSkgeworCWNhc2UgUkszMjg4 X0hETUk6CisJCWxjZHNlbF9ncmZfcmVnID0gUkszMjg4X0dSRl9TT0NfQ09ONjsKKwkJbGNkc2Vs X21hc2sgPSBSSzMyODhfSERNSV9MQ0RDX1NFTDsKKwkJYnJlYWs7CisJY2FzZSBSSzMzOTlfSERN SToKKwkJbGNkc2VsX2dyZl9yZWcgPSBSSzMzOTlfR1JGX1NPQ19DT04yMDsKKwkJbGNkc2VsX21h c2sgPSBSSzMzOTlfSERNSV9MQ0RDX1NFTDsKKwkJYnJlYWs7CisJZGVmYXVsdDoKKwkJcmV0dXJu OworCX07CisKIAltdXggPSBkcm1fb2ZfZW5jb2Rlcl9hY3RpdmVfZW5kcG9pbnRfaWQoaGRtaS0+ ZGV2LT5vZl9ub2RlLCBlbmNvZGVyKTsKIAlpZiAobXV4KQotCQl2YWwgPSBIRE1JX1NFTF9WT1Bf TElUIHwgKEhETUlfU0VMX1ZPUF9MSVQgPDwgMTYpOworCQl2YWwgPSBISVdPUkRfVVBEQVRFKGxj ZHNlbF9tYXNrLCBsY2RzZWxfbWFzayk7CiAJZWxzZQotCQl2YWwgPSBIRE1JX1NFTF9WT1BfTElU IDw8IDE2OworCQl2YWwgPSBISVdPUkRfVVBEQVRFKDAsIGxjZHNlbF9tYXNrKTsKIAotCXJlZ21h cF93cml0ZShoZG1pLT5yZWdtYXAsIEdSRl9TT0NfQ09ONiwgdmFsKTsKKwlyZWdtYXBfd3JpdGUo aGRtaS0+cmVnbWFwLCBsY2RzZWxfZ3JmX3JlZywgdmFsKTsKIAlkZXZfZGJnKGhkbWktPmRldiwg InZvcCAlcyBvdXRwdXQgdG8gaGRtaVxuIiwKIAkJKG11eCkgPyAiTElUIiA6ICJCSUciKTsKIH0K QEAgLTIyOSw3ICsyNDgsNyBAQCBzdGF0aWMgY29uc3Qgc3RydWN0IGRybV9lbmNvZGVyX2hlbHBl cl9mdW5jcyBkd19oZG1pX3JvY2tjaGlwX2VuY29kZXJfaGVscGVyX2Z1bgogCS5hdG9taWNfY2hl Y2sgPSBkd19oZG1pX3JvY2tjaGlwX2VuY29kZXJfYXRvbWljX2NoZWNrLAogfTsKIAotc3RhdGlj IGNvbnN0IHN0cnVjdCBkd19oZG1pX3BsYXRfZGF0YSByb2NrY2hpcF9oZG1pX2Rydl9kYXRhID0g eworc3RhdGljIGNvbnN0IHN0cnVjdCBkd19oZG1pX3BsYXRfZGF0YSByazMyODhfaGRtaV9kcnZf ZGF0YSA9IHsKIAkubW9kZV92YWxpZCA9IGR3X2hkbWlfcm9ja2NoaXBfbW9kZV92YWxpZCwKIAku bXBsbF9jZmcgICA9IHJvY2tjaGlwX21wbGxfY2ZnLAogCS5jdXJfY3RyICAgID0gcm9ja2NoaXBf Y3VyX2N0ciwKQEAgLTIzNyw5ICsyNTYsMjAgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBkd19oZG1p X3BsYXRfZGF0YSByb2NrY2hpcF9oZG1pX2Rydl9kYXRhID0gewogCS5kZXZfdHlwZSAgID0gUksz Mjg4X0hETUksCiB9OwogCitzdGF0aWMgY29uc3Qgc3RydWN0IGR3X2hkbWlfcGxhdF9kYXRhIHJr MzM5OV9oZG1pX2Rydl9kYXRhID0geworCS5tb2RlX3ZhbGlkID0gZHdfaGRtaV9yb2NrY2hpcF9t b2RlX3ZhbGlkLAorCS5tcGxsX2NmZyAgID0gcm9ja2NoaXBfbXBsbF9jZmcsCisJLmN1cl9jdHIg ICAgPSByb2NrY2hpcF9jdXJfY3RyLAorCS5waHlfY29uZmlnID0gcm9ja2NoaXBfcGh5X2NvbmZp ZywKKwkuZGV2X3R5cGUgICA9IFJLMzM5OV9IRE1JLAorfTsKKwogc3RhdGljIGNvbnN0IHN0cnVj dCBvZl9kZXZpY2VfaWQgZHdfaGRtaV9yb2NrY2hpcF9kdF9pZHNbXSA9IHsKIAl7IC5jb21wYXRp YmxlID0gInJvY2tjaGlwLHJrMzI4OC1kdy1oZG1pIiwKLQkgIC5kYXRhID0gJnJvY2tjaGlwX2hk bWlfZHJ2X2RhdGEKKwkgIC5kYXRhID0gJnJrMzI4OF9oZG1pX2Rydl9kYXRhCisJfSwKKwl7IC5j b21wYXRpYmxlID0gInJvY2tjaGlwLHJrMzM5OS1kdy1oZG1pIiwKKwkgIC5kYXRhID0gJnJrMzM5 OV9oZG1pX2Rydl9kYXRhCiAJfSwKIAl7fSwKIH07CkBAIC0yNjgsNiArMjk4LDcgQEAgc3RhdGlj IGludCBkd19oZG1pX3JvY2tjaGlwX2JpbmQoc3RydWN0IGRldmljZSAqZGV2LCBzdHJ1Y3QgZGV2 aWNlICptYXN0ZXIsCiAJbWF0Y2ggPSBvZl9tYXRjaF9ub2RlKGR3X2hkbWlfcm9ja2NoaXBfZHRf aWRzLCBwZGV2LT5kZXYub2Zfbm9kZSk7CiAJcGxhdF9kYXRhID0gbWF0Y2gtPmRhdGE7CiAJaGRt aS0+ZGV2ID0gJnBkZXYtPmRldjsKKwloZG1pLT5kZXZfdHlwZSA9IHBsYXRfZGF0YS0+ZGV2X3R5 cGU7CiAJZW5jb2RlciA9ICZoZG1pLT5lbmNvZGVyOwogCiAJaXJxID0gcGxhdGZvcm1fZ2V0X2ly cShwZGV2LCAwKTsKZGlmZiAtLWdpdCBhL2luY2x1ZGUvZHJtL2JyaWRnZS9kd19oZG1pLmggYi9p bmNsdWRlL2RybS9icmlkZ2UvZHdfaGRtaS5oCmluZGV4IGJhZTc5ZjMuLjI2YzA2ZDUgMTAwNjQ0 Ci0tLSBhL2luY2x1ZGUvZHJtL2JyaWRnZS9kd19oZG1pLmgKKysrIGIvaW5jbHVkZS9kcm0vYnJp ZGdlL2R3X2hkbWkuaApAQCAtMjUsNiArMjUsNyBAQCBlbnVtIGR3X2hkbWlfZGV2dHlwZSB7CiAJ SU1YNlFfSERNSSwKIAlJTVg2RExfSERNSSwKIAlSSzMyODhfSERNSSwKKwlSSzMzOTlfSERNSSwK IH07CiAKIHN0cnVjdCBkd19oZG1pX21wbGxfY29uZmlnIHsKQEAgLTU2LDYgKzU3LDExIEBAIHN0 cnVjdCBkd19oZG1pX3BsYXRfZGF0YSB7CiAJCQkJCSAgIHN0cnVjdCBkcm1fZGlzcGxheV9tb2Rl ICptb2RlKTsKIH07CiAKK3N0YXRpYyBpbmxpbmUgYm9vbCBpc19yb2NrY2hpcChlbnVtIGR3X2hk bWlfZGV2dHlwZSBkZXZfdHlwZSkKK3sKKwlyZXR1cm4gZGV2X3R5cGUgPT0gUkszMjg4X0hETUkg fHwgZGV2X3R5cGUgPT0gUkszMzk5X0hETUk7Cit9CisKIHZvaWQgZHdfaGRtaV91bmJpbmQoc3Ry dWN0IGRldmljZSAqZGV2LCBzdHJ1Y3QgZGV2aWNlICptYXN0ZXIsIHZvaWQgKmRhdGEpOwogaW50 IGR3X2hkbWlfYmluZChzdHJ1Y3QgZGV2aWNlICpkZXYsIHN0cnVjdCBkZXZpY2UgKm1hc3RlciwK IAkJIHZvaWQgKmRhdGEsIHN0cnVjdCBkcm1fZW5jb2RlciAqZW5jb2RlciwKLS0gCjEuOS4xCgoK X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: ykk@rock-chips.com (Yakir Yang) Date: Mon, 11 Jul 2016 19:05:46 +0800 Subject: [PATCH v1 4/6] drm/rockchip: dw_hdmi: add RK3399 HDMI support In-Reply-To: <1468235079-29152-1-git-send-email-ykk@rock-chips.com> References: <1468235079-29152-1-git-send-email-ykk@rock-chips.com> Message-ID: <1468235146-29575-1-git-send-email-ykk@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org RK3399 and RK3288 shared the same HDMI IP controller, only some light difference with GRF configure. Signed-off-by: Yakir Yang --- .../devicetree/bindings/display/bridge/dw_hdmi.txt | 1 + .../bindings/display/rockchip/dw_hdmi-rockchip.txt | 3 +- drivers/gpu/drm/bridge/dw-hdmi.c | 2 +- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 45 ++++++++++++++++++---- include/drm/bridge/dw_hdmi.h | 6 +++ 5 files changed, 48 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt b/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt index dc1452f..f50d4d5 100644 --- a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt +++ b/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt @@ -6,6 +6,7 @@ Required properties: * "fsl,imx6q-hdmi" * "fsl,imx6dl-hdmi" * "rockchip,rk3288-dw-hdmi" + * "rockchip,rk3399-dw-hdmi" - reg: Physical base address and length of the controller's registers. - interrupts: The HDMI interrupt number - clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks, diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt index 668091f..4e573d2 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt @@ -2,7 +2,8 @@ Rockchip specific extensions to the Synopsys Designware HDMI ================================ Required properties: -- compatible: "rockchip,rk3288-dw-hdmi"; +- compatible: "rockchip,rk3288-dw-hdmi", + "rockchip,rk3399-dw-hdmi"; - reg: Physical base address and length of the controller's registers. - clocks: phandle to hdmi iahb and isfr clocks. - clock-names: should be "iahb" "isfr" diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c index 70b1f7d..29f855a 100644 --- a/drivers/gpu/drm/bridge/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/dw-hdmi.c @@ -833,7 +833,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep, dw_hdmi_phy_gen2_txpwron(hdmi, 1); dw_hdmi_phy_gen2_pddq(hdmi, 0); - if (hdmi->dev_type == RK3288_HDMI) + if (is_rockchip(hdmi->dev_type)) dw_hdmi_phy_enable_spare(hdmi, 1); /*Wait for PHY PLL lock */ diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 8cb9ed2..329099b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -21,13 +21,18 @@ #include "rockchip_drm_drv.h" #include "rockchip_drm_vop.h" -#define GRF_SOC_CON6 0x025c -#define HDMI_SEL_VOP_LIT (1 << 4) +#define RK3288_GRF_SOC_CON6 0x025C +#define RK3288_HDMI_LCDC_SEL BIT(4) +#define RK3399_GRF_SOC_CON20 0x6250 +#define RK3399_HDMI_LCDC_SEL BIT(6) + +#define HIWORD_UPDATE(val, mask) (val | (mask) << 16) struct rockchip_hdmi { struct device *dev; struct regmap *regmap; struct drm_encoder encoder; + enum dw_hdmi_devtype dev_type; }; #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x) @@ -194,16 +199,30 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) { struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); + u32 lcdsel_grf_reg, lcdsel_mask; u32 val; int mux; + switch (hdmi->dev_type) { + case RK3288_HDMI: + lcdsel_grf_reg = RK3288_GRF_SOC_CON6; + lcdsel_mask = RK3288_HDMI_LCDC_SEL; + break; + case RK3399_HDMI: + lcdsel_grf_reg = RK3399_GRF_SOC_CON20; + lcdsel_mask = RK3399_HDMI_LCDC_SEL; + break; + default: + return; + }; + mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); if (mux) - val = HDMI_SEL_VOP_LIT | (HDMI_SEL_VOP_LIT << 16); + val = HIWORD_UPDATE(lcdsel_mask, lcdsel_mask); else - val = HDMI_SEL_VOP_LIT << 16; + val = HIWORD_UPDATE(0, lcdsel_mask); - regmap_write(hdmi->regmap, GRF_SOC_CON6, val); + regmap_write(hdmi->regmap, lcdsel_grf_reg, val); dev_dbg(hdmi->dev, "vop %s output to hdmi\n", (mux) ? "LIT" : "BIG"); } @@ -229,7 +248,7 @@ static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_fun .atomic_check = dw_hdmi_rockchip_encoder_atomic_check, }; -static const struct dw_hdmi_plat_data rockchip_hdmi_drv_data = { +static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { .mode_valid = dw_hdmi_rockchip_mode_valid, .mpll_cfg = rockchip_mpll_cfg, .cur_ctr = rockchip_cur_ctr, @@ -237,9 +256,20 @@ static const struct dw_hdmi_plat_data rockchip_hdmi_drv_data = { .dev_type = RK3288_HDMI, }; +static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { + .mode_valid = dw_hdmi_rockchip_mode_valid, + .mpll_cfg = rockchip_mpll_cfg, + .cur_ctr = rockchip_cur_ctr, + .phy_config = rockchip_phy_config, + .dev_type = RK3399_HDMI, +}; + static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { { .compatible = "rockchip,rk3288-dw-hdmi", - .data = &rockchip_hdmi_drv_data + .data = &rk3288_hdmi_drv_data + }, + { .compatible = "rockchip,rk3399-dw-hdmi", + .data = &rk3399_hdmi_drv_data }, {}, }; @@ -268,6 +298,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node); plat_data = match->data; hdmi->dev = &pdev->dev; + hdmi->dev_type = plat_data->dev_type; encoder = &hdmi->encoder; irq = platform_get_irq(pdev, 0); diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index bae79f3..26c06d5 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -25,6 +25,7 @@ enum dw_hdmi_devtype { IMX6Q_HDMI, IMX6DL_HDMI, RK3288_HDMI, + RK3399_HDMI, }; struct dw_hdmi_mpll_config { @@ -56,6 +57,11 @@ struct dw_hdmi_plat_data { struct drm_display_mode *mode); }; +static inline bool is_rockchip(enum dw_hdmi_devtype dev_type) +{ + return dev_type == RK3288_HDMI || dev_type == RK3399_HDMI; +} + void dw_hdmi_unbind(struct device *dev, struct device *master, void *data); int dw_hdmi_bind(struct device *dev, struct device *master, void *data, struct drm_encoder *encoder, -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758715AbcGKLF5 (ORCPT ); Mon, 11 Jul 2016 07:05:57 -0400 Received: from lucky1.263xmail.com ([211.157.147.132]:34067 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758106AbcGKLFy (ORCPT ); Mon, 11 Jul 2016 07:05:54 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: ykk@rock-chips.com X-FST-TO: mark.yao@rock-chips.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: ykk@rock-chips.com X-UNIQUE-TAG: <586d3b12d4db529e93031d59a5c70989> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Yakir Yang To: Mark Yao , Heiko Stuebner , Rob Herring , Russell King , Philipp Zabel , Andy Yan Cc: David Airlie , Daniel Vetter , Kumar Gala , Zheng Yang , xhc@rock-chips.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Yakir Yang Subject: [PATCH v1 4/6] drm/rockchip: dw_hdmi: add RK3399 HDMI support Date: Mon, 11 Jul 2016 19:05:46 +0800 Message-Id: <1468235146-29575-1-git-send-email-ykk@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1468235079-29152-1-git-send-email-ykk@rock-chips.com> References: <1468235079-29152-1-git-send-email-ykk@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org RK3399 and RK3288 shared the same HDMI IP controller, only some light difference with GRF configure. Signed-off-by: Yakir Yang --- .../devicetree/bindings/display/bridge/dw_hdmi.txt | 1 + .../bindings/display/rockchip/dw_hdmi-rockchip.txt | 3 +- drivers/gpu/drm/bridge/dw-hdmi.c | 2 +- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 45 ++++++++++++++++++---- include/drm/bridge/dw_hdmi.h | 6 +++ 5 files changed, 48 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt b/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt index dc1452f..f50d4d5 100644 --- a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt +++ b/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt @@ -6,6 +6,7 @@ Required properties: * "fsl,imx6q-hdmi" * "fsl,imx6dl-hdmi" * "rockchip,rk3288-dw-hdmi" + * "rockchip,rk3399-dw-hdmi" - reg: Physical base address and length of the controller's registers. - interrupts: The HDMI interrupt number - clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks, diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt index 668091f..4e573d2 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt @@ -2,7 +2,8 @@ Rockchip specific extensions to the Synopsys Designware HDMI ================================ Required properties: -- compatible: "rockchip,rk3288-dw-hdmi"; +- compatible: "rockchip,rk3288-dw-hdmi", + "rockchip,rk3399-dw-hdmi"; - reg: Physical base address and length of the controller's registers. - clocks: phandle to hdmi iahb and isfr clocks. - clock-names: should be "iahb" "isfr" diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c index 70b1f7d..29f855a 100644 --- a/drivers/gpu/drm/bridge/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/dw-hdmi.c @@ -833,7 +833,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep, dw_hdmi_phy_gen2_txpwron(hdmi, 1); dw_hdmi_phy_gen2_pddq(hdmi, 0); - if (hdmi->dev_type == RK3288_HDMI) + if (is_rockchip(hdmi->dev_type)) dw_hdmi_phy_enable_spare(hdmi, 1); /*Wait for PHY PLL lock */ diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 8cb9ed2..329099b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -21,13 +21,18 @@ #include "rockchip_drm_drv.h" #include "rockchip_drm_vop.h" -#define GRF_SOC_CON6 0x025c -#define HDMI_SEL_VOP_LIT (1 << 4) +#define RK3288_GRF_SOC_CON6 0x025C +#define RK3288_HDMI_LCDC_SEL BIT(4) +#define RK3399_GRF_SOC_CON20 0x6250 +#define RK3399_HDMI_LCDC_SEL BIT(6) + +#define HIWORD_UPDATE(val, mask) (val | (mask) << 16) struct rockchip_hdmi { struct device *dev; struct regmap *regmap; struct drm_encoder encoder; + enum dw_hdmi_devtype dev_type; }; #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x) @@ -194,16 +199,30 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) { struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); + u32 lcdsel_grf_reg, lcdsel_mask; u32 val; int mux; + switch (hdmi->dev_type) { + case RK3288_HDMI: + lcdsel_grf_reg = RK3288_GRF_SOC_CON6; + lcdsel_mask = RK3288_HDMI_LCDC_SEL; + break; + case RK3399_HDMI: + lcdsel_grf_reg = RK3399_GRF_SOC_CON20; + lcdsel_mask = RK3399_HDMI_LCDC_SEL; + break; + default: + return; + }; + mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); if (mux) - val = HDMI_SEL_VOP_LIT | (HDMI_SEL_VOP_LIT << 16); + val = HIWORD_UPDATE(lcdsel_mask, lcdsel_mask); else - val = HDMI_SEL_VOP_LIT << 16; + val = HIWORD_UPDATE(0, lcdsel_mask); - regmap_write(hdmi->regmap, GRF_SOC_CON6, val); + regmap_write(hdmi->regmap, lcdsel_grf_reg, val); dev_dbg(hdmi->dev, "vop %s output to hdmi\n", (mux) ? "LIT" : "BIG"); } @@ -229,7 +248,7 @@ static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_fun .atomic_check = dw_hdmi_rockchip_encoder_atomic_check, }; -static const struct dw_hdmi_plat_data rockchip_hdmi_drv_data = { +static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { .mode_valid = dw_hdmi_rockchip_mode_valid, .mpll_cfg = rockchip_mpll_cfg, .cur_ctr = rockchip_cur_ctr, @@ -237,9 +256,20 @@ static const struct dw_hdmi_plat_data rockchip_hdmi_drv_data = { .dev_type = RK3288_HDMI, }; +static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { + .mode_valid = dw_hdmi_rockchip_mode_valid, + .mpll_cfg = rockchip_mpll_cfg, + .cur_ctr = rockchip_cur_ctr, + .phy_config = rockchip_phy_config, + .dev_type = RK3399_HDMI, +}; + static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { { .compatible = "rockchip,rk3288-dw-hdmi", - .data = &rockchip_hdmi_drv_data + .data = &rk3288_hdmi_drv_data + }, + { .compatible = "rockchip,rk3399-dw-hdmi", + .data = &rk3399_hdmi_drv_data }, {}, }; @@ -268,6 +298,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node); plat_data = match->data; hdmi->dev = &pdev->dev; + hdmi->dev_type = plat_data->dev_type; encoder = &hdmi->encoder; irq = platform_get_irq(pdev, 0); diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index bae79f3..26c06d5 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -25,6 +25,7 @@ enum dw_hdmi_devtype { IMX6Q_HDMI, IMX6DL_HDMI, RK3288_HDMI, + RK3399_HDMI, }; struct dw_hdmi_mpll_config { @@ -56,6 +57,11 @@ struct dw_hdmi_plat_data { struct drm_display_mode *mode); }; +static inline bool is_rockchip(enum dw_hdmi_devtype dev_type) +{ + return dev_type == RK3288_HDMI || dev_type == RK3399_HDMI; +} + void dw_hdmi_unbind(struct device *dev, struct device *master, void *data); int dw_hdmi_bind(struct device *dev, struct device *master, void *data, struct drm_encoder *encoder, -- 1.9.1