From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philipp Zabel Subject: Re: [PATCH 4/4] drm/mediatek: adjust VENCPLL clock for 4K HDMI output Date: Wed, 20 Jul 2016 11:55:05 +0200 Message-ID: <1469008505.5809.41.camel@pengutronix.de> References: <1468987385-37353-1-git-send-email-bibby.hsieh@mediatek.com> <1468987385-37353-5-git-send-email-bibby.hsieh@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1468987385-37353-5-git-send-email-bibby.hsieh@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Bibby Hsieh Cc: linux-kernel@vger.kernel.org, Daniel Vetter , Cawa Cheng , dri-devel@lists.freedesktop.org, Mao Huang , linux-mediatek@lists.infradead.org, Sascha Hauer , Matthias Brugger , Yingjoe Chen , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org 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<1468987385-37353-5-git-send-email-bibby.hsieh@mediatek.com> Message-ID: <1469008505.5809.41.camel@pengutronix.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Bibby, Am Mittwoch, den 20.07.2016, 12:03 +0800 schrieb Bibby Hsieh: > if MT8173 display module can support 4K HDMI output, > we have to adjust VENCPLL clock from default 660MHz > to 800MHz. Is vencpll(_d2) the active source for the mm_sel mux? If so, it seems to me that mm_sel or rather one of its children should be set to 800 MHz, and the clock framework should propagate it up to vencpll. I suppose the requirement is that the input clocks to all the display units (ovl, rdma, and so on) need to be sufficiently above the pixel clock. Also, this reads as if we want to keep the clock at 660 MHz if 4K is not supported at all (for example because of a bridge connected at the outside). Actually, would it be desirable to switch vencpll to 660 MHz even on 4K capable devices as long as only lower pixel clocks are active? regards Philipp > Signed-off-by: Bibby Hsieh > --- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 9 +++++++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + > 2 files changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index b1223d5..f159189 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -23,6 +23,7 @@ > #include > #include > #include > +#include > > #include "mtk_drm_crtc.h" > #include "mtk_drm_ddp.h" > @@ -363,6 +364,14 @@ static int mtk_drm_probe(struct platform_device *pdev) > return ret; > } > > + private->vencpll_clk = devm_clk_get(dev, "vencpll"); > + if (IS_ERR(private->vencpll_clk)) { > + ret = PTR_ERR(private->vencpll_clk); > + dev_err(dev, "Failed to get vencpll clock: %d\n", ret); > + return ret; > + } > + clk_set_rate(private->vencpll_clk, 800000000); > + > /* Iterate over sibling DISP function blocks */ > for_each_child_of_node(dev->of_node->parent, node) { > const struct of_device_id *of_id; > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index aa93894..273ad02 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -40,6 +40,7 @@ struct mtk_drm_private { > void __iomem *config_regs; > struct device_node *comp_node[DDP_COMPONENT_ID_MAX]; > struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX]; > + struct clk *vencpll_clk; > > struct { > struct drm_atomic_state *state; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753810AbcGTJzp (ORCPT ); Wed, 20 Jul 2016 05:55:45 -0400 Received: from metis.ext.4.pengutronix.de ([92.198.50.35]:34047 "EHLO metis.ext.4.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753172AbcGTJzn convert rfc822-to-8bit (ORCPT ); Wed, 20 Jul 2016 05:55:43 -0400 Message-ID: <1469008505.5809.41.camel@pengutronix.de> Subject: Re: [PATCH 4/4] drm/mediatek: adjust VENCPLL clock for 4K HDMI output From: Philipp Zabel To: Bibby Hsieh Cc: David Airlie , Matthias Brugger , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Yingjoe Chen , Cawa Cheng , Daniel Kurtz , YT Shen , Thierry Reding , CK Hu , Mao Huang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sascha Hauer Date: Wed, 20 Jul 2016 11:55:05 +0200 In-Reply-To: <1468987385-37353-5-git-send-email-bibby.hsieh@mediatek.com> References: <1468987385-37353-1-git-send-email-bibby.hsieh@mediatek.com> <1468987385-37353-5-git-send-email-bibby.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Mailer: Evolution 3.12.9-1+b1 Mime-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:96de:80ff:fec2:9969 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Bibby, Am Mittwoch, den 20.07.2016, 12:03 +0800 schrieb Bibby Hsieh: > if MT8173 display module can support 4K HDMI output, > we have to adjust VENCPLL clock from default 660MHz > to 800MHz. Is vencpll(_d2) the active source for the mm_sel mux? If so, it seems to me that mm_sel or rather one of its children should be set to 800 MHz, and the clock framework should propagate it up to vencpll. I suppose the requirement is that the input clocks to all the display units (ovl, rdma, and so on) need to be sufficiently above the pixel clock. Also, this reads as if we want to keep the clock at 660 MHz if 4K is not supported at all (for example because of a bridge connected at the outside). Actually, would it be desirable to switch vencpll to 660 MHz even on 4K capable devices as long as only lower pixel clocks are active? regards Philipp > Signed-off-by: Bibby Hsieh > --- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 9 +++++++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + > 2 files changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index b1223d5..f159189 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -23,6 +23,7 @@ > #include > #include > #include > +#include > > #include "mtk_drm_crtc.h" > #include "mtk_drm_ddp.h" > @@ -363,6 +364,14 @@ static int mtk_drm_probe(struct platform_device *pdev) > return ret; > } > > + private->vencpll_clk = devm_clk_get(dev, "vencpll"); > + if (IS_ERR(private->vencpll_clk)) { > + ret = PTR_ERR(private->vencpll_clk); > + dev_err(dev, "Failed to get vencpll clock: %d\n", ret); > + return ret; > + } > + clk_set_rate(private->vencpll_clk, 800000000); > + > /* Iterate over sibling DISP function blocks */ > for_each_child_of_node(dev->of_node->parent, node) { > const struct of_device_id *of_id; > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index aa93894..273ad02 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -40,6 +40,7 @@ struct mtk_drm_private { > void __iomem *config_regs; > struct device_node *comp_node[DDP_COMPONENT_ID_MAX]; > struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX]; > + struct clk *vencpll_clk; > > struct { > struct drm_atomic_state *state;