diff for duplicates of <1469176383-35210-5-git-send-email-minghsiu.tsai@mediatek.com> diff --git a/a/1.txt b/N1/1.txt index 1fe51c4..c648a90 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -30,7 +30,7 @@ index a44cfb7..cabbd85 100644 #clock-cells = <1>; }; -+ mdp_rdma0: rdma@14001000 { ++ mdp_rdma0: rdma at 14001000 { + compatible = "mediatek,mt8173-mdp-rdma", + "mediatek,mt8173-mdp"; + reg = <0 0x14001000 0 0x1000>; @@ -42,7 +42,7 @@ index a44cfb7..cabbd85 100644 + mediatek,vpu = <&vpu>; + }; + -+ mdp_rdma1: rdma@14002000 { ++ mdp_rdma1: rdma at 14002000 { + compatible = "mediatek,mt8173-mdp-rdma"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RDMA1>, @@ -52,28 +52,28 @@ index a44cfb7..cabbd85 100644 + mediatek,larb = <&larb4>; + }; + -+ mdp_rsz0: rsz@14003000 { ++ mdp_rsz0: rsz at 14003000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14003000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ0>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + }; + -+ mdp_rsz1: rsz@14004000 { ++ mdp_rsz1: rsz at 14004000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14004000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + }; + -+ mdp_rsz2: rsz@14005000 { ++ mdp_rsz2: rsz at 14005000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14005000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ2>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + }; + -+ mdp_wdma0: wdma@14006000 { ++ mdp_wdma0: wdma at 14006000 { + compatible = "mediatek,mt8173-mdp-wdma"; + reg = <0 0x14006000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WDMA>; @@ -82,7 +82,7 @@ index a44cfb7..cabbd85 100644 + mediatek,larb = <&larb0>; + }; + -+ mdp_wrot0: wrot@14007000 { ++ mdp_wrot0: wrot at 14007000 { + compatible = "mediatek,mt8173-mdp-wrot"; + reg = <0 0x14007000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; @@ -91,7 +91,7 @@ index a44cfb7..cabbd85 100644 + mediatek,larb = <&larb0>; + }; + -+ mdp_wrot1: wrot@14008000 { ++ mdp_wrot1: wrot at 14008000 { + compatible = "mediatek,mt8173-mdp-wrot"; + reg = <0 0x14008000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WROT1>; @@ -100,7 +100,7 @@ index a44cfb7..cabbd85 100644 + mediatek,larb = <&larb4>; + }; + - pwm0: pwm@1401e000 { + pwm0: pwm at 1401e000 { compatible = "mediatek,mt8173-disp-pwm", "mediatek,mt6595-disp-pwm"; -- diff --git a/a/content_digest b/N1/content_digest index a153eb4..9ee40db 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,23 +1,8 @@ "ref\01469176383-35210-1-git-send-email-minghsiu.tsai@mediatek.com\0" - "From\0Minghsiu Tsai <minghsiu.tsai@mediatek.com>\0" + "From\0minghsiu.tsai@mediatek.com (Minghsiu Tsai)\0" "Subject\0[PATCH v2 4/4] arm64: dts: mediatek: Add MDP for MT8173\0" "Date\0Fri, 22 Jul 2016 16:33:03 +0800\0" - "To\0Hans Verkuil <hans.verkuil@cisco.com>" - daniel.thompson@linaro.org - Rob Herring <robh+dt@kernel.org> - Mauro Carvalho Chehab <mchehab@osg.samsung.com> - Matthias Brugger <matthias.bgg@gmail.com> - Daniel Kurtz <djkurtz@chromium.org> - " Pawel Osciak <posciak@chromium.org>\0" - "Cc\0srv_heupstream@mediatek.com" - Eddie Huang <eddie.huang@mediatek.com> - Yingjoe Chen <yingjoe.chen@mediatek.com> - devicetree@vger.kernel.org - linux-kernel@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-media@vger.kernel.org - linux-mediatek@lists.infradead.org - " Minghsiu Tsai <minghsiu.tsai@mediatek.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Add MDP node for MT8173\n" @@ -52,7 +37,7 @@ " \t\t\t#clock-cells = <1>;\n" " \t\t};\n" " \n" - "+\t\tmdp_rdma0: rdma@14001000 {\n" + "+\t\tmdp_rdma0: rdma at 14001000 {\n" "+\t\t\tcompatible = \"mediatek,mt8173-mdp-rdma\",\n" "+\t\t\t\t \"mediatek,mt8173-mdp\";\n" "+\t\t\treg = <0 0x14001000 0 0x1000>;\n" @@ -64,7 +49,7 @@ "+\t\t\tmediatek,vpu = <&vpu>;\n" "+\t\t};\n" "+\n" - "+\t\tmdp_rdma1: rdma@14002000 {\n" + "+\t\tmdp_rdma1: rdma at 14002000 {\n" "+\t\t\tcompatible = \"mediatek,mt8173-mdp-rdma\";\n" "+\t\t\treg = <0 0x14002000 0 0x1000>;\n" "+\t\t\tclocks = <&mmsys CLK_MM_MDP_RDMA1>,\n" @@ -74,28 +59,28 @@ "+\t\t\tmediatek,larb = <&larb4>;\n" "+\t\t};\n" "+\n" - "+\t\tmdp_rsz0: rsz@14003000 {\n" + "+\t\tmdp_rsz0: rsz at 14003000 {\n" "+\t\t\tcompatible = \"mediatek,mt8173-mdp-rsz\";\n" "+\t\t\treg = <0 0x14003000 0 0x1000>;\n" "+\t\t\tclocks = <&mmsys CLK_MM_MDP_RSZ0>;\n" "+\t\t\tpower-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;\n" "+\t\t};\n" "+\n" - "+\t\tmdp_rsz1: rsz@14004000 {\n" + "+\t\tmdp_rsz1: rsz at 14004000 {\n" "+\t\t\tcompatible = \"mediatek,mt8173-mdp-rsz\";\n" "+\t\t\treg = <0 0x14004000 0 0x1000>;\n" "+\t\t\tclocks = <&mmsys CLK_MM_MDP_RSZ1>;\n" "+\t\t\tpower-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;\n" "+\t\t};\n" "+\n" - "+\t\tmdp_rsz2: rsz@14005000 {\n" + "+\t\tmdp_rsz2: rsz at 14005000 {\n" "+\t\t\tcompatible = \"mediatek,mt8173-mdp-rsz\";\n" "+\t\t\treg = <0 0x14005000 0 0x1000>;\n" "+\t\t\tclocks = <&mmsys CLK_MM_MDP_RSZ2>;\n" "+\t\t\tpower-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;\n" "+\t\t};\n" "+\n" - "+\t\tmdp_wdma0: wdma@14006000 {\n" + "+\t\tmdp_wdma0: wdma at 14006000 {\n" "+\t\t\tcompatible = \"mediatek,mt8173-mdp-wdma\";\n" "+\t\t\treg = <0 0x14006000 0 0x1000>;\n" "+\t\t\tclocks = <&mmsys CLK_MM_MDP_WDMA>;\n" @@ -104,7 +89,7 @@ "+\t\t\tmediatek,larb = <&larb0>;\n" "+\t\t};\n" "+\n" - "+\t\tmdp_wrot0: wrot@14007000 {\n" + "+\t\tmdp_wrot0: wrot at 14007000 {\n" "+\t\t\tcompatible = \"mediatek,mt8173-mdp-wrot\";\n" "+\t\t\treg = <0 0x14007000 0 0x1000>;\n" "+\t\t\tclocks = <&mmsys CLK_MM_MDP_WROT0>;\n" @@ -113,7 +98,7 @@ "+\t\t\tmediatek,larb = <&larb0>;\n" "+\t\t};\n" "+\n" - "+\t\tmdp_wrot1: wrot@14008000 {\n" + "+\t\tmdp_wrot1: wrot at 14008000 {\n" "+\t\t\tcompatible = \"mediatek,mt8173-mdp-wrot\";\n" "+\t\t\treg = <0 0x14008000 0 0x1000>;\n" "+\t\t\tclocks = <&mmsys CLK_MM_MDP_WROT1>;\n" @@ -122,10 +107,10 @@ "+\t\t\tmediatek,larb = <&larb4>;\n" "+\t\t};\n" "+\n" - " \t\tpwm0: pwm@1401e000 {\n" + " \t\tpwm0: pwm at 1401e000 {\n" " \t\t\tcompatible = \"mediatek,mt8173-disp-pwm\",\n" " \t\t\t\t \"mediatek,mt6595-disp-pwm\";\n" "-- \n" 1.7.9.5 -0660ecf6366f89ecbebd41b57e471f01d1eacf1fe43a031c79ee0a451960ca2f +aedefb37f2636a730bab63833752bebb078f28f594507745f0cfe860f4a6f122
diff --git a/a/content_digest b/N2/content_digest index a153eb4..6c63470 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -3,20 +3,20 @@ "Subject\0[PATCH v2 4/4] arm64: dts: mediatek: Add MDP for MT8173\0" "Date\0Fri, 22 Jul 2016 16:33:03 +0800\0" "To\0Hans Verkuil <hans.verkuil@cisco.com>" - daniel.thompson@linaro.org + <daniel.thompson@linaro.org> Rob Herring <robh+dt@kernel.org> Mauro Carvalho Chehab <mchehab@osg.samsung.com> Matthias Brugger <matthias.bgg@gmail.com> Daniel Kurtz <djkurtz@chromium.org> " Pawel Osciak <posciak@chromium.org>\0" - "Cc\0srv_heupstream@mediatek.com" + "Cc\0<srv_heupstream@mediatek.com>" Eddie Huang <eddie.huang@mediatek.com> Yingjoe Chen <yingjoe.chen@mediatek.com> - devicetree@vger.kernel.org - linux-kernel@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-media@vger.kernel.org - linux-mediatek@lists.infradead.org + <devicetree@vger.kernel.org> + <linux-kernel@vger.kernel.org> + <linux-arm-kernel@lists.infradead.org> + <linux-media@vger.kernel.org> + <linux-mediatek@lists.infradead.org> " Minghsiu Tsai <minghsiu.tsai@mediatek.com>\0" "\00:1\0" "b\0" @@ -128,4 +128,4 @@ "-- \n" 1.7.9.5 -0660ecf6366f89ecbebd41b57e471f01d1eacf1fe43a031c79ee0a451960ca2f +14f584d337edf9fa7d5da7efac560d88b0ef3be132733b13129f2e90078b5f44
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