From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f67.google.com ([209.85.220.67]:33080 "EHLO mail-pa0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755118AbcGZGMe (ORCPT ); Tue, 26 Jul 2016 02:12:34 -0400 From: Caesar Wang To: jic23@kernel.org Cc: heiko@sntech.de, robh+dt@kernel.org, linux-iio@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux@roeck-us.net, dianders@chromium.org, Caesar Wang Subject: [PATCH 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs Date: Tue, 26 Jul 2016 14:11:49 +0800 Message-Id: <1469513510-1516-3-git-send-email-wxt@rock-chips.com> In-Reply-To: <1469513510-1516-1-git-send-email-wxt@rock-chips.com> References: <1469513510-1516-1-git-send-email-wxt@rock-chips.com> Sender: linux-iio-owner@vger.kernel.org List-Id: linux-iio@vger.kernel.org SARADC controller needs to be reset before programming it, otherwise it will not function properly. Signed-off-by: Caesar Wang --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index d02a9003..4f44d11 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -270,6 +270,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Caesar Wang Subject: [PATCH 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs Date: Tue, 26 Jul 2016 14:11:49 +0800 Message-ID: <1469513510-1516-3-git-send-email-wxt@rock-chips.com> References: <1469513510-1516-1-git-send-email-wxt@rock-chips.com> Return-path: In-Reply-To: <1469513510-1516-1-git-send-email-wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Sender: linux-iio-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Cc: heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org, dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, Caesar Wang List-Id: linux-rockchip.vger.kernel.org SARADC controller needs to be reset before programming it, otherwise it will not function properly. Signed-off-by: Caesar Wang --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index d02a9003..4f44d11 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -270,6 +270,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; -- 1.9.1