From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lyude Subject: [PATCH v6 3/6] drm/i915/skl: Update plane watermarks atomically during plane updates Date: Tue, 2 Aug 2016 18:37:34 -0400 Message-ID: <1470177458-31984-4-git-send-email-cpaul@redhat.com> References: <1470177458-31984-1-git-send-email-cpaul@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1470177458-31984-1-git-send-email-cpaul@redhat.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: intel-gfx@lists.freedesktop.org, =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , Maarten Lankhorst , Matt Roper Cc: Radhakrishna Sripada , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Hans de Goede , stable@vger.kernel.org, Daniel Vetter , Lyude List-Id: dri-devel@lists.freedesktop.org VGhhbmtzIHRvIFZpbGxlIGZvciBzdWdnZXN0aW5nIHRoaXMgYXMgYSBwb3RlbnRpYWwgc29sdXRp b24gdG8gcGlwZQp1bmRlcnJ1bnMgb24gU2t5bGFrZS4KCk9uIFNreWxha2UgYWxsIG9mIHRoZSBy ZWdpc3RlcnMgZm9yIGNvbmZpZ3VyaW5nIHBsYW5lcywgaW5jbHVkaW5nIHRoZQpyZWdpc3RlcnMg Zm9yIGNvbmZpZ3VyaW5nIHRoZWlyIHdhdGVybWFya3MsIGFyZSBkb3VibGUgYnVmZmVyZWQuIE5l dwp2YWx1ZXMgd3JpdHRlbiB0byB0aGVtIHdvbid0IHRha2UgZWZmZWN0IHVudGlsIHNhaWQgcmVn aXN0ZXJzIGFyZQoiYXJtZWQiLCB3aGljaCBpcyBkb25lIGJ5IHdyaXRpbmcgdG8gdGhlIFBMQU5F X1NVUkYgKG9yIGluIHRoZSBjYXNlIG9mCmN1cnNvciBwbGFuZXMsIHRoZSBDVVJCQVNFIHJlZ2lz dGVyKSByZWdpc3Rlci4KCldpdGggdGhpcyBpbiBtaW5kLCB1cCB1bnRpbCBub3cgd2UndmUgYmVl biB1cGRhdGluZyB3YXRlcm1hcmtzIG9uIHNrbApsaWtlIHRoaXM6CgogIG5vbi1tb2Rlc2V0IHsK ICAgLSBjYWxjdWxhdGUgKGR1cmluZyBhdG9taWMgY2hlY2sgcGhhc2UpCiAgIC0gZmluaXNoX2F0 b21pY19jb21taXQ6CiAgICAgLSBpbnRlbF9wcmVfcGxhbmVfdXBkYXRlOgogICAgICAgIC0gaW50 ZWxfdXBkYXRlX3dhdGVybWFya3MoKQogICAgIC0ge3ZibGFuayBoYXBwZW5zOyBuZXcgd2F0ZXJt YXJrcyArIG9sZCBwbGFuZSB2YWx1ZXMgPT4gdW5kZXJydW4gfQogICAgIC0gZHJtX2F0b21pY19o ZWxwZXJfY29tbWl0X3BsYW5lc19vbl9jcnRjOgogICAgICAgIC0gc3RhcnQgdmJsYW5rIGV2YXNp b24KICAgICAgICAtIHdyaXRlIG5ldyBwbGFuZSByZWdpc3RlcnMKICAgICAgICAtIGVuZCB2Ymxh bmsgZXZhc2lvbgogIH0KCiAgb3IKCiAgbW9kZXNldCB7CiAgIC0gY2FsY3VsYXRlIChkdXJpbmcg YXRvbWljIGNoZWNrIHBoYXNlKQogICAtIGZpbmlzaF9hdG9taWNfY29tbWl0OgogICAgIC0gY3J0 Y19lbmFibGU6CiAgICAgICAgLSBpbnRlbF91cGRhdGVfd2F0ZXJtYXJrcygpCiAgICAgLSB7dmJs YW5rIGhhcHBlbnM7IG5ldyB3YXRlcm1hcmtzICsgb2xkIHBsYW5lIHZhbHVlcyA9PiB1bmRlcnJ1 biB9CiAgICAgLSBkcm1fYXRvbWljX2hlbHBlcl9jb21taXRfcGxhbmVzX29uX2NydGM6CiAgICAg ICAgLSBzdGFydCB2YmxhbmsgZXZhc2lvbgogICAgICAgIC0gd3JpdGUgbmV3IHBsYW5lIHJlZ2lz dGVycwogICAgICAgIC0gZW5kIHZibGFuayBldmFzaW9uCiAgfQoKTm93IHdlIHVwZGF0ZSB3YXRl cm1hcmtzIGF0b21pY2FsbHkgbGlrZSB0aGlzOgoKICBub24tbW9kZXNldCB7CiAgIC0gY2FsY3Vs YXRlIChkdXJpbmcgYXRvbWljIGNoZWNrIHBoYXNlKQogICAtIGZpbmlzaF9hdG9taWNfY29tbWl0 OgogICAgIC0gaW50ZWxfcHJlX3BsYW5lX3VwZGF0ZToKICAgICAgICAtIGludGVsX3VwZGF0ZV93 YXRlcm1hcmtzKCkgKHdtIHZhbHVlcyBhcmVuJ3Qgd3JpdHRlbiB5ZXQpCiAgICAgLSBkcm1fYXRv bWljX2hlbHBlcl9jb21taXRfcGxhbmVzX29uX2NydGM6CiAgICAgICAgLSBzdGFydCB2Ymxhbmsg ZXZhc2lvbgogICAgICAgIC0gd3JpdGUgbmV3IHBsYW5lIHJlZ2lzdGVycwogICAgICAgIC0gd3Jp dGUgbmV3IHdtIHZhbHVlcwogICAgICAgIC0gZW5kIHZibGFuayBldmFzaW9uCiAgfQoKICBtb2Rl c2V0IHsKICAgLSBjYWxjdWxhdGUgKGR1cmluZyBhdG9taWMgY2hlY2sgcGhhc2UpCiAgIC0gZmlu aXNoX2F0b21pY19jb21taXQ6CiAgICAgLSBjcnRjX2VuYWJsZToKICAgICAgICAtIGludGVsX3Vw ZGF0ZV93YXRlcm1hcmtzKCkgKGFjdHVhbCB3bSB2YWx1ZXMgYXJlbid0IHdyaXR0ZW4KICAgICAg ICAgIHlldCkKICAgICAtIGRybV9hdG9taWNfaGVscGVyX2NvbW1pdF9wbGFuZXNfb25fY3J0YzoK ICAgICAgICAtIHN0YXJ0IHZibGFuayBldmFzaW9uCiAgICAgICAgLSB3cml0ZSBuZXcgcGxhbmUg cmVnaXN0ZXJzCgktIHdyaXRlIG5ldyB3bSB2YWx1ZXMKICAgICAgICAtIGVuZCB2YmxhbmsgZXZh c2lvbgogIH0KClNvIHRoaXMgcGF0Y2ggbW92ZXMgYWxsIG9mIHRoZSB3YXRlcm1hcmsgd3JpdGVz IGludG8gdGhlIHJpZ2h0IHBsYWNlOwppbnNpZGUgb2YgdGhlIHZibGFuayBldmFzaW9uIHdoZXJl IHdlIHVwZGF0ZSBhbGwgb2YgdGhlIHJlZ2lzdGVycyBmb3IKZWFjaCBwbGFuZS4gV2hpbGUgdGhp cyBwYXRjaCBkb2Vzbid0IGZpeCBldmVyeXRoaW5nLCBpdCBkb2VzIGFsbG93IHVzIHRvCnVwZGF0 ZSB0aGUgd2F0ZXJtYXJrIHZhbHVlcyBpbiB0aGUgd2F5IHRoZSBoYXJkd2FyZSBleHBlY3RzIHVz IHRvLgoKQ2hhbmdlcyBzaW5jZSBvcmlnaW5hbCBwYXRjaCBzZXJpZXM6CiAtIFJlbW92ZSBtdXRl eF9sb2NrL211dGV4X3VubG9jayBzaW5jZSB0aGV5IGRvbid0IGRvIGFueXRoaW5nIGFuZCB3ZSdy ZQogICBub3QgdG91Y2hpbmcgZ2xvYmFsIHN0YXRlCiAtIE1vdmUgc2tsX3dyaXRlX2N1cnNvcl93 bS9za2xfd3JpdGVfcGxhbmVfd20gZnVuY3Rpb25zIGludG8KICAgaW50ZWxfcG0uYywgbWFrZSBl eHRlcm5hbGx5IHZpc2libGUKIC0gQWRkIHNrbF93cml0ZV9wbGFuZV93bSBjYWxscyB0byBza2xf dXBkYXRlX3BsYW5lCiAtIEZpeCBjb25kaXRpb25hbCBmb3IgZm9yIGxvb3AgaW4gc2tsX3dyaXRl X3BsYW5lX3dtIChsZXZlbCA8IG1heF9sZXZlbAogICBzaG91bGQgYmUgbGV2ZWwgPD0gbWF4X2xl dmVsKQogLSBNYWtlIGRpYWdyYW0gaW4gY29tbWl0IG1vcmUgYWNjdXJhdGUgdG8gd2hhdCdzIGFj dHVhbGx5IGhhcHBlbmluZwogLSBBZGQgRml4ZXM6CgpDaGFuZ2VzIHNpbmNlIHYxOgogLSBVc2Ug SVNfR0VOOSgpIGluc3RlYWQgb2YgSVNfU0tZTEFLRSgpIHNpbmNlIHRoZXNlIGZpeGVzIGFwcGx5 IHRvIG1vcmUKICAgdGhlbiBqdXN0IFNreWxha2UKIC0gVXBkYXRlIGRlc2NyaXB0aW9uIHRvIG1h a2UgaXQgY2xlYXIgdGhpcyBwYXRjaCBkb2Vzbid0IGZpeCBldmVyeXRoaW5nCiAtIENoZWNrIGlm IHBpcGVzIHdlcmUgYWN0dWFsbHkgY2hhbmdlZCBiZWZvcmUgd3JpdGluZyB3YXRlcm1hcmtzCgpD aGFuZ2VzIHNpbmNlIHYyOgogLSBXcml0ZSBQSVBFX1dNX0xJTkVUSU1FIGR1cmluZyB2Ymxhbmsg ZXZhc2lvbgoKQ2hhbmdlcyBzaW5jZSB2MzoKIC0gUmViYXNlIGFnYWluc3QgbmV3IFNBR1YgcGF0 Y2ggY2hhbmdlcwoKQ2hhbmdlcyBzaW5jZSB2NDoKIC0gQWRkIGEgcGFyYW1ldGVyIHRvIGNob29z ZSB3aGF0IHNrbF93bV92YWx1ZXMgc3RydWN0IHRvIHVzZSB3aGVuCiAgIHdyaXRpbmcgbmV3IHBs YW5lIHdhdGVybWFya3MKCkNoYW5nZXMgc2luY2UgdjU6CiAtIFJlbW92ZSBjdXJzb3IgZGRiIGVu dHJ5IHdyaXRlIGluIHNrbF93cml0ZV9jdXJzb3Jfd20oKSwgZGVmZXIgdW50aWwKICAgcGF0Y2gg NgogLSBXcml0ZSBXTV9MSU5FVElNRSBpbiBpbnRlbF9iZWdpbl9jcnRjX2NvbW1pdCgpCgpGaXhl czogMmQ0MWMwYjU5YWZjICgiZHJtL2k5MTUvc2tsOiBTS0wgV2F0ZXJtYXJrIENvbXB1dGF0aW9u IikKU2lnbmVkLW9mZi1ieTogTHl1ZGUgPGNwYXVsQHJlZGhhdC5jb20+CkNjOiBzdGFibGVAdmdl ci5rZXJuZWwub3JnCkNjOiBWaWxsZSBTeXJqw6Rsw6QgPHZpbGxlLnN5cmphbGFAbGludXguaW50 ZWwuY29tPgpDYzogRGFuaWVsIFZldHRlciA8ZGFuaWVsLnZldHRlckBpbnRlbC5jb20+CkNjOiBS YWRoYWtyaXNobmEgU3JpcGFkYSA8cmFkaGFrcmlzaG5hLnNyaXBhZGFAaW50ZWwuY29tPgpDYzog SGFucyBkZSBHb2VkZSA8aGRlZ29lZGVAcmVkaGF0LmNvbT4KQ2M6IE1hdHQgUm9wZXIgPG1hdHRo ZXcuZC5yb3BlckBpbnRlbC5jb20+Ci0tLQogZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZGlz cGxheS5jIHwgMTYgKysrKysrKysrKy0KIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rydi5o ICAgICB8ICA1ICsrKysKIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX3BtLmMgICAgICB8IDUz ICsrKysrKysrKysrKysrKysrKysrKysrKystLS0tLS0tLS0tLQogZHJpdmVycy9ncHUvZHJtL2k5 MTUvaW50ZWxfc3ByaXRlLmMgIHwgIDYgKysrKwogNCBmaWxlcyBjaGFuZ2VkLCA2MyBpbnNlcnRp b25zKCspLCAxNyBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkx NS9pbnRlbF9kaXNwbGF5LmMgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kaXNwbGF5LmMK aW5kZXggMDAxYzg4NS4uNzZlZmU1MyAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUv aW50ZWxfZGlzcGxheS5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rpc3BsYXku YwpAQCAtMjk4MCw2ICsyOTgwLDcgQEAgc3RhdGljIHZvaWQgc2t5bGFrZV91cGRhdGVfcHJpbWFy eV9wbGFuZShzdHJ1Y3QgZHJtX3BsYW5lICpwbGFuZSwKIAlzdHJ1Y3QgaW50ZWxfY3J0YyAqaW50 ZWxfY3J0YyA9IHRvX2ludGVsX2NydGMoY3J0Y19zdGF0ZS0+YmFzZS5jcnRjKTsKIAlzdHJ1Y3Qg ZHJtX2ZyYW1lYnVmZmVyICpmYiA9IHBsYW5lX3N0YXRlLT5iYXNlLmZiOwogCXN0cnVjdCBkcm1f aTkxNV9nZW1fb2JqZWN0ICpvYmogPSBpbnRlbF9mYl9vYmooZmIpOworCXN0cnVjdCBza2xfd21f dmFsdWVzICp3bSA9ICZkZXZfcHJpdi0+d20uc2tsX3Jlc3VsdHM7CiAJaW50IHBpcGUgPSBpbnRl bF9jcnRjLT5waXBlOwogCXUzMiBwbGFuZV9jdGwsIHN0cmlkZV9kaXYsIHN0cmlkZTsKIAl1MzIg dGlsZV9oZWlnaHQsIHBsYW5lX29mZnNldCwgcGxhbmVfc2l6ZTsKQEAgLTMwMzEsNiArMzAzMiw5 IEBAIHN0YXRpYyB2b2lkIHNreWxha2VfdXBkYXRlX3ByaW1hcnlfcGxhbmUoc3RydWN0IGRybV9w bGFuZSAqcGxhbmUsCiAJaW50ZWxfY3J0Yy0+YWRqdXN0ZWRfeCA9IHhfb2Zmc2V0OwogCWludGVs X2NydGMtPmFkanVzdGVkX3kgPSB5X29mZnNldDsKIAorCWlmICh3bS0+ZGlydHlfcGlwZXMgJiBk cm1fY3J0Y19tYXNrKCZpbnRlbF9jcnRjLT5iYXNlKSkKKwkgICAgc2tsX3dyaXRlX3BsYW5lX3dt KGludGVsX2NydGMsIHdtLCAwKTsKKwogCUk5MTVfV1JJVEUoUExBTkVfQ1RMKHBpcGUsIDApLCBw bGFuZV9jdGwpOwogCUk5MTVfV1JJVEUoUExBTkVfT0ZGU0VUKHBpcGUsIDApLCBwbGFuZV9vZmZz ZXQpOwogCUk5MTVfV1JJVEUoUExBTkVfU0laRShwaXBlLCAwKSwgcGxhbmVfc2l6ZSk7CkBAIC0x MDIzMSw5ICsxMDIzNSwxMyBAQCBzdGF0aWMgdm9pZCBpOXh4X3VwZGF0ZV9jdXJzb3Ioc3RydWN0 IGRybV9jcnRjICpjcnRjLCB1MzIgYmFzZSwKIAlzdHJ1Y3QgZHJtX2RldmljZSAqZGV2ID0gY3J0 Yy0+ZGV2OwogCXN0cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiA9IHRvX2k5MTUoZGV2 KTsKIAlzdHJ1Y3QgaW50ZWxfY3J0YyAqaW50ZWxfY3J0YyA9IHRvX2ludGVsX2NydGMoY3J0Yyk7 CisJc3RydWN0IHNrbF93bV92YWx1ZXMgKndtID0gJmRldl9wcml2LT53bS5za2xfcmVzdWx0czsK IAlpbnQgcGlwZSA9IGludGVsX2NydGMtPnBpcGU7CiAJdWludDMyX3QgY250bCA9IDA7CiAKKwlp ZiAoSVNfR0VOOShkZXZfcHJpdikgJiYgd20tPmRpcnR5X3BpcGVzICYgZHJtX2NydGNfbWFzayhj cnRjKSkKKwkJc2tsX3dyaXRlX2N1cnNvcl93bShpbnRlbF9jcnRjLCB3bSk7CisKIAlpZiAocGxh bmVfc3RhdGUgJiYgcGxhbmVfc3RhdGUtPnZpc2libGUpIHsKIAkJY250bCA9IE1DVVJTT1JfR0FN TUFfRU5BQkxFOwogCQlzd2l0Y2ggKHBsYW5lX3N0YXRlLT5iYXNlLmNydGNfdykgewpAQCAtMTQx NTYsMTAgKzE0MTY0LDEyIEBAIHN0YXRpYyB2b2lkIGludGVsX2JlZ2luX2NydGNfY29tbWl0KHN0 cnVjdCBkcm1fY3J0YyAqY3J0YywKIAkJCQkgICAgc3RydWN0IGRybV9jcnRjX3N0YXRlICpvbGRf Y3J0Y19zdGF0ZSkKIHsKIAlzdHJ1Y3QgZHJtX2RldmljZSAqZGV2ID0gY3J0Yy0+ZGV2OworCXN0 cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiA9IHRvX2k5MTUoZGV2KTsKIAlzdHJ1Y3Qg aW50ZWxfY3J0YyAqaW50ZWxfY3J0YyA9IHRvX2ludGVsX2NydGMoY3J0Yyk7CiAJc3RydWN0IGlu dGVsX2NydGNfc3RhdGUgKm9sZF9pbnRlbF9zdGF0ZSA9CiAJCXRvX2ludGVsX2NydGNfc3RhdGUo b2xkX2NydGNfc3RhdGUpOwogCWJvb2wgbW9kZXNldCA9IG5lZWRzX21vZGVzZXQoY3J0Yy0+c3Rh dGUpOworCWVudW0gcGlwZSBwaXBlID0gaW50ZWxfY3J0Yy0+cGlwZTsKIAogCS8qIFBlcmZvcm0g dmJsYW5rIGV2YXNpb24gYXJvdW5kIGNvbW1pdCBvcGVyYXRpb24gKi8KIAlpbnRlbF9waXBlX3Vw ZGF0ZV9zdGFydChpbnRlbF9jcnRjKTsKQEAgLTE0MTc0LDggKzE0MTg0LDEyIEBAIHN0YXRpYyB2 b2lkIGludGVsX2JlZ2luX2NydGNfY29tbWl0KHN0cnVjdCBkcm1fY3J0YyAqY3J0YywKIAogCWlm ICh0b19pbnRlbF9jcnRjX3N0YXRlKGNydGMtPnN0YXRlKS0+dXBkYXRlX3BpcGUpCiAJCWludGVs X3VwZGF0ZV9waXBlX2NvbmZpZyhpbnRlbF9jcnRjLCBvbGRfaW50ZWxfc3RhdGUpOwotCWVsc2Ug aWYgKElOVEVMX0lORk8oZGV2KS0+Z2VuID49IDkpCisJZWxzZSBpZiAoSU5URUxfSU5GTyhkZXYp LT5nZW4gPj0gOSkgewogCQlza2xfZGV0YWNoX3NjYWxlcnMoaW50ZWxfY3J0Yyk7CisKKwkJSTkx NV9XUklURShQSVBFX1dNX0xJTkVUSU1FKHBpcGUpLAorCQkJICAgZGV2X3ByaXYtPndtLnNrbF9o dy53bV9saW5ldGltZVtwaXBlXSk7CisJfQogfQogCiBzdGF0aWMgdm9pZCBpbnRlbF9maW5pc2hf Y3J0Y19jb21taXQoc3RydWN0IGRybV9jcnRjICpjcnRjLApkaWZmIC0tZ2l0IGEvZHJpdmVycy9n cHUvZHJtL2k5MTUvaW50ZWxfZHJ2LmggYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcnYu aAppbmRleCA2YjA1MzJhLi4xYjQ0NGQzIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkx NS9pbnRlbF9kcnYuaAorKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcnYuaApAQCAt MTcxMSw2ICsxNzExLDExIEBAIHZvaWQgc2tsX2RkYl9nZXRfaHdfc3RhdGUoc3RydWN0IGRybV9p OTE1X3ByaXZhdGUgKmRldl9wcml2LAogCQkJICBzdHJ1Y3Qgc2tsX2RkYl9hbGxvY2F0aW9uICpk ZGIgLyogb3V0ICovKTsKIGludCBza2xfZW5hYmxlX3NhZ3Yoc3RydWN0IGRybV9pOTE1X3ByaXZh dGUgKmRldl9wcml2KTsKIGludCBza2xfZGlzYWJsZV9zYWd2KHN0cnVjdCBkcm1faTkxNV9wcml2 YXRlICpkZXZfcHJpdik7Cit2b2lkIHNrbF93cml0ZV9jdXJzb3Jfd20oc3RydWN0IGludGVsX2Ny dGMgKmludGVsX2NydGMsCisJCQkgY29uc3Qgc3RydWN0IHNrbF93bV92YWx1ZXMgKndtKTsKK3Zv aWQgc2tsX3dyaXRlX3BsYW5lX3dtKHN0cnVjdCBpbnRlbF9jcnRjICppbnRlbF9jcnRjLAorCQkJ Y29uc3Qgc3RydWN0IHNrbF93bV92YWx1ZXMgKndtLAorCQkJaW50IHBsYW5lKTsKIHVpbnQzMl90 IGlsa19waXBlX3BpeGVsX3JhdGUoY29uc3Qgc3RydWN0IGludGVsX2NydGNfc3RhdGUgKnBpcGVf Y29uZmlnKTsKIGJvb2wgaWxrX2Rpc2FibGVfbHBfd20oc3RydWN0IGRybV9kZXZpY2UgKmRldik7 CiBpbnQgc2FuaXRpemVfcmM2X29wdGlvbihzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3By aXYsIGludCBlbmFibGVfcmM2KTsKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2lu dGVsX3BtLmMgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wbS5jCmluZGV4IDdmZDI5OWUu LjJjMTJiNjYgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX3BtLmMKKysr IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfcG0uYwpAQCAtMzc5OCw2ICszNzk4LDQyIEBA IHN0YXRpYyB2b2lkIHNrbF9kZGJfZW50cnlfd3JpdGUoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUg KmRldl9wcml2LAogCQlJOTE1X1dSSVRFKHJlZywgMCk7CiB9CiAKK3ZvaWQgc2tsX3dyaXRlX3Bs YW5lX3dtKHN0cnVjdCBpbnRlbF9jcnRjICppbnRlbF9jcnRjLAorCQkJY29uc3Qgc3RydWN0IHNr bF93bV92YWx1ZXMgKndtLAorCQkJaW50IHBsYW5lKQoreworCXN0cnVjdCBkcm1fY3J0YyAqY3J0 YyA9ICZpbnRlbF9jcnRjLT5iYXNlOworCXN0cnVjdCBkcm1fZGV2aWNlICpkZXYgPSBjcnRjLT5k ZXY7CisJc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2ID0gdG9faTkxNShkZXYpOwor CWludCBsZXZlbCwgbWF4X2xldmVsID0gaWxrX3dtX21heF9sZXZlbChkZXYpOworCWVudW0gcGlw ZSBwaXBlID0gaW50ZWxfY3J0Yy0+cGlwZTsKKworCWlmICghKHdtLT5kaXJ0eV9waXBlcyAmIGRy bV9jcnRjX21hc2soY3J0YykpKQorCQlyZXR1cm47CisKKwlmb3IgKGxldmVsID0gMDsgbGV2ZWwg PD0gbWF4X2xldmVsOyBsZXZlbCsrKSB7CisJCUk5MTVfV1JJVEUoUExBTkVfV00ocGlwZSwgcGxh bmUsIGxldmVsKSwKKwkJCSAgIHdtLT5wbGFuZVtwaXBlXVtwbGFuZV1bbGV2ZWxdKTsKKwl9CisJ STkxNV9XUklURShQTEFORV9XTV9UUkFOUyhwaXBlLCBwbGFuZSksIHdtLT5wbGFuZV90cmFuc1tw aXBlXVtwbGFuZV0pOworfQorCit2b2lkIHNrbF93cml0ZV9jdXJzb3Jfd20oc3RydWN0IGludGVs X2NydGMgKmludGVsX2NydGMsCisJCQkgY29uc3Qgc3RydWN0IHNrbF93bV92YWx1ZXMgKndtKQor eworCXN0cnVjdCBkcm1fY3J0YyAqY3J0YyA9ICZpbnRlbF9jcnRjLT5iYXNlOworCXN0cnVjdCBk cm1fZGV2aWNlICpkZXYgPSBjcnRjLT5kZXY7CisJc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRl dl9wcml2ID0gdG9faTkxNShkZXYpOworCWludCBsZXZlbCwgbWF4X2xldmVsID0gaWxrX3dtX21h eF9sZXZlbChkZXYpOworCWVudW0gcGlwZSBwaXBlID0gaW50ZWxfY3J0Yy0+cGlwZTsKKworCWZv ciAobGV2ZWwgPSAwOyBsZXZlbCA8PSBtYXhfbGV2ZWw7IGxldmVsKyspIHsKKwkJSTkxNV9XUklU RShDVVJfV00ocGlwZSwgbGV2ZWwpLAorCQkJICAgd20tPnBsYW5lW3BpcGVdW1BMQU5FX0NVUlNP Ul1bbGV2ZWxdKTsKKwl9CisJSTkxNV9XUklURShDVVJfV01fVFJBTlMocGlwZSksIHdtLT5wbGFu ZV90cmFuc1twaXBlXVtQTEFORV9DVVJTT1JdKTsKK30KKwogc3RhdGljIHZvaWQgc2tsX3dyaXRl X3dtX3ZhbHVlcyhzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYsCiAJCQkJY29uc3Qg c3RydWN0IHNrbF93bV92YWx1ZXMgKm5ldykKIHsKQEAgLTM4MDUsNyArMzg0MSw3IEBAIHN0YXRp YyB2b2lkIHNrbF93cml0ZV93bV92YWx1ZXMoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9w cml2LAogCXN0cnVjdCBpbnRlbF9jcnRjICpjcnRjOwogCiAJZm9yX2VhY2hfaW50ZWxfY3J0Yyhk ZXYsIGNydGMpIHsKLQkJaW50IGksIGxldmVsLCBtYXhfbGV2ZWwgPSBpbGtfd21fbWF4X2xldmVs KGRldik7CisJCWludCBpOwogCQllbnVtIHBpcGUgcGlwZSA9IGNydGMtPnBpcGU7CiAKIAkJaWYg KChuZXctPmRpcnR5X3BpcGVzICYgZHJtX2NydGNfbWFzaygmY3J0Yy0+YmFzZSkpID09IDApCkBA IC0zODEzLDIxICszODQ5LDYgQEAgc3RhdGljIHZvaWQgc2tsX3dyaXRlX3dtX3ZhbHVlcyhzdHJ1 Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYsCiAJCWlmICghY3J0Yy0+YWN0aXZlKQogCQkJ Y29udGludWU7CiAKLQkJSTkxNV9XUklURShQSVBFX1dNX0xJTkVUSU1FKHBpcGUpLCBuZXctPndt X2xpbmV0aW1lW3BpcGVdKTsKLQotCQlmb3IgKGxldmVsID0gMDsgbGV2ZWwgPD0gbWF4X2xldmVs OyBsZXZlbCsrKSB7Ci0JCQlmb3IgKGkgPSAwOyBpIDwgaW50ZWxfbnVtX3BsYW5lcyhjcnRjKTsg aSsrKQotCQkJCUk5MTVfV1JJVEUoUExBTkVfV00ocGlwZSwgaSwgbGV2ZWwpLAotCQkJCQkgICBu ZXctPnBsYW5lW3BpcGVdW2ldW2xldmVsXSk7Ci0JCQlJOTE1X1dSSVRFKENVUl9XTShwaXBlLCBs ZXZlbCksCi0JCQkJICAgbmV3LT5wbGFuZVtwaXBlXVtQTEFORV9DVVJTT1JdW2xldmVsXSk7Ci0J CX0KLQkJZm9yIChpID0gMDsgaSA8IGludGVsX251bV9wbGFuZXMoY3J0Yyk7IGkrKykKLQkJCUk5 MTVfV1JJVEUoUExBTkVfV01fVFJBTlMocGlwZSwgaSksCi0JCQkJICAgbmV3LT5wbGFuZV90cmFu c1twaXBlXVtpXSk7Ci0JCUk5MTVfV1JJVEUoQ1VSX1dNX1RSQU5TKHBpcGUpLAotCQkJICAgbmV3 LT5wbGFuZV90cmFuc1twaXBlXVtQTEFORV9DVVJTT1JdKTsKLQogCQlmb3IgKGkgPSAwOyBpIDwg aW50ZWxfbnVtX3BsYW5lcyhjcnRjKTsgaSsrKSB7CiAJCQlza2xfZGRiX2VudHJ5X3dyaXRlKGRl dl9wcml2LAogCQkJCQkgICAgUExBTkVfQlVGX0NGRyhwaXBlLCBpKSwKZGlmZiAtLWdpdCBhL2Ry aXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX3Nwcml0ZS5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUv aW50ZWxfc3ByaXRlLmMKaW5kZXggMGRlOTM1YS4uNTVkMTczZiAxMDA2NDQKLS0tIGEvZHJpdmVy cy9ncHUvZHJtL2k5MTUvaW50ZWxfc3ByaXRlLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUv aW50ZWxfc3ByaXRlLmMKQEAgLTIwMyw2ICsyMDMsOSBAQCBza2xfdXBkYXRlX3BsYW5lKHN0cnVj dCBkcm1fcGxhbmUgKmRybV9wbGFuZSwKIAlzdHJ1Y3QgaW50ZWxfcGxhbmUgKmludGVsX3BsYW5l ID0gdG9faW50ZWxfcGxhbmUoZHJtX3BsYW5lKTsKIAlzdHJ1Y3QgZHJtX2ZyYW1lYnVmZmVyICpm YiA9IHBsYW5lX3N0YXRlLT5iYXNlLmZiOwogCXN0cnVjdCBkcm1faTkxNV9nZW1fb2JqZWN0ICpv YmogPSBpbnRlbF9mYl9vYmooZmIpOworCXN0cnVjdCBza2xfd21fdmFsdWVzICp3bSA9ICZkZXZf cHJpdi0+d20uc2tsX3Jlc3VsdHM7CisJc3RydWN0IGRybV9jcnRjICpjcnRjID0gY3J0Y19zdGF0 ZS0+YmFzZS5jcnRjOworCXN0cnVjdCBpbnRlbF9jcnRjICppbnRlbF9jcnRjID0gdG9faW50ZWxf Y3J0YyhjcnRjKTsKIAljb25zdCBpbnQgcGlwZSA9IGludGVsX3BsYW5lLT5waXBlOwogCWNvbnN0 IGludCBwbGFuZSA9IGludGVsX3BsYW5lLT5wbGFuZSArIDE7CiAJdTMyIHBsYW5lX2N0bCwgc3Ry aWRlX2Rpdiwgc3RyaWRlOwpAQCAtMjM4LDYgKzI0MSw5IEBAIHNrbF91cGRhdGVfcGxhbmUoc3Ry dWN0IGRybV9wbGFuZSAqZHJtX3BsYW5lLAogCWNydGNfdy0tOwogCWNydGNfaC0tOwogCisJaWYg KHdtLT5kaXJ0eV9waXBlcyAmIGRybV9jcnRjX21hc2soY3J0YykpCisJICAgIHNrbF93cml0ZV9w bGFuZV93bShpbnRlbF9jcnRjLCB3bSwgcGxhbmUpOworCiAJaWYgKGtleS0+ZmxhZ3MpIHsKIAkJ STkxNV9XUklURShQTEFORV9LRVlWQUwocGlwZSwgcGxhbmUpLCBrZXktPm1pbl92YWx1ZSk7CiAJ CUk5MTVfV1JJVEUoUExBTkVfS0VZTUFYKHBpcGUsIHBsYW5lKSwga2V5LT5tYXhfdmFsdWUpOwot LSAKMi43LjQKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f CmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpo dHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756172AbcHBWkE (ORCPT ); Tue, 2 Aug 2016 18:40:04 -0400 Received: from mx1.redhat.com ([209.132.183.28]:43420 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754252AbcHBWji (ORCPT ); Tue, 2 Aug 2016 18:39:38 -0400 From: Lyude To: intel-gfx@lists.freedesktop.org, =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , Maarten Lankhorst , Matt Roper Cc: Lyude , stable@vger.kernel.org, Daniel Vetter , Radhakrishna Sripada , Hans de Goede , Jani Nikula , David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/6] drm/i915/skl: Update plane watermarks atomically during plane updates Date: Tue, 2 Aug 2016 18:37:34 -0400 Message-Id: <1470177458-31984-4-git-send-email-cpaul@redhat.com> In-Reply-To: <1470177458-31984-1-git-send-email-cpaul@redhat.com> References: <1470177458-31984-1-git-send-email-cpaul@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Tue, 02 Aug 2016 22:38:17 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thanks to Ville for suggesting this as a potential solution to pipe underruns on Skylake. On Skylake all of the registers for configuring planes, including the registers for configuring their watermarks, are double buffered. New values written to them won't take effect until said registers are "armed", which is done by writing to the PLANE_SURF (or in the case of cursor planes, the CURBASE register) register. With this in mind, up until now we've been updating watermarks on skl like this: non-modeset { - calculate (during atomic check phase) - finish_atomic_commit: - intel_pre_plane_update: - intel_update_watermarks() - {vblank happens; new watermarks + old plane values => underrun } - drm_atomic_helper_commit_planes_on_crtc: - start vblank evasion - write new plane registers - end vblank evasion } or modeset { - calculate (during atomic check phase) - finish_atomic_commit: - crtc_enable: - intel_update_watermarks() - {vblank happens; new watermarks + old plane values => underrun } - drm_atomic_helper_commit_planes_on_crtc: - start vblank evasion - write new plane registers - end vblank evasion } Now we update watermarks atomically like this: non-modeset { - calculate (during atomic check phase) - finish_atomic_commit: - intel_pre_plane_update: - intel_update_watermarks() (wm values aren't written yet) - drm_atomic_helper_commit_planes_on_crtc: - start vblank evasion - write new plane registers - write new wm values - end vblank evasion } modeset { - calculate (during atomic check phase) - finish_atomic_commit: - crtc_enable: - intel_update_watermarks() (actual wm values aren't written yet) - drm_atomic_helper_commit_planes_on_crtc: - start vblank evasion - write new plane registers - write new wm values - end vblank evasion } So this patch moves all of the watermark writes into the right place; inside of the vblank evasion where we update all of the registers for each plane. While this patch doesn't fix everything, it does allow us to update the watermark values in the way the hardware expects us to. Changes since original patch series: - Remove mutex_lock/mutex_unlock since they don't do anything and we're not touching global state - Move skl_write_cursor_wm/skl_write_plane_wm functions into intel_pm.c, make externally visible - Add skl_write_plane_wm calls to skl_update_plane - Fix conditional for for loop in skl_write_plane_wm (level < max_level should be level <= max_level) - Make diagram in commit more accurate to what's actually happening - Add Fixes: Changes since v1: - Use IS_GEN9() instead of IS_SKYLAKE() since these fixes apply to more then just Skylake - Update description to make it clear this patch doesn't fix everything - Check if pipes were actually changed before writing watermarks Changes since v2: - Write PIPE_WM_LINETIME during vblank evasion Changes since v3: - Rebase against new SAGV patch changes Changes since v4: - Add a parameter to choose what skl_wm_values struct to use when writing new plane watermarks Changes since v5: - Remove cursor ddb entry write in skl_write_cursor_wm(), defer until patch 6 - Write WM_LINETIME in intel_begin_crtc_commit() Fixes: 2d41c0b59afc ("drm/i915/skl: SKL Watermark Computation") Signed-off-by: Lyude Cc: stable@vger.kernel.org Cc: Ville Syrjälä Cc: Daniel Vetter Cc: Radhakrishna Sripada Cc: Hans de Goede Cc: Matt Roper --- drivers/gpu/drm/i915/intel_display.c | 16 ++++++++++- drivers/gpu/drm/i915/intel_drv.h | 5 ++++ drivers/gpu/drm/i915/intel_pm.c | 53 +++++++++++++++++++++++++----------- drivers/gpu/drm/i915/intel_sprite.c | 6 ++++ 4 files changed, 63 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 001c885..76efe53 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2980,6 +2980,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane, struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_framebuffer *fb = plane_state->base.fb; struct drm_i915_gem_object *obj = intel_fb_obj(fb); + struct skl_wm_values *wm = &dev_priv->wm.skl_results; int pipe = intel_crtc->pipe; u32 plane_ctl, stride_div, stride; u32 tile_height, plane_offset, plane_size; @@ -3031,6 +3032,9 @@ static void skylake_update_primary_plane(struct drm_plane *plane, intel_crtc->adjusted_x = x_offset; intel_crtc->adjusted_y = y_offset; + if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) + skl_write_plane_wm(intel_crtc, wm, 0); + I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); @@ -10231,9 +10235,13 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct skl_wm_values *wm = &dev_priv->wm.skl_results; int pipe = intel_crtc->pipe; uint32_t cntl = 0; + if (IS_GEN9(dev_priv) && wm->dirty_pipes & drm_crtc_mask(crtc)) + skl_write_cursor_wm(intel_crtc, wm); + if (plane_state && plane_state->visible) { cntl = MCURSOR_GAMMA_ENABLE; switch (plane_state->base.crtc_w) { @@ -14156,10 +14164,12 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_crtc_state *old_intel_state = to_intel_crtc_state(old_crtc_state); bool modeset = needs_modeset(crtc->state); + enum pipe pipe = intel_crtc->pipe; /* Perform vblank evasion around commit operation */ intel_pipe_update_start(intel_crtc); @@ -14174,8 +14184,12 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc, if (to_intel_crtc_state(crtc->state)->update_pipe) intel_update_pipe_config(intel_crtc, old_intel_state); - else if (INTEL_INFO(dev)->gen >= 9) + else if (INTEL_INFO(dev)->gen >= 9) { skl_detach_scalers(intel_crtc); + + I915_WRITE(PIPE_WM_LINETIME(pipe), + dev_priv->wm.skl_hw.wm_linetime[pipe]); + } } static void intel_finish_crtc_commit(struct drm_crtc *crtc, diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 6b0532a..1b444d3 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1711,6 +1711,11 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, struct skl_ddb_allocation *ddb /* out */); int skl_enable_sagv(struct drm_i915_private *dev_priv); int skl_disable_sagv(struct drm_i915_private *dev_priv); +void skl_write_cursor_wm(struct intel_crtc *intel_crtc, + const struct skl_wm_values *wm); +void skl_write_plane_wm(struct intel_crtc *intel_crtc, + const struct skl_wm_values *wm, + int plane); uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config); bool ilk_disable_lp_wm(struct drm_device *dev); int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7fd299e..2c12b66 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3798,6 +3798,42 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, I915_WRITE(reg, 0); } +void skl_write_plane_wm(struct intel_crtc *intel_crtc, + const struct skl_wm_values *wm, + int plane) +{ + struct drm_crtc *crtc = &intel_crtc->base; + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + int level, max_level = ilk_wm_max_level(dev); + enum pipe pipe = intel_crtc->pipe; + + if (!(wm->dirty_pipes & drm_crtc_mask(crtc))) + return; + + for (level = 0; level <= max_level; level++) { + I915_WRITE(PLANE_WM(pipe, plane, level), + wm->plane[pipe][plane][level]); + } + I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]); +} + +void skl_write_cursor_wm(struct intel_crtc *intel_crtc, + const struct skl_wm_values *wm) +{ + struct drm_crtc *crtc = &intel_crtc->base; + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + int level, max_level = ilk_wm_max_level(dev); + enum pipe pipe = intel_crtc->pipe; + + for (level = 0; level <= max_level; level++) { + I915_WRITE(CUR_WM(pipe, level), + wm->plane[pipe][PLANE_CURSOR][level]); + } + I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]); +} + static void skl_write_wm_values(struct drm_i915_private *dev_priv, const struct skl_wm_values *new) { @@ -3805,7 +3841,7 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv, struct intel_crtc *crtc; for_each_intel_crtc(dev, crtc) { - int i, level, max_level = ilk_wm_max_level(dev); + int i; enum pipe pipe = crtc->pipe; if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0) @@ -3813,21 +3849,6 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv, if (!crtc->active) continue; - I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); - - for (level = 0; level <= max_level; level++) { - for (i = 0; i < intel_num_planes(crtc); i++) - I915_WRITE(PLANE_WM(pipe, i, level), - new->plane[pipe][i][level]); - I915_WRITE(CUR_WM(pipe, level), - new->plane[pipe][PLANE_CURSOR][level]); - } - for (i = 0; i < intel_num_planes(crtc); i++) - I915_WRITE(PLANE_WM_TRANS(pipe, i), - new->plane_trans[pipe][i]); - I915_WRITE(CUR_WM_TRANS(pipe), - new->plane_trans[pipe][PLANE_CURSOR]); - for (i = 0; i < intel_num_planes(crtc); i++) { skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, i), diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 0de935a..55d173f 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -203,6 +203,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct intel_plane *intel_plane = to_intel_plane(drm_plane); struct drm_framebuffer *fb = plane_state->base.fb; struct drm_i915_gem_object *obj = intel_fb_obj(fb); + struct skl_wm_values *wm = &dev_priv->wm.skl_results; + struct drm_crtc *crtc = crtc_state->base.crtc; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); const int pipe = intel_plane->pipe; const int plane = intel_plane->plane + 1; u32 plane_ctl, stride_div, stride; @@ -238,6 +241,9 @@ skl_update_plane(struct drm_plane *drm_plane, crtc_w--; crtc_h--; + if (wm->dirty_pipes & drm_crtc_mask(crtc)) + skl_write_plane_wm(intel_crtc, wm, plane); + if (key->flags) { I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); -- 2.7.4