From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lyude Paul Subject: Re: [PATCH v6 6/6] drm/i915/skl: Update DDB values atomically with wms/plane attrs Date: Wed, 03 Aug 2016 17:39:23 -0400 Message-ID: <1470260363.5153.34.camel@redhat.com> References: <1470177458-31984-1-git-send-email-cpaul@redhat.com> <1470177458-31984-7-git-send-email-cpaul@redhat.com> <20160803150042.GK4329@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20160803150042.GK4329@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ville =?ISO-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Hans de Goede , Daniel Vetter List-Id: dri-devel@lists.freedesktop.org T24gV2VkLCAyMDE2LTA4LTAzIGF0IDE4OjAwICswMzAwLCBWaWxsZSBTeXJqw6Rsw6Qgd3JvdGU6 Cj4gT24gVHVlLCBBdWcgMDIsIDIwMTYgYXQgMDY6Mzc6MzdQTSAtMDQwMCwgTHl1ZGUgd3JvdGU6 Cj4gPiAKPiA+IE5vdyB0aGF0IHdlIGNhbiBob29rIGludG8gdXBkYXRlX2NydGNzIGFuZCBjb250 cm9sIHRoZSBvcmRlciBpbiB3aGljaCB3ZQo+ID4gdXBkYXRlIENSVENzIGF0IGVhY2ggbW9kZXNl dCwgd2UgY2FuIGZpbmlzaCB0aGUgZmluYWwgc3RlcCBvZiBmaXhpbmcKPiA+IFNreWxha2UncyB3 YXRlcm1hcmsgaGFuZGxpbmcgYnkgcGVyZm9ybWluZyBEREIgdXBkYXRlcyBhdCB0aGUgc2FtZSB0 aW1lCj4gPiBhcyBwbGFuZSB1cGRhdGVzIGFuZCB3YXRlcm1hcmsgdXBkYXRlcy4KPiA+IAo+ID4g VGhlIGZpcnN0IG1ham9yIGNoYW5nZSBpbiB0aGlzIHBhdGNoIGlzIHNrbF91cGRhdGVfY3J0Y3Mo KSwgd2hpY2gKPiA+IGhhbmRsZXMgZW5zdXJpbmcgdGhhdCB3ZSBvcmRlciBlYWNoIENSVEMgdXBk YXRlIGluIG91ciBhdG9taWMgY29tbWl0cwo+ID4gcHJvcGVybHkgc28gdGhhdCB0aGV5IGhvbm9y IHRoZSBEREIgZmx1c2ggb3JkZXIuCj4gPiAKPiA+IFRoZSBzZWNvbmQgbWFqb3IgY2hhbmdlIGlu IHRoaXMgcGF0Y2ggaXMgdGhlIG9yZGVyIGluIHdoaWNoIHdlIGZsdXNoIHRoZQo+ID4gcGlwZXMu IFdoaWxlIHRoZSBwcmV2aW91cyBvcmRlciBtYXkgaGF2ZSB3b3JrZWQsIGl0IGNhbid0IGJlIHVz ZWQgaW4KPiA+IHRoaXMgYXBwcm9hY2ggc2luY2UgaXQgbm8gbG9uZ2VyIHdpbGwgZG8gdGhlIHJp Z2h0IHRoaW5nLiBGb3IgZXhhbXBsZSwKPiA+IHVzaW5nIHRoZSBvbGQgZGRiIGZsdXNoIG9yZGVy Ogo+ID4gCj4gPiBXZSBoYXZlIHBpcGVzIEEsIEIsIGFuZCBDIGVuYWJsZWQsIGFuZCB3ZSdyZSBk aXNhYmxpbmcgQy4gSW5pdGlhbCBkZGIKPiA+IGFsbG9jYXRpb24gbG9va3MgbGlrZSB0aGlzOgo+ ID4gCj4gPiA+IAo+ID4gPiDCoCBBwqDCoMKgfMKgwqDCoELCoMKgwqB8eHh4eHh4eHwKPiA+IAo+ ID4gU2luY2Ugd2UncmUgcGVyZm9ybWluZyB0aGUgZGRiIHVwZGF0ZXMgYWZ0ZXIgcGVyZm9ybWlu ZyBhbnkgQ1JUQwo+ID4gZGlzYWJsZW1lbnRzIGluIGludGVsX2F0b21pY19jb21taXRfdGFpbCgp LCB0aGUgc3BhY2UgdG8gdGhlIHJpZ2h0IG9mCj4gPiBwaXBlIEIgaXMgdW5hbGxvY2F0ZWQuCj4g PiAKPiA+IDEuIEZsdXNoIHBpcGVzIHdpdGggbmV3IGFsbG9jYXRpb24gY29udGFpbmVkIGludG8g b2xkIHNwYWNlLiBOb25lCj4gPiDCoMKgwqBhcHBseSwgc28gd2Ugc2tpcCB0aGlzCj4gPiAyLiBG bHVzaCBwaXBlcyBoYXZpbmcgdGhlaXIgYWxsb2NhdGlvbiByZWR1Y2VkLCBidXQgb3ZlcmxhcHBp bmcgd2l0aCBhCj4gPiDCoMKgwqBwcmV2aW91cyBhbGxvY2F0aW9uLiBOb25lIGFwcGx5LCBzbyB3 ZSBhbHNvIHNraXAgdGhpcwo+ID4gMy4gRmx1c2ggcGlwZXMgdGhhdCBnb3QgbW9yZSBzcGFjZSBh bGxvY2F0ZWQuIFRoaXMgYXBwbGllcyB0byBBIGFuZCBCLAo+ID4gwqDCoMKgZ2l2aW5nIHVzIHRo ZSBmb2xsb3dpbmcgdXBkYXRlIG9yZGVyOiBBLCBCCj4gPiAKPiA+IFRoaXMgaXMgd3JvbmcsIHNp bmNlIHVwZGF0aW5nIHBpcGUgQSBmaXJzdCB3aWxsIGNhdXNlIGl0IHRvIG92ZXJsYXAgd2l0aAo+ ID4gQiBhbmQgcG90ZW50aWFsbHkgYnVyc3QgaW50byBmbGFtZXMuIE91ciBuZXcgb3JkZXIgKHNl ZSB0aGUgY29kZQo+ID4gY29tbWVudHMgZm9yIGRldGFpbHMpIHdvdWxkIHVwZGF0ZSB0aGUgcGlw ZXMgaW4gdGhlIHByb3BlciBvcmRlcjogQiwgQS4KPiA+IAo+ID4gQXMgd2VsbCwgd2UgY2FsY3Vs YXRlIHRoZSBvcmRlciBmb3IgZWFjaCBEREIgdXBkYXRlIGR1cmluZyB0aGUgY2hlY2sKPiA+IHBo YXNlLCBhbmQgcmVmZXJlbmNlIGl0IGxhdGVyIGluIHRoZSBjb21taXQgcGhhc2Ugd2hlbiB3ZSBo aXQKPiA+IHNrbF91cGRhdGVfY3J0Y3MoKS4KPiA+IAo+ID4gVGhpcyBsb25nIG92ZXJkdWUgcGF0 Y2ggZml4ZXMgdGhlIHJlc3Qgb2YgdGhlIHVuZGVycnVucyBvbiBTa3lsYWtlLgo+ID4gCj4gPiBD aGFuZ2VzIHNpbmNlIHYxOgo+ID4gwqAtIEFkZCBza2xfZGRiX2VudHJ5X3dyaXRlKCkgZm9yIGN1 cnNvciBpbnRvIHNrbF93cml0ZV9jdXJzb3Jfd20oKQo+ID4gCj4gPiBGaXhlczogMGU4ZmI3YmE3 Y2E1ICgiZHJtL2k5MTUvc2tsOiBGbHVzaCB0aGUgV00gY29uZmlndXJhdGlvbiIpCj4gPiBGaXhl czogODIxMWJkNWJkZjVlICgiZHJtL2k5MTUvc2tsOiBQcm9ncmFtIHRoZSBEREIgYWxsb2NhdGlv biIpCj4gPiBTaWduZWQtb2ZmLWJ5OiBMeXVkZSA8Y3BhdWxAcmVkaGF0LmNvbT4KPiA+IFtvbWl0 dGluZyBDQyBmb3Igc3RhYmxlLCBzaW5jZSB0aGlzIHBhdGNoIHdpbGwgbmVlZCB0byBiZSBjaGFu Z2VkIGZvcgo+ID4gc3VjaCBiYWNrcG9ydHMgZmlyc3RdCj4gPiBDYzogVmlsbGUgU3lyasOkbMOk IDx2aWxsZS5zeXJqYWxhQGxpbnV4LmludGVsLmNvbT4KPiA+IENjOiBEYW5pZWwgVmV0dGVyIDxk YW5pZWwudmV0dGVyQGludGVsLmNvbT4KPiA+IENjOiBSYWRoYWtyaXNobmEgU3JpcGFkYSA8cmFk aGFrcmlzaG5hLnNyaXBhZGFAaW50ZWwuY29tPgo+ID4gQ2M6IEhhbnMgZGUgR29lZGUgPGhkZWdv ZWRlQHJlZGhhdC5jb20+Cj4gPiBDYzogTWF0dCBSb3BlciA8bWF0dGhldy5kLnJvcGVyQGludGVs LmNvbT4KPiA+IC0tLQo+ID4gwqBkcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kaXNwbGF5LmMg fCAxMDAgKysrKysrKysrKy0tCj4gPiDCoGRyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rydi5o wqDCoMKgwqDCoHzCoMKgMTAgKysKPiA+IMKgZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfcG0u Y8KgwqDCoMKgwqDCoHwgMjg4ICsrKysrKysrKysrKysrKystLS0tLS0tLS0tLS0tLQo+ID4gLS0t LS0KPiA+IMKgMyBmaWxlcyBjaGFuZ2VkLCAyMzMgaW5zZXJ0aW9ucygrKSwgMTY1IGRlbGV0aW9u cygtKQo+ID4gCj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZGlz cGxheS5jCj4gPiBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rpc3BsYXkuYwo+ID4gaW5k ZXggNTljZjUxMy4uMDYyOTVmNyAxMDA2NDQKPiA+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1 L2ludGVsX2Rpc3BsYXkuYwo+ID4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZGlz cGxheS5jCj4gPiBAQCAtMTI4OTcsMTYgKzEyODk3LDIzIEBAIHN0YXRpYyB2b2lkIHZlcmlmeV93 bV9zdGF0ZShzdHJ1Y3QgZHJtX2NydGMgKmNydGMsCj4gPiDCoAkJCcKgwqBod19lbnRyeS0+c3Rh cnQsIGh3X2VudHJ5LT5lbmQpOwo+ID4gwqAJfQo+ID4gwqAKPiA+IC0JLyogY3Vyc29yICovCj4g PiAtCWh3X2VudHJ5ID0gJmh3X2RkYi5wbGFuZVtwaXBlXVtQTEFORV9DVVJTT1JdOwo+ID4gLQlz d19lbnRyeSA9ICZzd19kZGItPnBsYW5lW3BpcGVdW1BMQU5FX0NVUlNPUl07Cj4gPiAtCj4gPiAt CWlmICghc2tsX2RkYl9lbnRyeV9lcXVhbChod19lbnRyeSwgc3dfZW50cnkpKSB7Cj4gPiAtCQlE Uk1fRVJST1IoIm1pc21hdGNoIGluIEREQiBzdGF0ZSBwaXBlICVjIGN1cnNvciAiCj4gPiAtCQkJ wqDCoCIoZXhwZWN0ZWQgKCV1LCV1KSwgZm91bmQgKCV1LCV1KSlcbiIsCj4gPiAtCQkJwqDCoHBp cGVfbmFtZShwaXBlKSwKPiA+IC0JCQnCoMKgc3dfZW50cnktPnN0YXJ0LCBzd19lbnRyeS0+ZW5k LAo+ID4gLQkJCcKgwqBod19lbnRyeS0+c3RhcnQsIGh3X2VudHJ5LT5lbmQpOwo+ID4gKwkvKgo+ ID4gKwnCoCogY3Vyc29yCj4gPiArCcKgKiBJZiB0aGUgY3Vyc29yIHBsYW5lIGlzbid0IGFjdGl2 ZSwgd2UgbWF5IG5vdCBoYXZlIHVwZGF0ZWQgaXQncwo+ID4gZGRiCj4gPiArCcKgKiBhbGxvY2F0 aW9uLiBJbiB0aGF0IGNhc2Ugc2luY2UgdGhlIGRkYiBhbGxvY2F0aW9uIHdpbGwgYmUKPiA+IHVw ZGF0ZWQKPiA+ICsJwqAqIG9uY2UgdGhlIHBsYW5lIGJlY29tZXMgdmlzaWJsZSwgd2UgY2FuIHNr aXAgdGhpcyBjaGVjawo+ID4gKwnCoCovCj4gPiArCWlmIChpbnRlbF9jcnRjLT5jdXJzb3JfYWRk cikgewo+ID4gKwkJaHdfZW50cnkgPSAmaHdfZGRiLnBsYW5lW3BpcGVdW1BMQU5FX0NVUlNPUl07 Cj4gPiArCQlzd19lbnRyeSA9ICZzd19kZGItPnBsYW5lW3BpcGVdW1BMQU5FX0NVUlNPUl07Cj4g PiArCj4gPiArCQlpZiAoIXNrbF9kZGJfZW50cnlfZXF1YWwoaHdfZW50cnksIHN3X2VudHJ5KSkg ewo+ID4gKwkJCURSTV9FUlJPUigibWlzbWF0Y2ggaW4gRERCIHN0YXRlIHBpcGUgJWMgY3Vyc29y ICIKPiA+ICsJCQkJwqDCoCIoZXhwZWN0ZWQgKCV1LCV1KSwgZm91bmQgKCV1LCV1KSlcbiIsCj4g PiArCQkJCcKgwqBwaXBlX25hbWUocGlwZSksCj4gPiArCQkJCcKgwqBzd19lbnRyeS0+c3RhcnQs IHN3X2VudHJ5LT5lbmQsCj4gPiArCQkJCcKgwqBod19lbnRyeS0+c3RhcnQsIGh3X2VudHJ5LT5l bmQpOwo+ID4gKwkJfQo+ID4gwqAJfQo+ID4gwqB9Cj4gPiDCoAo+ID4gQEAgLTEzNjU4LDYgKzEz NjY1LDcyIEBAIHN0YXRpYyB2b2lkIGludGVsX3VwZGF0ZV9jcnRjcyhzdHJ1Y3QKPiA+IGRybV9h dG9taWNfc3RhdGUgKnN0YXRlLAo+ID4gwqAJfQo+ID4gwqB9Cj4gPiDCoAo+ID4gK3N0YXRpYyBp bmxpbmUgdm9pZAo+ID4gK3NrbF9kb19kZGJfc3RlcChzdHJ1Y3QgZHJtX2F0b21pY19zdGF0ZSAq c3RhdGUsCj4gPiArCQllbnVtIHNrbF9kZGJfc3RlcCBzdGVwKQo+ID4gK3sKPiA+ICsJc3RydWN0 IGludGVsX2F0b21pY19zdGF0ZSAqaW50ZWxfc3RhdGUgPQo+ID4gdG9faW50ZWxfYXRvbWljX3N0 YXRlKHN0YXRlKTsKPiA+ICsJc3RydWN0IGRybV9jcnRjICpjcnRjOwo+ID4gKwlzdHJ1Y3QgZHJt X2NydGNfc3RhdGUgKm9sZF9jcnRjX3N0YXRlOwo+ID4gKwl1bnNpZ25lZCBpbnQgY3J0Y192Ymxh bmtfbWFzazsgLyogdW51c2VkICovCj4gPiArCWludCBpOwo+ID4gKwo+ID4gKwlmb3JfZWFjaF9j cnRjX2luX3N0YXRlKHN0YXRlLCBjcnRjLCBvbGRfY3J0Y19zdGF0ZSwgaSkgewo+ID4gKwkJc3Ry dWN0IGludGVsX2NydGMgKmludGVsX2NydGMgPSB0b19pbnRlbF9jcnRjKGNydGMpOwo+ID4gKwkJ c3RydWN0IGludGVsX2NydGNfc3RhdGUgKmNzdGF0ZSA9Cj4gPiArCQkJdG9faW50ZWxfY3J0Y19z dGF0ZShjcnRjLT5zdGF0ZSk7Cj4gPiArCQlib29sIHZibGFua193YWl0ID0gZmFsc2U7Cj4gPiAr Cj4gPiArCQlpZiAoY3N0YXRlLT53bS5za2wuZGRiX3JlYWxsb2MgIT0gc3RlcCB8fCAhY3J0Yy0+ c3RhdGUtCj4gPiA+YWN0aXZlKQo+ID4gKwkJCWNvbnRpbnVlOwo+ID4gKwo+ID4gKwkJLyoKPiA+ ICsJCcKgKiBJZiB3ZSdyZSBjaGFuZ2luZyB0aGUgZGRiIGFsbG9jYXRpb24gb2YgdGhpcyBwaXBl IHRvCj4gPiBtYWtlCj4gPiArCQnCoCogcm9vbSBmb3IgYW5vdGhlciBwaXBlLCB3ZSBoYXZlIHRv IHdhaXQgZm9yIHRoZSBwaXBlJ3MKPiA+IGRkYgo+ID4gKwkJwqAqIGFsbG9jYXRpb25zIHRvIGFj dHVhbGx5IHVwZGF0ZSBieSB3YWl0aW5nIGZvciBhIHZibGFuay4KPiA+ICsJCcKgKiBPdGhlcndp c2Ugd2UgcmlzayB0aGUgbmV4dCBwaXBlIHVwZGF0aW5nIGJlZm9yZSB0aGlzCj4gPiBwaXBlCj4g PiArCQnCoCogZmluaXNoZXMsIHJlc3VsdGluZyBpbiB0aGUgcGlwZSBmZXRjaGluZyBmcm9tIGRk YiBzcGFjZQo+ID4gZm9yCj4gPiArCQnCoCogdGhlIHdyb25nIHBpcGUuCj4gPiArCQnCoCoKPiA+ ICsJCcKgKiBIb3dldmVyLCBpZiB3ZSBrbm93IHdlIGRvbid0IGhhdmUgYW55IG1vcmUgcGlwZXMg dG8gbW92ZQo+ID4gKwkJwqAqIGFyb3VuZCwgd2UgY2FuIHNraXAgdGhpcyB3YWl0IGFuZCB0aGUg bmV3IGRkYiBhbGxvY2F0aW9uCj4gPiArCQnCoCogd2lsbCB0YWtlIGVmZmVjdCBhdCB0aGUgc3Rh cnQgb2YgdGhlIG5leHQgdmJsYW5rLgo+ID4gKwkJwqAqLwo+ID4gKwkJc3dpdGNoIChzdGVwKSB7 Cj4gPiArCQljYXNlIFNLTF9EREJfU1RFUF9OT19PVkVSTEFQOgo+ID4gKwkJY2FzZSBTS0xfRERC X1NURVBfT1ZFUkxBUDoKPiA+ICsJCQlpZiAoc3RlcCAhPSBpbnRlbF9zdGF0ZS0+bGFzdF9kZGJf c3RlcCkKPiA+ICsJCQkJdmJsYW5rX3dhaXQgPSB0cnVlOwo+ID4gKwo+ID4gKwkJLyogZHJvcCB0 aHJvdWdoICovCj4gPiArCQljYXNlIFNLTF9EREJfU1RFUF9GSU5BTDoKPiA+ICsJCQlEUk1fREVC VUdfS01TKAo+ID4gKwkJCcKgwqDCoMKgIlVwZGF0aW5nIFtDUlRDOiVkOnBpcGUgJWNdIGZvciBE REIgc3RlcCAlZFxuIiwKPiA+ICsJCQnCoMKgwqDCoGNydGMtPmJhc2UuaWQsIHBpcGVfbmFtZShp bnRlbF9jcnRjLT5waXBlKSwKPiA+ICsJCQnCoMKgwqDCoHN0ZXApOwo+ID4gKwo+ID4gKwkJY2Fz ZSBTS0xfRERCX1NURVBfTk9ORToKPiA+ICsJCQlicmVhazsKPiA+ICsJCX0KPiAKPiBOb3Qgc3Vy ZSB3ZSByZWFsbHkgbmVlZCB0aGlzIHN0ZXAgc3R1ZmYuIEhvdyBhYm91dD8KPiAKPiBmb3JfZWFj aF9jcnRjCj4gCWlmIChjcnRjX25lZWRzX2Rpc2FibGluZykKPiAJCWRpc2FibGVfY3J0YygpOwo+ IAo+IGRvIHsKPiAJcHJvZ3Jlc3MgPSBmYWxzZTsKPiAJd2FpdF92YmxfcGlwZXM9MDsKPiAJZm9y X2VhY2hfY3J0YygpIHsKPiAJCWlmICghYWN0aXZlIHx8IG5lZWRzX21vZGVzZXQpCj4gCQkJY29u dGludWU7Cj4gCQlpZiAoIWRkYl9jaGFuZ2VkKQo+IAkJCWNvbnRpbnVlOwo+IAkJaWYgKG5ld19k ZGJfb3ZlcmxhcHNfd2l0aF9hbnlfb3RoZXJfcGlwZXNfY3VycmVudF9kZGIpCj4gCQkJY29udGlu dWU7Cj4gCQljb21taXQ7Cj4gCQl3YWl0X3ZibF9waXBlcyB8PSBwaXBlOwo+IAkJcHJvZ3Jlc3Mg PSB0cnVlOwo+IAl9Cj4gCXdhaXRfdmJscyh3YWl0X3ZibF9waXBlcyk7Cj4gfSB3aGlsZSAocHJv Z3Jlc3MpOwo+IAo+IGZvcl9lYWNoX2NydGMKPiAJaWYgKGNydGNfbmVlZHNfZW5hYmxpbmcpCj4g CQllbmFibGVfY3J0YygpOwo+IAljb21taXQ7Cj4gfQoKSSdtIGZpbmUgd2l0aCB0aGlzLCBpdCBt aWdodCBtYWtlIHRoaXMgbG9naWMgYSBsaXR0bGUgZWFzaWVyIHRvIHJlYWQuwqAKPiAKPiBPciBp ZiB3ZSdyZSBwYXJhbm9pZCwgd2UgY291bGQgYWxzbyBoYXZlIGFuIHVwcGVyIGJvdW5kIG9uIHRo ZQo+IGxvb3AgYW5kIGFzc2VydCB0aGF0IHdlIG5ldmVyIHJlYWNoIGl0Lgo+IAo+IAo+IFRob3Vn aCBvbmUgdGhpbmcgSSBkb24ndCBwYXJ0aWN1bGFybHkgbGlrZSBhYm91dCB0aGlzIGNvbW1pdCB3 aGlsZQo+IGNoYW5naW5nIHRoZSBkZGIgYXBwcm9hY2ggaXMgdGhhdCBpdCdzIGdvaW5nIHRvIG1h a2UgdGhlIHVwZGF0ZQo+IGFwcGVhciBldmVuIGxlc3MgYXRvbWljLiBXaGF0IEknZCByYXRoZXIg bGlrZSB0byBkbyBmb3IgdGhlIG5vcm1hbAo+IGNvbW1pdCBwYXRoIGlzIHRoaXM6Cj4gCj4gZm9y X2VhY2hfY3J0Ywo+IAlpZiAoY3J0Y19uZWVkc19kaXNhYmxpbmcpCj4gCQlkaXNhYmxlX3BsYW5l cwo+IGZvcl9lYWNoX2NydGMKPiAJaWYgKGNydGNfbmVlZHNfZGlzYWJsaW5nKQo+IAkJZGlzYWJs ZV9jcnRjCj4gZm9yX2VhY2hfY3J0Ywo+IAlpZiAoY3J0Y19uZWVkc19lbmFibGluZykKPiAJCWVu YWJsZV9jcnRjCj4gZm9yX2VhY2hfY3J0Ywo+IAlpZiAoYWN0aXZlKQo+IAkJY29tbWl0X3BsYW5l czsKPiAKPiBUaGF0IHdheSBldmVyeXRoaW5nIHdvdWxkIHBvcCBpbiBhbmQgb3V0IGFzIGNsb3Nl IHRvZ2V0aGVyIGFzIHBvc3NpYmxlLgo+IEhtbS4gQWN0dWFsbHksIEkgd29uZGVyLi4uIEknbSB0 aGlua2luZyB3ZSBzaG91bGQgYmUgYWJsZSB0byBlbmFibGUgYWxsCj4gY3J0Y3MgcHJpb3IgdG8g ZW50ZXJpbmcgdGhlIGRkYiBjb21taXQgbG9vcCwgb24gYWNjb3VudCBvZiBubyBwbGFuZXMKPiBi ZWluZyBlbmFibGVkIG9uIHRob3NlIGNydGNzIHVudGlsIHdlIGNvbW1pdCB0aGVtLiBBbmQgaWYg bm8gcGxhbmVzIGFyZQo+IGVuYWJsZWQsIHJ1bm5pbmcgdGhlIHBpcGUgdy9vIGFsbG9jYXRlZCBk ZGIgc2hvdWxkIGJlIGZpbmUuIFNvIHdpdGggdGhhdAo+IGFwcHJvYWNoLCBJIHRoaW5rIHdlIHNo b3VsZCBiZSBhYmxlIHRvIGNvbW1pdCBhbGwgcGxhbmVzIHdpdGhpbiBhIGZldwo+IGl0ZXJhdGlv bnMgb2YgdGhlIGxvb3AsIGFuZCBoZW5jZSB3aXRoaW4gYSBmZXcgdmJsYW5rcy4KCkkgY2FuJ3Qg c2VlIGFueSBpc3N1ZXMgd2l0aCB0aGlzLCBhbmQgdGhpcyB3b3VsZCBkZWZpbml0ZWx5IG1ha2Ug dGhlIGNvZGUgYSBsb3QKY2xlYW5lci4gSSdtIGFscmlnaHQgd2l0aCBnb2luZyB0aGlzIHJvdXRl IGlmIG1hdHQgZG9lc24ndCBzZWUgYW55IGlzc3VlcyB3aXRoCml0IGFzIHdlbGwuCgpDaGVlcnMs CglMeXVkZQoKPiAKPiA+IAo+ID4gKwo+ID4gKwkJaW50ZWxfdXBkYXRlX2NydGMoY3J0Yywgc3Rh dGUsIG9sZF9jcnRjX3N0YXRlLAo+ID4gKwkJCQnCoMKgJmNydGNfdmJsYW5rX21hc2spOwo+ID4g Kwo+ID4gKwkJaWYgKHZibGFua193YWl0KQo+ID4gKwkJCWludGVsX3dhaXRfZm9yX3ZibGFuayhz dGF0ZS0+ZGV2LCBpbnRlbF9jcnRjLQo+ID4gPnBpcGUpOwo+ID4gKwl9Cj4gPiArfQo+ID4gKwo+ ID4gK3N0YXRpYyB2b2lkIHNrbF91cGRhdGVfY3J0Y3Moc3RydWN0IGRybV9hdG9taWNfc3RhdGUg KnN0YXRlLAo+ID4gKwkJCcKgwqDCoMKgwqB1bnNpZ25lZCBpbnQgKmNydGNfdmJsYW5rX21hc2sp Cj4gPiArewo+ID4gKwlzdHJ1Y3QgaW50ZWxfYXRvbWljX3N0YXRlICppbnRlbF9zdGF0ZSA9Cj4g PiB0b19pbnRlbF9hdG9taWNfc3RhdGUoc3RhdGUpOwo+ID4gKwllbnVtIHNrbF9kZGJfc3RlcCBz dGVwOwo+ID4gKwo+ID4gKwlmb3IgKHN0ZXAgPSAwOyBzdGVwIDw9IGludGVsX3N0YXRlLT5sYXN0 X2RkYl9zdGVwOyBzdGVwKyspCj4gPiArCQlza2xfZG9fZGRiX3N0ZXAoc3RhdGUsIHN0ZXApOwo+ ID4gK30KPiA+ICsKPiA+IMKgc3RhdGljIHZvaWQgaW50ZWxfYXRvbWljX2NvbW1pdF90YWlsKHN0 cnVjdCBkcm1fYXRvbWljX3N0YXRlICpzdGF0ZSkKPiA+IMKgewo+ID4gwqAJc3RydWN0IGRybV9k ZXZpY2UgKmRldiA9IHN0YXRlLT5kZXY7Cj4gPiBAQCAtMTUyMzUsOCArMTUzMDgsNiBAQCB2b2lk IGludGVsX2luaXRfZGlzcGxheV9ob29rcyhzdHJ1Y3QKPiA+IGRybV9pOTE1X3ByaXZhdGUgKmRl dl9wcml2KQo+ID4gwqAJCWRldl9wcml2LT5kaXNwbGF5LmNydGNfZGlzYWJsZSA9IGk5eHhfY3J0 Y19kaXNhYmxlOwo+ID4gwqAJfQo+ID4gwqAKPiA+IC0JZGV2X3ByaXYtPmRpc3BsYXkudXBkYXRl X2NydGNzID0gaW50ZWxfdXBkYXRlX2NydGNzOwo+ID4gLQo+ID4gwqAJLyogUmV0dXJucyB0aGUg Y29yZSBkaXNwbGF5IGNsb2NrIHNwZWVkICovCj4gPiDCoAlpZiAoSVNfU0tZTEFLRShkZXZfcHJp dikgfHwgSVNfS0FCWUxBS0UoZGV2X3ByaXYpKQo+ID4gwqAJCWRldl9wcml2LT5kaXNwbGF5Lmdl dF9kaXNwbGF5X2Nsb2NrX3NwZWVkID0KPiA+IEBAIC0xNTMyNiw2ICsxNTM5NywxMSBAQCB2b2lk IGludGVsX2luaXRfZGlzcGxheV9ob29rcyhzdHJ1Y3QKPiA+IGRybV9pOTE1X3ByaXZhdGUgKmRl dl9wcml2KQo+ID4gwqAJCQlza2xfbW9kZXNldF9jYWxjX2NkY2xrOwo+ID4gwqAJfQo+ID4gwqAK PiA+ICsJaWYgKGRldl9wcml2LT5pbmZvLmdlbiA+PSA5KQo+ID4gKwkJZGV2X3ByaXYtPmRpc3Bs YXkudXBkYXRlX2NydGNzID0gc2tsX3VwZGF0ZV9jcnRjczsKPiA+ICsJZWxzZQo+ID4gKwkJZGV2 X3ByaXYtPmRpc3BsYXkudXBkYXRlX2NydGNzID0gaW50ZWxfdXBkYXRlX2NydGNzOwo+ID4gKwo+ ID4gwqAJc3dpdGNoIChJTlRFTF9JTkZPKGRldl9wcml2KS0+Z2VuKSB7Cj4gPiDCoAljYXNlIDI6 Cj4gPiDCoAkJZGV2X3ByaXYtPmRpc3BsYXkucXVldWVfZmxpcCA9IGludGVsX2dlbjJfcXVldWVf ZmxpcDsKPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcnYuaAo+ ID4gYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcnYuaAo+ID4gaW5kZXggMWI0NDRkMy4u Y2Y1ZGE4MyAxMDA2NDQKPiA+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rydi5o Cj4gPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcnYuaAo+ID4gQEAgLTMzNCw2 ICszMzQsNyBAQCBzdHJ1Y3QgaW50ZWxfYXRvbWljX3N0YXRlIHsKPiA+IMKgCj4gPiDCoAkvKiBH ZW45KyBvbmx5ICovCj4gPiDCoAlzdHJ1Y3Qgc2tsX3dtX3ZhbHVlcyB3bV9yZXN1bHRzOwo+ID4g KwlpbnQgbGFzdF9kZGJfc3RlcDsKPiA+IMKgfTsKPiA+IMKgCj4gPiDCoHN0cnVjdCBpbnRlbF9w bGFuZV9zdGF0ZSB7Cj4gPiBAQCAtNDM3LDYgKzQzOCwxMyBAQCBzdHJ1Y3Qgc2tsX3BpcGVfd20g ewo+ID4gwqAJdWludDMyX3QgbGluZXRpbWU7Cj4gPiDCoH07Cj4gPiDCoAo+ID4gK2VudW0gc2ts X2RkYl9zdGVwIHsKPiA+ICsJU0tMX0REQl9TVEVQX05PTkUgPSAwLAo+ID4gKwlTS0xfRERCX1NU RVBfTk9fT1ZFUkxBUCwKPiA+ICsJU0tMX0REQl9TVEVQX09WRVJMQVAsCj4gPiArCVNLTF9EREJf U1RFUF9GSU5BTAo+ID4gK307Cj4gPiArCj4gPiDCoHN0cnVjdCBpbnRlbF9jcnRjX3dtX3N0YXRl IHsKPiA+IMKgCXVuaW9uIHsKPiA+IMKgCQlzdHJ1Y3Qgewo+ID4gQEAgLTQ2Nyw2ICs0NzUsOCBA QCBzdHJ1Y3QgaW50ZWxfY3J0Y193bV9zdGF0ZSB7Cj4gPiDCoAkJCS8qIG1pbmltdW0gYmxvY2sg YWxsb2NhdGlvbiAqLwo+ID4gwqAJCQl1aW50MTZfdCBtaW5pbXVtX2Jsb2Nrc1tJOTE1X01BWF9Q TEFORVNdOwo+ID4gwqAJCQl1aW50MTZfdCBtaW5pbXVtX3lfYmxvY2tzW0k5MTVfTUFYX1BMQU5F U107Cj4gPiArCj4gPiArCQkJZW51bSBza2xfZGRiX3N0ZXAgZGRiX3JlYWxsb2M7Cj4gPiDCoAkJ fSBza2w7Cj4gPiDCoAl9Owo+ID4gwqAKPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0v aTkxNS9pbnRlbF9wbS5jCj4gPiBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX3BtLmMKPiA+ IGluZGV4IDZmNWJlYjMuLjYzNmM5MGEgMTAwNjQ0Cj4gPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0v aTkxNS9pbnRlbF9wbS5jCj4gPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wbS5j Cj4gPiBAQCAtMzgxNiw2ICszODE2LDExIEBAIHZvaWQgc2tsX3dyaXRlX3BsYW5lX3dtKHN0cnVj dCBpbnRlbF9jcnRjCj4gPiAqaW50ZWxfY3J0YywKPiA+IMKgCQkJwqDCoMKgd20tPnBsYW5lW3Bp cGVdW3BsYW5lXVtsZXZlbF0pOwo+ID4gwqAJfQo+ID4gwqAJSTkxNV9XUklURShQTEFORV9XTV9U UkFOUyhwaXBlLCBwbGFuZSksIHdtLQo+ID4gPnBsYW5lX3RyYW5zW3BpcGVdW3BsYW5lXSk7Cj4g PiArCj4gPiArCXNrbF9kZGJfZW50cnlfd3JpdGUoZGV2X3ByaXYsIFBMQU5FX0JVRl9DRkcocGlw ZSwgcGxhbmUpLAo+ID4gKwkJCcKgwqDCoMKgJndtLT5kZGIucGxhbmVbcGlwZV1bcGxhbmVdKTsK PiA+ICsJc2tsX2RkYl9lbnRyeV93cml0ZShkZXZfcHJpdiwgUExBTkVfTlYxMl9CVUZfQ0ZHKHBp cGUsIHBsYW5lKSwKPiA+ICsJCQnCoMKgwqDCoCZ3bS0+ZGRiLnlfcGxhbmVbcGlwZV1bcGxhbmVd KTsKPiA+IMKgfQo+ID4gwqAKPiA+IMKgdm9pZCBza2xfd3JpdGVfY3Vyc29yX3dtKHN0cnVjdCBp bnRlbF9jcnRjICppbnRlbF9jcnRjLAo+ID4gQEAgLTM4MzIsMTcwICszODM3LDUxIEBAIHZvaWQg c2tsX3dyaXRlX2N1cnNvcl93bShzdHJ1Y3QgaW50ZWxfY3J0Ywo+ID4gKmludGVsX2NydGMsCj4g PiDCoAkJCcKgwqDCoHdtLT5wbGFuZVtwaXBlXVtQTEFORV9DVVJTT1JdW2xldmVsXSk7Cj4gPiDC oAl9Cj4gPiDCoAlJOTE1X1dSSVRFKENVUl9XTV9UUkFOUyhwaXBlKSwgd20tCj4gPiA+cGxhbmVf dHJhbnNbcGlwZV1bUExBTkVfQ1VSU09SXSk7Cj4gPiAtfQo+ID4gLQo+ID4gLXN0YXRpYyB2b2lk IHNrbF93cml0ZV93bV92YWx1ZXMoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2LAo+ ID4gLQkJCQljb25zdCBzdHJ1Y3Qgc2tsX3dtX3ZhbHVlcyAqbmV3KQo+ID4gLXsKPiA+IC0Jc3Ry dWN0IGRybV9kZXZpY2UgKmRldiA9ICZkZXZfcHJpdi0+ZHJtOwo+ID4gLQlzdHJ1Y3QgaW50ZWxf Y3J0YyAqY3J0YzsKPiA+IC0KPiA+IC0JZm9yX2VhY2hfaW50ZWxfY3J0YyhkZXYsIGNydGMpIHsK PiA+IC0JCWludCBpOwo+ID4gLQkJZW51bSBwaXBlIHBpcGUgPSBjcnRjLT5waXBlOwo+ID4gLQo+ ID4gLQkJaWYgKChuZXctPmRpcnR5X3BpcGVzICYgZHJtX2NydGNfbWFzaygmY3J0Yy0+YmFzZSkp ID09IDApCj4gPiAtCQkJY29udGludWU7Cj4gPiAtCQlpZiAoIWNydGMtPmFjdGl2ZSkKPiA+IC0J CQljb250aW51ZTsKPiA+IMKgCj4gPiAtCQlmb3IgKGkgPSAwOyBpIDwgaW50ZWxfbnVtX3BsYW5l cyhjcnRjKTsgaSsrKSB7Cj4gPiAtCQkJc2tsX2RkYl9lbnRyeV93cml0ZShkZXZfcHJpdiwKPiA+ IC0JCQkJCcKgwqDCoMKgUExBTkVfQlVGX0NGRyhwaXBlLCBpKSwKPiA+IC0JCQkJCcKgwqDCoMKg Jm5ldy0+ZGRiLnBsYW5lW3BpcGVdW2ldKTsKPiA+IC0JCQlza2xfZGRiX2VudHJ5X3dyaXRlKGRl dl9wcml2LAo+ID4gLQkJCQkJwqDCoMKgwqBQTEFORV9OVjEyX0JVRl9DRkcocGlwZSwgaSksCj4g PiAtCQkJCQnCoMKgwqDCoCZuZXctPmRkYi55X3BsYW5lW3BpcGVdW2ldKTsKPiA+IC0JCX0KPiA+ IC0KPiA+IC0JCXNrbF9kZGJfZW50cnlfd3JpdGUoZGV2X3ByaXYsIENVUl9CVUZfQ0ZHKHBpcGUp LAo+ID4gLQkJCQnCoMKgwqDCoCZuZXctPmRkYi5wbGFuZVtwaXBlXVtQTEFORV9DVVJTT1JdKTsK PiA+IC0JfQo+ID4gKwlza2xfZGRiX2VudHJ5X3dyaXRlKGRldl9wcml2LCBDVVJfQlVGX0NGRyhw aXBlKSwKPiA+ICsJCQnCoMKgwqDCoCZ3bS0+ZGRiLnBsYW5lW3BpcGVdW1BMQU5FX0NVUlNPUl0p Owo+ID4gwqB9Cj4gPiDCoAo+ID4gLS8qCj4gPiAtICogV2hlbiBzZXR0aW5nIHVwIGEgbmV3IERE QiBhbGxvY2F0aW9uIGFycmFuZ2VtZW50LCB3ZSBuZWVkIHRvIGNvcnJlY3RseQo+ID4gLSAqIHNl cXVlbmNlIHRoZSB0aW1lcyBhdCB3aGljaCB0aGUgbmV3IGFsbG9jYXRpb25zIGZvciB0aGUgcGlw ZXMgYXJlIHRha2VuCj4gPiBpbnRvCj4gPiAtICogYWNjb3VudCBvciB3ZSdsbCBoYXZlIHBpcGVz IGZldGNoaW5nIGZyb20gc3BhY2UgcHJldmlvdXNseSBhbGxvY2F0ZWQgdG8KPiA+IC0gKiBhbm90 aGVyIHBpcGUuCj4gPiAtICoKPiA+IC0gKiBSb3VnaGx5IHRoZSBzZXF1ZW5jZSBsb29rcyBsaWtl Ogo+ID4gLSAqwqDCoDEuIHJlLWFsbG9jYXRlIHRoZSBwaXBlKHMpIHdpdGggdGhlIGFsbG9jYXRp b24gYmVpbmcgcmVkdWNlZCBhbmQgbm90Cj4gPiAtICrCoMKgwqDCoMKgb3ZlcmxhcHBpbmcgd2l0 aCBhIHByZXZpb3VzIGxpZ2h0LXVwIHBpcGUgKGFub3RoZXIgd2F5IHRvIHB1dCBpdCBpczoKPiA+ IC0gKsKgwqDCoMKgwqBwaXBlcyB3aXRoIHRoZWlyIG5ldyBhbGxvY2F0aW9uIHN0cmlja2x5IGlu Y2x1ZGVkIGludG8gdGhlaXIgb2xkCj4gPiBvbmVzKS4KPiA+IC0gKsKgwqAyLiByZS1hbGxvY2F0 ZSB0aGUgb3RoZXIgcGlwZXMgdGhhdCBnZXQgdGhlaXIgYWxsb2NhdGlvbiByZWR1Y2VkCj4gPiAt ICrCoMKgMy4gYWxsb2NhdGUgdGhlIHBpcGVzIGhhdmluZyB0aGVpciBhbGxvY2F0aW9uIGluY3Jl YXNlZAo+ID4gLSAqCj4gPiAtICogU3RlcHMgMS4gYW5kIDIuIGFyZSBoZXJlIHRvIHRha2UgY2Fy ZSBvZiB0aGUgZm9sbG93aW5nIGNhc2U6Cj4gPiAtICogLSBJbml0aWFsbHkgRERCIGxvb2tzIGxp a2UgdGhpczoKPiA+IC0gKsKgwqDCoMKgwqB8wqDCoMKgQsKgwqDCoMKgfMKgwqDCoEPCoMKgwqDC oHwKPiA+IC0gKiAtIGVuYWJsZSBwaXBlIEEuCj4gPiAtICogLSBwaXBlIEIgaGFzIGEgcmVkdWNl ZCBEREIgYWxsb2NhdGlvbiB0aGF0IG92ZXJsYXBzIHdpdGggdGhlIG9sZCBwaXBlIEMKPiA+IC0g KsKgwqDCoGFsbG9jYXRpb24KPiA+IC0gKsKgwqDCoMKgwqB8wqDCoEHCoMKgfMKgwqBCwqDCoHzC oMKgQ8KgwqB8Cj4gPiAtICoKPiA+IC0gKiBXZSBuZWVkIHRvIHNlcXVlbmNlIHRoZSByZS1hbGxv Y2F0aW9uOiBDLCBCLCBBIChhbmQgbm90IEIsIEMsIEEpLgo+ID4gLSAqLwo+ID4gLQo+ID4gLXN0 YXRpYyB2b2lkCj4gPiAtc2tsX3dtX2ZsdXNoX3BpcGUoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUg KmRldl9wcml2LCBlbnVtIHBpcGUgcGlwZSwgaW50Cj4gPiBwYXNzKQo+ID4gK3N0YXRpYyBib29s Cj4gPiArc2tsX2RkYl9hbGxvY2F0aW9uX2VxdWFscyhjb25zdCBzdHJ1Y3Qgc2tsX2RkYl9hbGxv Y2F0aW9uICpvbGQsCj4gPiArCQkJwqDCoGNvbnN0IHN0cnVjdCBza2xfZGRiX2FsbG9jYXRpb24g Km5ldywKPiA+ICsJCQnCoMKgZW51bSBwaXBlIHBpcGUpCj4gPiDCoHsKPiA+IC0JaW50IHBsYW5l Owo+ID4gLQo+ID4gLQlEUk1fREVCVUdfS01TKCJmbHVzaCBwaXBlICVjIChwYXNzICVkKVxuIiwg cGlwZV9uYW1lKHBpcGUpLCBwYXNzKTsKPiA+IC0KPiA+IC0JZm9yX2VhY2hfcGxhbmUoZGV2X3By aXYsIHBpcGUsIHBsYW5lKSB7Cj4gPiAtCQlJOTE1X1dSSVRFKFBMQU5FX1NVUkYocGlwZSwgcGxh bmUpLAo+ID4gLQkJCcKgwqDCoEk5MTVfUkVBRChQTEFORV9TVVJGKHBpcGUsIHBsYW5lKSkpOwo+ ID4gLQl9Cj4gPiAtCUk5MTVfV1JJVEUoQ1VSQkFTRShwaXBlKSwgSTkxNV9SRUFEKENVUkJBU0Uo cGlwZSkpKTsKPiA+ICsJcmV0dXJuIG5ldy0+cGlwZVtwaXBlXS5zdGFydCA9PSBvbGQtPnBpcGVb cGlwZV0uc3RhcnQgJiYKPiA+ICsJwqDCoMKgwqDCoMKgwqBuZXctPnBpcGVbcGlwZV0uZW5kID09 IG9sZC0+cGlwZVtwaXBlXS5lbmQ7Cj4gPiDCoH0KPiA+IMKgCj4gPiDCoHN0YXRpYyBib29sCj4g PiAtc2tsX2RkYl9hbGxvY2F0aW9uX2luY2x1ZGVkKGNvbnN0IHN0cnVjdCBza2xfZGRiX2FsbG9j YXRpb24gKm9sZCwKPiA+ICtza2xfZGRiX2FsbG9jYXRpb25fb3ZlcmxhcHMoc3RydWN0IGRybV9h dG9taWNfc3RhdGUgKnN0YXRlLAo+ID4gKwkJCcKgwqDCoMKgY29uc3Qgc3RydWN0IHNrbF9kZGJf YWxsb2NhdGlvbiAqb2xkLAo+ID4gwqAJCQnCoMKgwqDCoGNvbnN0IHN0cnVjdCBza2xfZGRiX2Fs bG9jYXRpb24gKm5ldywKPiA+IMKgCQkJwqDCoMKgwqBlbnVtIHBpcGUgcGlwZSkKPiA+IMKgewo+ ID4gLQl1aW50MTZfdCBvbGRfc2l6ZSwgbmV3X3NpemU7Cj4gPiAtCj4gPiAtCW9sZF9zaXplID0g c2tsX2RkYl9lbnRyeV9zaXplKCZvbGQtPnBpcGVbcGlwZV0pOwo+ID4gLQluZXdfc2l6ZSA9IHNr bF9kZGJfZW50cnlfc2l6ZSgmbmV3LT5waXBlW3BpcGVdKTsKPiA+IC0KPiA+IC0JcmV0dXJuIG9s ZF9zaXplICE9IG5ld19zaXplICYmCj4gPiAtCcKgwqDCoMKgwqDCoMKgbmV3LT5waXBlW3BpcGVd LnN0YXJ0ID49IG9sZC0+cGlwZVtwaXBlXS5zdGFydCAmJgo+ID4gLQnCoMKgwqDCoMKgwqDCoG5l dy0+cGlwZVtwaXBlXS5lbmQgPD0gb2xkLT5waXBlW3BpcGVdLmVuZDsKPiA+IC19Cj4gPiAtCj4g PiAtc3RhdGljIHZvaWQgc2tsX2ZsdXNoX3dtX3ZhbHVlcyhzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0 ZSAqZGV2X3ByaXYsCj4gPiAtCQkJCXN0cnVjdCBza2xfd21fdmFsdWVzICpuZXdfdmFsdWVzKQo+ ID4gLXsKPiA+IC0Jc3RydWN0IGRybV9kZXZpY2UgKmRldiA9ICZkZXZfcHJpdi0+ZHJtOwo+ID4g LQlzdHJ1Y3Qgc2tsX2RkYl9hbGxvY2F0aW9uICpjdXJfZGRiLCAqbmV3X2RkYjsKPiA+IC0JYm9v bCByZWFsbG9jYXRlZFtJOTE1X01BWF9QSVBFU10gPSB7fTsKPiA+IC0Jc3RydWN0IGludGVsX2Ny dGMgKmNydGM7Cj4gPiAtCWVudW0gcGlwZSBwaXBlOwo+ID4gLQo+ID4gLQluZXdfZGRiID0gJm5l d192YWx1ZXMtPmRkYjsKPiA+IC0JY3VyX2RkYiA9ICZkZXZfcHJpdi0+d20uc2tsX2h3LmRkYjsK PiA+IC0KPiA+IC0JLyoKPiA+IC0JwqAqIEZpcnN0IHBhc3M6IGZsdXNoIHRoZSBwaXBlcyB3aXRo IHRoZSBuZXcgYWxsb2NhdGlvbiBjb250YWluZWQKPiA+IGludG8KPiA+IC0JwqAqIHRoZSBvbGQg c3BhY2UuCj4gPiAtCcKgKgo+ID4gLQnCoCogV2UnbGwgd2FpdCBmb3IgdGhlIHZibGFuayBvbiB0 aG9zZSBwaXBlcyB0byBlbnN1cmUgd2UgY2FuIHNhZmVseQo+ID4gLQnCoCogcmUtYWxsb2NhdGUg dGhlIGZyZWVkIHNwYWNlIHdpdGhvdXQgdGhpcyBwaXBlIGZldGNoaW5nIGZyb20gaXQuCj4gPiAt CcKgKi8KPiA+IC0JZm9yX2VhY2hfaW50ZWxfY3J0YyhkZXYsIGNydGMpIHsKPiA+IC0JCWlmICgh Y3J0Yy0+YWN0aXZlKQo+ID4gLQkJCWNvbnRpbnVlOwo+ID4gLQo+ID4gLQkJcGlwZSA9IGNydGMt PnBpcGU7Cj4gPiAtCj4gPiAtCQlpZiAoIXNrbF9kZGJfYWxsb2NhdGlvbl9pbmNsdWRlZChjdXJf ZGRiLCBuZXdfZGRiLCBwaXBlKSkKPiA+IC0JCQljb250aW51ZTsKPiA+IC0KPiA+IC0JCXNrbF93 bV9mbHVzaF9waXBlKGRldl9wcml2LCBwaXBlLCAxKTsKPiA+IC0JCWludGVsX3dhaXRfZm9yX3Zi bGFuayhkZXYsIHBpcGUpOwo+ID4gLQo+ID4gLQkJcmVhbGxvY2F0ZWRbcGlwZV0gPSB0cnVlOwo+ ID4gLQl9Cj4gPiAtCj4gPiAtCj4gPiAtCS8qCj4gPiAtCcKgKiBTZWNvbmQgcGFzczogZmx1c2gg dGhlIHBpcGVzIHRoYXQgYXJlIGhhdmluZyB0aGVpciBhbGxvY2F0aW9uCj4gPiAtCcKgKiByZWR1 Y2VkLCBidXQgb3ZlcmxhcHBpbmcgd2l0aCBhIHByZXZpb3VzIGFsbG9jYXRpb24uCj4gPiAtCcKg Kgo+ID4gLQnCoCogSGVyZSBhcyB3ZWxsIHdlIG5lZWQgdG8gd2FpdCBmb3IgdGhlIHZibGFuayB0 byBtYWtlIHN1cmUgdGhlCj4gPiBmcmVlZAo+ID4gLQnCoCogc3BhY2UgaXMgbm90IHVzZWQgYW55 bW9yZS4KPiA+IC0JwqAqLwo+ID4gLQlmb3JfZWFjaF9pbnRlbF9jcnRjKGRldiwgY3J0Yykgewo+ ID4gLQkJaWYgKCFjcnRjLT5hY3RpdmUpCj4gPiAtCQkJY29udGludWU7Cj4gPiAtCj4gPiAtCQlw aXBlID0gY3J0Yy0+cGlwZTsKPiA+IC0KPiA+IC0JCWlmIChyZWFsbG9jYXRlZFtwaXBlXSkKPiA+ IC0JCQljb250aW51ZTsKPiA+IC0KPiA+IC0JCWlmIChza2xfZGRiX2VudHJ5X3NpemUoJm5ld19k ZGItPnBpcGVbcGlwZV0pIDwKPiA+IC0JCcKgwqDCoMKgc2tsX2RkYl9lbnRyeV9zaXplKCZjdXJf ZGRiLT5waXBlW3BpcGVdKSkgewo+ID4gLQkJCXNrbF93bV9mbHVzaF9waXBlKGRldl9wcml2LCBw aXBlLCAyKTsKPiA+IC0JCQlpbnRlbF93YWl0X2Zvcl92YmxhbmsoZGV2LCBwaXBlKTsKPiA+IC0J CQlyZWFsbG9jYXRlZFtwaXBlXSA9IHRydWU7Cj4gPiAtCQl9Cj4gPiAtCX0KPiA+IC0KPiA+IC0J LyoKPiA+IC0JwqAqIFRoaXJkIHBhc3M6IGZsdXNoIHRoZSBwaXBlcyB0aGF0IGdvdCBtb3JlIHNw YWNlIGFsbG9jYXRlZC4KPiA+IC0JwqAqCj4gPiAtCcKgKiBXZSBkb24ndCBuZWVkIHRvIGFjdGl2 ZWx5IHdhaXQgZm9yIHRoZSB1cGRhdGUgaGVyZSwgbmV4dCB2YmxhbmsKPiA+IC0JwqAqIHdpbGwg anVzdCBnZXQgbW9yZSBEREIgc3BhY2Ugd2l0aCB0aGUgY29ycmVjdCBXTSB2YWx1ZXMuCj4gPiAt CcKgKi8KPiA+IC0JZm9yX2VhY2hfaW50ZWxfY3J0YyhkZXYsIGNydGMpIHsKPiA+IC0JCWlmICgh Y3J0Yy0+YWN0aXZlKQo+ID4gLQkJCWNvbnRpbnVlOwo+ID4gKwlzdHJ1Y3QgZHJtX2RldmljZSAq ZGV2ID0gc3RhdGUtPmRldjsKPiA+ICsJc3RydWN0IGludGVsX2NydGMgKmludGVsX2NydGM7Cj4g PiArCWVudW0gcGlwZSBvdGhlcnA7Cj4gPiDCoAo+ID4gLQkJcGlwZSA9IGNydGMtPnBpcGU7Cj4g PiArCWZvcl9lYWNoX2ludGVsX2NydGMoZGV2LCBpbnRlbF9jcnRjKSB7Cj4gPiArCQlvdGhlcnAg PSBpbnRlbF9jcnRjLT5waXBlOwo+ID4gwqAKPiA+IMKgCQkvKgo+ID4gLQkJwqAqIEF0IHRoaXMg cG9pbnQsIG9ubHkgdGhlIHBpcGVzIG1vcmUgc3BhY2UgdGhhbiBiZWZvcmUgYXJlCj4gPiAtCQnC oCogbGVmdCB0byByZS1hbGxvY2F0ZS4KPiA+ICsJCcKgKiBXaGVuIGNoZWNraW5nIGZvciBvdmVy bGFwcywgd2UgZG9uJ3Qgd2FudCB0bzoKPiA+ICsJCcKgKsKgwqAtIENvbXBhcmUgYWdhaW5zdCBv dXJzZWx2ZXMKPiA+ICsJCcKgKsKgwqAtIENvbXBhcmUgYWdhaW5zdCBwaXBlcyB0aGF0IHdpbGwg YmUgZGlzYWJsZWQgaW4gc3RlcCAwCj4gPiArCQnCoCrCoMKgLSBDb21wYXJlIGFnYWluc3QgcGlw ZXMgdGhhdCB3b24ndCBiZSBlbmFibGVkIHVudGlsCj4gPiBzdGVwIDMKPiA+IMKgCQnCoCovCj4g PiAtCQlpZiAocmVhbGxvY2F0ZWRbcGlwZV0pCj4gPiArCQlpZiAob3RoZXJwID09IHBpcGUgfHwg IW5ldy0+cGlwZVtvdGhlcnBdLmVuZCB8fAo+ID4gKwkJwqDCoMKgwqAhb2xkLT5waXBlW290aGVy cF0uZW5kKQo+ID4gwqAJCQljb250aW51ZTsKPiA+IMKgCj4gPiAtCQlza2xfd21fZmx1c2hfcGlw ZShkZXZfcHJpdiwgcGlwZSwgMyk7Cj4gPiArCQlpZiAoKG5ldy0+cGlwZVtwaXBlXS5zdGFydCA+ PSBvbGQtPnBpcGVbb3RoZXJwXS5zdGFydCAmJgo+ID4gKwkJwqDCoMKgwqDCoG5ldy0+cGlwZVtw aXBlXS5zdGFydCA8IG9sZC0+cGlwZVtvdGhlcnBdLmVuZCkgfHwKPiA+ICsJCcKgwqDCoMKgKG9s ZC0+cGlwZVtvdGhlcnBdLnN0YXJ0ID49IG5ldy0+cGlwZVtwaXBlXS5zdGFydCAmJgo+ID4gKwkJ wqDCoMKgwqDCoG9sZC0+cGlwZVtvdGhlcnBdLnN0YXJ0IDwgbmV3LT5waXBlW3BpcGVdLmVuZCkp Cj4gPiArCQkJcmV0dXJuIHRydWU7Cj4gPiDCoAl9Cj4gPiArCj4gPiArCXJldHVybiBmYWxzZTsK PiA+IMKgfQo+ID4gwqAKPiA+IMKgc3RhdGljIGludCBza2xfdXBkYXRlX3BpcGVfd20oc3RydWN0 IGRybV9jcnRjX3N0YXRlICpjc3RhdGUsCj4gPiBAQCAtNDAzOCw4ICszOTI0LDEwIEBAIHNrbF9j b21wdXRlX2RkYihzdHJ1Y3QgZHJtX2F0b21pY19zdGF0ZSAqc3RhdGUpCj4gPiDCoAlzdHJ1Y3Qg ZHJtX2RldmljZSAqZGV2ID0gc3RhdGUtPmRldjsKPiA+IMKgCXN0cnVjdCBkcm1faTkxNV9wcml2 YXRlICpkZXZfcHJpdiA9IHRvX2k5MTUoZGV2KTsKPiA+IMKgCXN0cnVjdCBpbnRlbF9hdG9taWNf c3RhdGUgKmludGVsX3N0YXRlID0KPiA+IHRvX2ludGVsX2F0b21pY19zdGF0ZShzdGF0ZSk7Cj4g PiArCXN0cnVjdCBpbnRlbF9jcnRjX3N0YXRlICpjc3RhdGU7Cj4gPiDCoAlzdHJ1Y3QgaW50ZWxf Y3J0YyAqaW50ZWxfY3J0YzsKPiA+IC0Jc3RydWN0IHNrbF9kZGJfYWxsb2NhdGlvbiAqZGRiID0g JmludGVsX3N0YXRlLT53bV9yZXN1bHRzLmRkYjsKPiA+ICsJc3RydWN0IHNrbF9kZGJfYWxsb2Nh dGlvbiAqb2xkX2RkYiA9ICZkZXZfcHJpdi0+d20uc2tsX2h3LmRkYjsKPiA+ICsJc3RydWN0IHNr bF9kZGJfYWxsb2NhdGlvbiAqbmV3X2RkYiA9ICZpbnRlbF9zdGF0ZS0+d21fcmVzdWx0cy5kZGI7 Cj4gPiDCoAl1aW50MzJfdCByZWFsbG9jX3BpcGVzID0gcGlwZXNfbW9kaWZpZWQoc3RhdGUpOwo+ ID4gwqAJaW50IHJldDsKPiA+IMKgCj4gPiBAQCAtNDA3MSwxMyArMzk1OSwxMSBAQCBza2xfY29t cHV0ZV9kZGIoc3RydWN0IGRybV9hdG9taWNfc3RhdGUgKnN0YXRlKQo+ID4gwqAJfQo+ID4gwqAK PiA+IMKgCWZvcl9lYWNoX2ludGVsX2NydGNfbWFzayhkZXYsIGludGVsX2NydGMsIHJlYWxsb2Nf cGlwZXMpIHsKPiA+IC0JCXN0cnVjdCBpbnRlbF9jcnRjX3N0YXRlICpjc3RhdGU7Cj4gPiAtCj4g PiDCoAkJY3N0YXRlID0gaW50ZWxfYXRvbWljX2dldF9jcnRjX3N0YXRlKHN0YXRlLCBpbnRlbF9j cnRjKTsKPiA+IMKgCQlpZiAoSVNfRVJSKGNzdGF0ZSkpCj4gPiDCoAkJCXJldHVybiBQVFJfRVJS KGNzdGF0ZSk7Cj4gPiDCoAo+ID4gLQkJcmV0ID0gc2tsX2FsbG9jYXRlX3BpcGVfZGRiKGNzdGF0 ZSwgZGRiKTsKPiA+ICsJCXJldCA9IHNrbF9hbGxvY2F0ZV9waXBlX2RkYihjc3RhdGUsIG5ld19k ZGIpOwo+ID4gwqAJCWlmIChyZXQpCj4gPiDCoAkJCXJldHVybiByZXQ7Cj4gPiDCoAo+ID4gQEAg LTQwODYsNiArMzk3Miw3MyBAQCBza2xfY29tcHV0ZV9kZGIoc3RydWN0IGRybV9hdG9taWNfc3Rh dGUgKnN0YXRlKQo+ID4gwqAJCQlyZXR1cm4gcmV0Owo+ID4gwqAJfQo+ID4gwqAKPiA+ICsJLyoK PiA+ICsJwqAqIFdoZW4gc2V0dGluZyB1cCBhIG5ldyBEREIgYWxsb2NhdGlvbiBhcnJhbmdlbWVu dCwgd2UgbmVlZCB0bwo+ID4gKwnCoCogY29ycmVjdGx5IHNlcXVlbmNlIHRoZSB0aW1lcyBhdCB3 aGljaCB0aGUgbmV3IGFsbG9jYXRpb25zIGZvcgo+ID4gdGhlCj4gPiArCcKgKiBwaXBlcyBhcmUg dGFrZW4gaW50byBhY2NvdW50IG9yIHdlJ2xsIGhhdmUgcGlwZXMgZmV0Y2hpbmcgZnJvbQo+ID4g c3BhY2UKPiA+ICsJwqAqIHByZXZpb3VzbHkgYWxsb2NhdGVkIHRvIGFub3RoZXIgcGlwZS4KPiA+ ICsJwqAqCj4gPiArCcKgKiBSb3VnaGx5IHRoZSBmaW5hbCBzZXF1ZW5jZSB3ZSB3YW50IGxvb2tz IGxpa2UgdGhpczoKPiA+ICsJwqAqwqDCoDEuIERpc2FibGUgYW55IHBpcGVzIHdlJ3JlIG5vdCBn b2luZyB0byBiZSB1c2luZyBhbnltb3JlCj4gPiArCcKgKsKgwqAyLiBSZWFsbG9jYXRlIGFsbCBv ZiB0aGUgYWN0aXZlIHBpcGVzIHdob3NlIG5ldyBkZGIgYWxsb2NhdGlvbnMKPiA+ICsJwqAqwqDC oHdvbid0IG92ZXJsYXAgd2l0aCBhbm90aGVyIGFjdGl2ZSBwaXBlJ3MgZGRiIGFsbG9jYXRpb24u Cj4gPiArCcKgKsKgwqAzLiBSZWFsbG9jYXRlIHJlbWFpbmluZyBhY3RpdmUgcGlwZXMsIGlmIGFu eS4KPiA+ICsJwqAqwqDCoDQuIEVuYWJsZSBhbnkgbmV3IHBpcGVzLCBpZiBhbnkuCj4gPiArCcKg Kgo+ID4gKwnCoCogRXhhbXBsZToKPiA+ICsJwqAqIEluaXRpYWxseSBEREIgbG9va3MgbGlrZSB0 aGlzOgo+ID4gKwnCoCrCoMKgwqB8wqDCoMKgQsKgwqDCoMKgfMKgwqDCoEPCoMKgwqDCoHwKPiA+ ICsJwqAqIEFuZCB0aGUgZmluYWwgRERCIHNob3VsZCBsb29rIGxpa2UgdGhpczoKPiA+ICsJwqAq wqDCoMKgfMKgwqBCwqDCoHzCoMKgQ8KgwqB8wqDCoEHCoMKgfAo+ID4gKwnCoCoKPiA+ICsJwqAq IDEuIFdlJ3JlIG5vdCBkaXNhYmxpbmcgYW55IHBpcGVzLCBzbyBkbyBub3RoaW5nIG9uIHRoaXMg c3RlcC4KPiA+ICsJwqAqIDIuIFBpcGUgQidzIG5ldyBhbGxvY2F0aW9uIHdvdWxkbid0IG92ZXJs YXAgd2l0aCBwaXBlIEMsIGhvd2V2ZXIKPiA+ICsJwqAqIHBpcGUgQydzIG5ldyBhbGxvY2F0aW9u IGRvZXMgb3ZlcmxhcCB3aXRoIHBpcGUgQidzIGN1cnJlbnQKPiA+ICsJwqAqIGFsbG9jYXRpb24u IFJlYWxsb2NhdGUgQiBmaXJzdCBzbyB0aGUgRERCIGxvb2tzIGxpa2UgdGhpczoKPiA+ICsJwqAq wqDCoMKgfMKgwqBCwqDCoHx4eHzCoMKgwqBDwqDCoMKgwqB8Cj4gPiArCcKgKiAzLiBOb3cgd2Ug Y2FuIHNhZmVseSByZWFsbG9jYXRlIHBpcGUgQyB0byBpdCdzIG5ldyBsb2NhdGlvbjoKPiA+ICsJ wqAqwqDCoMKgfMKgwqBCwqDCoHzCoMKgQ8KgwqB8eHh4eHh8Cj4gPiArCcKgKiA0LiBFbmFibGUg YW55IHJlbWFpbmluZyBwaXBlcywgaW4gdGhpcyBjYXNlIEEKPiA+ICsJwqAqwqDCoMKgfMKgwqBC wqDCoHzCoMKgQ8KgwqB8wqDCoEHCoMKgfAo+ID4gKwnCoCoKPiA+ICsJwqAqIEFzIHdlbGwsIGJl dHdlZW4gZXZlcnkgcGlwZSByZWFsbG9jYXRpb24gd2UgaGF2ZSB0byB3YWl0IGZvciBhCj4gPiAr CcKgKiB2Ymxhbmsgb24gdGhlIHBpcGUgc28gdGhhdCB3ZSBlbnN1cmUgaXQncyBuZXcgYWxsb2Nh dGlvbiBoYXMKPiA+IHRha2VuCj4gPiArCcKgKiBlZmZlY3QgYnkgdGhlIHRpbWUgd2Ugc3RhcnQg bW92aW5nIHRoZSBuZXh0IHBpcGUuIFRoaXMgY2FuIGJlCj4gPiArCcKgKiBza2lwcGVkIG9uIHRo ZSBsYXN0IHN0ZXAgd2UgbmVlZCB0byBwZXJmb3JtLCB3aGljaCBpcyB3aHkgd2UKPiA+IGtlZXAK PiA+ICsJwqAqIHRyYWNrIG9mIHRoYXQgaW5mb3JtYXRpb24gaGVyZS4gRm9yIGV4YW1wbGUsIGlm IHdlJ3ZlCj4gPiByZWFsbG9jYXRlZAo+ID4gKwnCoCogYWxsIHRoZSBwaXBlcyB0aGF0IG5lZWQg Y2hhbmdpbmcgYnkgdGhlIHRpbWUgd2UgcmVhY2ggc3RlcCAzLCB3ZQo+ID4gY2FuCj4gPiArCcKg KiBmaW5pc2ggd2l0aG91dCB3YWl0aW5nIGZvciB0aGUgcGlwZXMgd2UgY2hhbmdlZCBpbiBzdGVw IDMgdG8KPiA+IHVwZGF0ZS4KPiA+ICsJwqAqLwo+ID4gKwlmb3JfZWFjaF9pbnRlbF9jcnRjX21h c2soZGV2LCBpbnRlbF9jcnRjLCByZWFsbG9jX3BpcGVzKSB7Cj4gPiArCQllbnVtIHBpcGUgcGlw ZSA9IGludGVsX2NydGMtPnBpcGU7Cj4gPiArCQllbnVtIHNrbF9kZGJfc3RlcCBzdGVwOwo+ID4g Kwo+ID4gKwkJY3N0YXRlID0gaW50ZWxfYXRvbWljX2dldF9jcnRjX3N0YXRlKHN0YXRlLCBpbnRl bF9jcnRjKTsKPiA+ICsJCWlmIChJU19FUlIoY3N0YXRlKSkKPiA+ICsJCQlyZXR1cm4gUFRSX0VS Uihjc3RhdGUpOwo+ID4gKwo+ID4gKwkJLyogU3RlcCAxOiBQaXBlcyB3ZSdyZSBkaXNhYmxpbmcg LyBoYXZlbid0IGNoYW5nZWQgKi8KPiA+ICsJCWlmIChza2xfZGRiX2FsbG9jYXRpb25fZXF1YWxz KG9sZF9kZGIsIG5ld19kZGIsIHBpcGUpIHx8Cj4gPiArCQnCoMKgwqDCoG5ld19kZGItPnBpcGVb cGlwZV0uZW5kID09IDApIHsKPiA+ICsJCQlzdGVwID0gU0tMX0REQl9TVEVQX05PTkU7Cj4gPiAr CQkvKiBTdGVwIDItMzogQWN0aXZlIHBpcGVzIHdlJ3JlIHJlYWxsb2NhdGluZyAqLwo+ID4gKwkJ fSBlbHNlIGlmIChvbGRfZGRiLT5waXBlW3BpcGVdLmVuZCAhPSAwKSB7Cj4gPiArCQkJaWYgKHNr bF9kZGJfYWxsb2NhdGlvbl9vdmVybGFwcyhzdGF0ZSwgb2xkX2RkYiwKPiA+IG5ld19kZGIsCj4g PiArCQkJCQkJCXBpcGUpKQo+ID4gKwkJCQlzdGVwID0gU0tMX0REQl9TVEVQX09WRVJMQVA7Cj4g PiArCQkJZWxzZQo+ID4gKwkJCQlzdGVwID0gU0tMX0REQl9TVEVQX05PX09WRVJMQVA7Cj4gPiAr CQkvKiBTdGVwIDQ6IFBpcGVzIHdlJ3JlIGVuYWJsaW5nICovCj4gPiArCQl9IGVsc2Ugewo+ID4g KwkJCXN0ZXAgPSBTS0xfRERCX1NURVBfRklOQUw7Cj4gPiArCQl9Cj4gPiArCj4gPiArCQljc3Rh dGUtPndtLnNrbC5kZGJfcmVhbGxvYyA9IHN0ZXA7Cj4gPiArCj4gPiArCQlpZiAoc3RlcCA+IGlu dGVsX3N0YXRlLT5sYXN0X2RkYl9zdGVwKQo+ID4gKwkJCWludGVsX3N0YXRlLT5sYXN0X2RkYl9z dGVwID0gc3RlcDsKPiA+ICsJfQo+ID4gKwo+ID4gwqAJcmV0dXJuIDA7Cj4gPiDCoH0KPiA+IMKg Cj4gPiBAQCAtNDExMCwxMCArNDA2MywxMyBAQCBza2xfY29weV93bV9mb3JfcGlwZShzdHJ1Y3Qg c2tsX3dtX3ZhbHVlcyAqZHN0LAo+ID4gwqBzdGF0aWMgaW50Cj4gPiDCoHNrbF9jb21wdXRlX3dt KHN0cnVjdCBkcm1fYXRvbWljX3N0YXRlICpzdGF0ZSkKPiA+IMKgewo+ID4gKwlzdHJ1Y3QgZHJt X2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYgPSB0b19pOTE1KHN0YXRlLT5kZXYpOwo+ID4gwqAJc3Ry dWN0IGRybV9jcnRjICpjcnRjOwo+ID4gwqAJc3RydWN0IGRybV9jcnRjX3N0YXRlICpjc3RhdGU7 Cj4gPiDCoAlzdHJ1Y3QgaW50ZWxfYXRvbWljX3N0YXRlICppbnRlbF9zdGF0ZSA9Cj4gPiB0b19p bnRlbF9hdG9taWNfc3RhdGUoc3RhdGUpOwo+ID4gwqAJc3RydWN0IHNrbF93bV92YWx1ZXMgKnJl c3VsdHMgPSAmaW50ZWxfc3RhdGUtPndtX3Jlc3VsdHM7Cj4gPiArCXN0cnVjdCBza2xfZGRiX2Fs bG9jYXRpb24gKm9sZF9kZGIgPSAmZGV2X3ByaXYtPndtLnNrbF9ody5kZGI7Cj4gPiArCXN0cnVj dCBza2xfZGRiX2FsbG9jYXRpb24gKm5ld19kZGIgPSAmcmVzdWx0cy0+ZGRiOwo+ID4gwqAJc3Ry dWN0IHNrbF9waXBlX3dtICpwaXBlX3dtOwo+ID4gwqAJYm9vbCBjaGFuZ2VkID0gZmFsc2U7Cj4g PiDCoAlpbnQgcmV0LCBpOwo+ID4gQEAgLTQxNTIsNyArNDEwOCwxMCBAQCBza2xfY29tcHV0ZV93 bShzdHJ1Y3QgZHJtX2F0b21pY19zdGF0ZSAqc3RhdGUpCj4gPiDCoAkJc3RydWN0IGludGVsX2Ny dGMgKmludGVsX2NydGMgPSB0b19pbnRlbF9jcnRjKGNydGMpOwo+ID4gwqAJCXN0cnVjdCBpbnRl bF9jcnRjX3N0YXRlICppbnRlbF9jc3RhdGUgPQo+ID4gwqAJCQl0b19pbnRlbF9jcnRjX3N0YXRl KGNzdGF0ZSk7Cj4gPiArCQllbnVtIHNrbF9kZGJfc3RlcCBzdGVwOwo+ID4gKwkJZW51bSBwaXBl IHBpcGU7Cj4gPiDCoAo+ID4gKwkJcGlwZSA9IGludGVsX2NydGMtPnBpcGU7Cj4gPiDCoAkJcGlw ZV93bSA9ICZpbnRlbF9jc3RhdGUtPndtLnNrbC5vcHRpbWFsOwo+ID4gwqAJCXJldCA9IHNrbF91 cGRhdGVfcGlwZV93bShjc3RhdGUsICZyZXN1bHRzLT5kZGIsIHBpcGVfd20sCj4gPiDCoAkJCQkJ wqAmY2hhbmdlZCk7Cj4gPiBAQCAtNDE2Nyw3ICs0MTI2LDE4IEBAIHNrbF9jb21wdXRlX3dtKHN0 cnVjdCBkcm1fYXRvbWljX3N0YXRlICpzdGF0ZSkKPiA+IMKgCQkJY29udGludWU7Cj4gPiDCoAo+ ID4gwqAJCWludGVsX2NzdGF0ZS0+dXBkYXRlX3dtX3ByZSA9IHRydWU7Cj4gPiArCQlzdGVwID0g aW50ZWxfY3N0YXRlLT53bS5za2wuZGRiX3JlYWxsb2M7Cj4gPiDCoAkJc2tsX2NvbXB1dGVfd21f cmVzdWx0cyhjcnRjLT5kZXYsIHBpcGVfd20sIHJlc3VsdHMsCj4gPiBpbnRlbF9jcnRjKTsKPiA+ ICsKPiA+ICsJCWlmICghc2tsX2RkYl9lbnRyeV9lcXVhbCgmb2xkX2RkYi0+cGlwZVtwaXBlXSwK PiA+ICsJCQkJCcKgJm5ld19kZGItPnBpcGVbcGlwZV0pKSB7Cj4gPiArCQkJRFJNX0RFQlVHX0tN UygKPiA+ICsJCQnCoMKgwqDCoCJEREIgY2hhbmdlcyBmb3IgW0NSVEM6JWQ6cGlwZSAlY106ICgl M2QgLSAlM2QpCj4gPiAtPiAoJTNkIC0gJTNkKSBvbiBzdGVwICVkXG4iLAo+ID4gKwkJCcKgwqDC oMKgaW50ZWxfY3J0Yy0+YmFzZS5iYXNlLmlkLCBwaXBlX25hbWUocGlwZSksCj4gPiArCQkJwqDC oMKgwqBvbGRfZGRiLT5waXBlW3BpcGVdLnN0YXJ0LCBvbGRfZGRiLQo+ID4gPnBpcGVbcGlwZV0u ZW5kLAo+ID4gKwkJCcKgwqDCoMKgbmV3X2RkYi0+cGlwZVtwaXBlXS5zdGFydCwgbmV3X2RkYi0K PiA+ID5waXBlW3BpcGVdLmVuZCwKPiA+ICsJCQnCoMKgwqDCoHN0ZXApOwo+ID4gKwkJfQo+ID4g wqAJfQo+ID4gwqAKPiA+IMKgCXJldHVybiAwOwo+ID4gQEAgLTQxOTEsOCArNDE2MSwyMCBAQCBz dGF0aWMgdm9pZCBza2xfdXBkYXRlX3dtKHN0cnVjdCBkcm1fY3J0YyAqY3J0YykKPiA+IMKgCj4g PiDCoAltdXRleF9sb2NrKCZkZXZfcHJpdi0+d20ud21fbXV0ZXgpOwo+ID4gwqAKPiA+IC0Jc2ts X3dyaXRlX3dtX3ZhbHVlcyhkZXZfcHJpdiwgcmVzdWx0cyk7Cj4gPiAtCXNrbF9mbHVzaF93bV92 YWx1ZXMoZGV2X3ByaXYsIHJlc3VsdHMpOwo+ID4gKwkvKgo+ID4gKwnCoCogSWYgdGhpcyBwaXBl IGlzbid0IGFjdGl2ZSBhbHJlYWR5LCB3ZSdyZSBnb2luZyB0byBiZSBlbmFibGluZyBpdAo+ID4g KwnCoCogdmVyeSBzb29uLiBTaW5jZSBpdCdzIHNhZmUgdG8gdXBkYXRlIHRoZXNlIHdoaWxlIHRo ZSBwaXBlJ3Mgc2h1dAo+ID4gb2ZmLAo+ID4gKwnCoCoganVzdCBkbyBzbyBoZXJlLiBBbHJlYWR5 IGFjdGl2ZSBwaXBlcyB3aWxsIGhhdmUgdGhlaXIgd2F0ZXJtYXJrcwo+ID4gKwnCoCogdXBkYXRl ZCBvbmNlIHdlIHVwZGF0ZSB0aGVpciBwbGFuZXMuCj4gPiArCcKgKi8KPiA+ICsJaWYgKCFpbnRl bF9jcnRjLT5hY3RpdmUpIHsKPiA+ICsJCWludCBwbGFuZTsKPiA+ICsKPiA+ICsJCWZvciAocGxh bmUgPSAwOyBwbGFuZSA8IGludGVsX251bV9wbGFuZXMoaW50ZWxfY3J0Yyk7Cj4gPiBwbGFuZSsr KQo+ID4gKwkJCXNrbF93cml0ZV9wbGFuZV93bShpbnRlbF9jcnRjLCByZXN1bHRzLCBwbGFuZSk7 Cj4gPiArCj4gPiArCQlza2xfd3JpdGVfY3Vyc29yX3dtKGludGVsX2NydGMsIHJlc3VsdHMpOwo+ ID4gKwl9Cj4gPiDCoAo+ID4gwqAJLyoKPiA+IMKgCcKgKiBTdG9yZSB0aGUgbmV3IGNvbmZpZ3Vy YXRpb24gKGJ1dCBvbmx5IGZvciB0aGUgcGlwZXMgdGhhdCBoYXZlCj4gPiAtLcKgCj4gPiAyLjcu NAo+IApfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRl bC1nZnggbWFpbGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6 Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758478AbcHCVja (ORCPT ); Wed, 3 Aug 2016 17:39:30 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37808 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758388AbcHCVj0 (ORCPT ); Wed, 3 Aug 2016 17:39:26 -0400 Message-ID: <1470260363.5153.34.camel@redhat.com> Subject: Re: [PATCH v6 6/6] drm/i915/skl: Update DDB values atomically with wms/plane attrs From: Lyude Paul To: Ville =?ISO-8859-1?Q?Syrj=E4l=E4?= Cc: Radhakrishna Sripada , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Hans de Goede , dri-devel@lists.freedesktop.org, Daniel Vetter Date: Wed, 03 Aug 2016 17:39:23 -0400 In-Reply-To: <20160803150042.GK4329@intel.com> References: <1470177458-31984-1-git-send-email-cpaul@redhat.com> <1470177458-31984-7-git-send-email-cpaul@redhat.com> <20160803150042.GK4329@intel.com> Organization: Red Hat Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Wed, 03 Aug 2016 21:39:26 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2016-08-03 at 18:00 +0300, Ville Syrjälä wrote: > On Tue, Aug 02, 2016 at 06:37:37PM -0400, Lyude wrote: > > > > Now that we can hook into update_crtcs and control the order in which we > > update CRTCs at each modeset, we can finish the final step of fixing > > Skylake's watermark handling by performing DDB updates at the same time > > as plane updates and watermark updates. > > > > The first major change in this patch is skl_update_crtcs(), which > > handles ensuring that we order each CRTC update in our atomic commits > > properly so that they honor the DDB flush order. > > > > The second major change in this patch is the order in which we flush the > > pipes. While the previous order may have worked, it can't be used in > > this approach since it no longer will do the right thing. For example, > > using the old ddb flush order: > > > > We have pipes A, B, and C enabled, and we're disabling C. Initial ddb > > allocation looks like this: > > > > > > > >   A   |   B   |xxxxxxx| > > > > Since we're performing the ddb updates after performing any CRTC > > disablements in intel_atomic_commit_tail(), the space to the right of > > pipe B is unallocated. > > > > 1. Flush pipes with new allocation contained into old space. None > >    apply, so we skip this > > 2. Flush pipes having their allocation reduced, but overlapping with a > >    previous allocation. None apply, so we also skip this > > 3. Flush pipes that got more space allocated. This applies to A and B, > >    giving us the following update order: A, B > > > > This is wrong, since updating pipe A first will cause it to overlap with > > B and potentially burst into flames. Our new order (see the code > > comments for details) would update the pipes in the proper order: B, A. > > > > As well, we calculate the order for each DDB update during the check > > phase, and reference it later in the commit phase when we hit > > skl_update_crtcs(). > > > > This long overdue patch fixes the rest of the underruns on Skylake. > > > > Changes since v1: > >  - Add skl_ddb_entry_write() for cursor into skl_write_cursor_wm() > > > > Fixes: 0e8fb7ba7ca5 ("drm/i915/skl: Flush the WM configuration") > > Fixes: 8211bd5bdf5e ("drm/i915/skl: Program the DDB allocation") > > Signed-off-by: Lyude > > [omitting CC for stable, since this patch will need to be changed for > > such backports first] > > Cc: Ville Syrjälä > > Cc: Daniel Vetter > > Cc: Radhakrishna Sripada > > Cc: Hans de Goede > > Cc: Matt Roper > > --- > >  drivers/gpu/drm/i915/intel_display.c | 100 ++++++++++-- > >  drivers/gpu/drm/i915/intel_drv.h     |  10 ++ > >  drivers/gpu/drm/i915/intel_pm.c      | 288 ++++++++++++++++-------------- > > ----- > >  3 files changed, 233 insertions(+), 165 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 59cf513..06295f7 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -12897,16 +12897,23 @@ static void verify_wm_state(struct drm_crtc *crtc, > >     hw_entry->start, hw_entry->end); > >   } > >   > > - /* cursor */ > > - hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; > > - sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; > > - > > - if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { > > - DRM_ERROR("mismatch in DDB state pipe %c cursor " > > -   "(expected (%u,%u), found (%u,%u))\n", > > -   pipe_name(pipe), > > -   sw_entry->start, sw_entry->end, > > -   hw_entry->start, hw_entry->end); > > + /* > > +  * cursor > > +  * If the cursor plane isn't active, we may not have updated it's > > ddb > > +  * allocation. In that case since the ddb allocation will be > > updated > > +  * once the plane becomes visible, we can skip this check > > +  */ > > + if (intel_crtc->cursor_addr) { > > + hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; > > + sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; > > + > > + if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { > > + DRM_ERROR("mismatch in DDB state pipe %c cursor " > > +   "(expected (%u,%u), found (%u,%u))\n", > > +   pipe_name(pipe), > > +   sw_entry->start, sw_entry->end, > > +   hw_entry->start, hw_entry->end); > > + } > >   } > >  } > >   > > @@ -13658,6 +13665,72 @@ static void intel_update_crtcs(struct > > drm_atomic_state *state, > >   } > >  } > >   > > +static inline void > > +skl_do_ddb_step(struct drm_atomic_state *state, > > + enum skl_ddb_step step) > > +{ > > + struct intel_atomic_state *intel_state = > > to_intel_atomic_state(state); > > + struct drm_crtc *crtc; > > + struct drm_crtc_state *old_crtc_state; > > + unsigned int crtc_vblank_mask; /* unused */ > > + int i; > > + > > + for_each_crtc_in_state(state, crtc, old_crtc_state, i) { > > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > > + struct intel_crtc_state *cstate = > > + to_intel_crtc_state(crtc->state); > > + bool vblank_wait = false; > > + > > + if (cstate->wm.skl.ddb_realloc != step || !crtc->state- > > >active) > > + continue; > > + > > + /* > > +  * If we're changing the ddb allocation of this pipe to > > make > > +  * room for another pipe, we have to wait for the pipe's > > ddb > > +  * allocations to actually update by waiting for a vblank. > > +  * Otherwise we risk the next pipe updating before this > > pipe > > +  * finishes, resulting in the pipe fetching from ddb space > > for > > +  * the wrong pipe. > > +  * > > +  * However, if we know we don't have any more pipes to move > > +  * around, we can skip this wait and the new ddb allocation > > +  * will take effect at the start of the next vblank. > > +  */ > > + switch (step) { > > + case SKL_DDB_STEP_NO_OVERLAP: > > + case SKL_DDB_STEP_OVERLAP: > > + if (step != intel_state->last_ddb_step) > > + vblank_wait = true; > > + > > + /* drop through */ > > + case SKL_DDB_STEP_FINAL: > > + DRM_DEBUG_KMS( > > +     "Updating [CRTC:%d:pipe %c] for DDB step %d\n", > > +     crtc->base.id, pipe_name(intel_crtc->pipe), > > +     step); > > + > > + case SKL_DDB_STEP_NONE: > > + break; > > + } > > Not sure we really need this step stuff. How about? > > for_each_crtc > if (crtc_needs_disabling) > disable_crtc(); > > do { > progress = false; > wait_vbl_pipes=0; > for_each_crtc() { > if (!active || needs_modeset) > continue; > if (!ddb_changed) > continue; > if (new_ddb_overlaps_with_any_other_pipes_current_ddb) > continue; > commit; > wait_vbl_pipes |= pipe; > progress = true; > } > wait_vbls(wait_vbl_pipes); > } while (progress); > > for_each_crtc > if (crtc_needs_enabling) > enable_crtc(); > commit; > } I'm fine with this, it might make this logic a little easier to read.  > > Or if we're paranoid, we could also have an upper bound on the > loop and assert that we never reach it. > > > Though one thing I don't particularly like about this commit while > changing the ddb approach is that it's going to make the update > appear even less atomic. What I'd rather like to do for the normal > commit path is this: > > for_each_crtc > if (crtc_needs_disabling) > disable_planes > for_each_crtc > if (crtc_needs_disabling) > disable_crtc > for_each_crtc > if (crtc_needs_enabling) > enable_crtc > for_each_crtc > if (active) > commit_planes; > > That way everything would pop in and out as close together as possible. > Hmm. Actually, I wonder... I'm thinking we should be able to enable all > crtcs prior to entering the ddb commit loop, on account of no planes > being enabled on those crtcs until we commit them. And if no planes are > enabled, running the pipe w/o allocated ddb should be fine. So with that > approach, I think we should be able to commit all planes within a few > iterations of the loop, and hence within a few vblanks. I can't see any issues with this, and this would definitely make the code a lot cleaner. I'm alright with going this route if matt doesn't see any issues with it as well. Cheers, Lyude > > > > > + > > + intel_update_crtc(crtc, state, old_crtc_state, > > +   &crtc_vblank_mask); > > + > > + if (vblank_wait) > > + intel_wait_for_vblank(state->dev, intel_crtc- > > >pipe); > > + } > > +} > > + > > +static void skl_update_crtcs(struct drm_atomic_state *state, > > +      unsigned int *crtc_vblank_mask) > > +{ > > + struct intel_atomic_state *intel_state = > > to_intel_atomic_state(state); > > + enum skl_ddb_step step; > > + > > + for (step = 0; step <= intel_state->last_ddb_step; step++) > > + skl_do_ddb_step(state, step); > > +} > > + > >  static void intel_atomic_commit_tail(struct drm_atomic_state *state) > >  { > >   struct drm_device *dev = state->dev; > > @@ -15235,8 +15308,6 @@ void intel_init_display_hooks(struct > > drm_i915_private *dev_priv) > >   dev_priv->display.crtc_disable = i9xx_crtc_disable; > >   } > >   > > - dev_priv->display.update_crtcs = intel_update_crtcs; > > - > >   /* Returns the core display clock speed */ > >   if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) > >   dev_priv->display.get_display_clock_speed = > > @@ -15326,6 +15397,11 @@ void intel_init_display_hooks(struct > > drm_i915_private *dev_priv) > >   skl_modeset_calc_cdclk; > >   } > >   > > + if (dev_priv->info.gen >= 9) > > + dev_priv->display.update_crtcs = skl_update_crtcs; > > + else > > + dev_priv->display.update_crtcs = intel_update_crtcs; > > + > >   switch (INTEL_INFO(dev_priv)->gen) { > >   case 2: > >   dev_priv->display.queue_flip = intel_gen2_queue_flip; > > diff --git a/drivers/gpu/drm/i915/intel_drv.h > > b/drivers/gpu/drm/i915/intel_drv.h > > index 1b444d3..cf5da83 100644 > > --- a/drivers/gpu/drm/i915/intel_drv.h > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > @@ -334,6 +334,7 @@ struct intel_atomic_state { > >   > >   /* Gen9+ only */ > >   struct skl_wm_values wm_results; > > + int last_ddb_step; > >  }; > >   > >  struct intel_plane_state { > > @@ -437,6 +438,13 @@ struct skl_pipe_wm { > >   uint32_t linetime; > >  }; > >   > > +enum skl_ddb_step { > > + SKL_DDB_STEP_NONE = 0, > > + SKL_DDB_STEP_NO_OVERLAP, > > + SKL_DDB_STEP_OVERLAP, > > + SKL_DDB_STEP_FINAL > > +}; > > + > >  struct intel_crtc_wm_state { > >   union { > >   struct { > > @@ -467,6 +475,8 @@ struct intel_crtc_wm_state { > >   /* minimum block allocation */ > >   uint16_t minimum_blocks[I915_MAX_PLANES]; > >   uint16_t minimum_y_blocks[I915_MAX_PLANES]; > > + > > + enum skl_ddb_step ddb_realloc; > >   } skl; > >   }; > >   > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > b/drivers/gpu/drm/i915/intel_pm.c > > index 6f5beb3..636c90a 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3816,6 +3816,11 @@ void skl_write_plane_wm(struct intel_crtc > > *intel_crtc, > >      wm->plane[pipe][plane][level]); > >   } > >   I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm- > > >plane_trans[pipe][plane]); > > + > > + skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane), > > +     &wm->ddb.plane[pipe][plane]); > > + skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane), > > +     &wm->ddb.y_plane[pipe][plane]); > >  } > >   > >  void skl_write_cursor_wm(struct intel_crtc *intel_crtc, > > @@ -3832,170 +3837,51 @@ void skl_write_cursor_wm(struct intel_crtc > > *intel_crtc, > >      wm->plane[pipe][PLANE_CURSOR][level]); > >   } > >   I915_WRITE(CUR_WM_TRANS(pipe), wm- > > >plane_trans[pipe][PLANE_CURSOR]); > > -} > > - > > -static void skl_write_wm_values(struct drm_i915_private *dev_priv, > > - const struct skl_wm_values *new) > > -{ > > - struct drm_device *dev = &dev_priv->drm; > > - struct intel_crtc *crtc; > > - > > - for_each_intel_crtc(dev, crtc) { > > - int i; > > - enum pipe pipe = crtc->pipe; > > - > > - if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0) > > - continue; > > - if (!crtc->active) > > - continue; > >   > > - for (i = 0; i < intel_num_planes(crtc); i++) { > > - skl_ddb_entry_write(dev_priv, > > -     PLANE_BUF_CFG(pipe, i), > > -     &new->ddb.plane[pipe][i]); > > - skl_ddb_entry_write(dev_priv, > > -     PLANE_NV12_BUF_CFG(pipe, i), > > -     &new->ddb.y_plane[pipe][i]); > > - } > > - > > - skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), > > -     &new->ddb.plane[pipe][PLANE_CURSOR]); > > - } > > + skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), > > +     &wm->ddb.plane[pipe][PLANE_CURSOR]); > >  } > >   > > -/* > > - * When setting up a new DDB allocation arrangement, we need to correctly > > - * sequence the times at which the new allocations for the pipes are taken > > into > > - * account or we'll have pipes fetching from space previously allocated to > > - * another pipe. > > - * > > - * Roughly the sequence looks like: > > - *  1. re-allocate the pipe(s) with the allocation being reduced and not > > - *     overlapping with a previous light-up pipe (another way to put it is: > > - *     pipes with their new allocation strickly included into their old > > ones). > > - *  2. re-allocate the other pipes that get their allocation reduced > > - *  3. allocate the pipes having their allocation increased > > - * > > - * Steps 1. and 2. are here to take care of the following case: > > - * - Initially DDB looks like this: > > - *     |   B    |   C    | > > - * - enable pipe A. > > - * - pipe B has a reduced DDB allocation that overlaps with the old pipe C > > - *   allocation > > - *     |  A  |  B  |  C  | > > - * > > - * We need to sequence the re-allocation: C, B, A (and not B, C, A). > > - */ > > - > > -static void > > -skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int > > pass) > > +static bool > > +skl_ddb_allocation_equals(const struct skl_ddb_allocation *old, > > +   const struct skl_ddb_allocation *new, > > +   enum pipe pipe) > >  { > > - int plane; > > - > > - DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); > > - > > - for_each_plane(dev_priv, pipe, plane) { > > - I915_WRITE(PLANE_SURF(pipe, plane), > > -    I915_READ(PLANE_SURF(pipe, plane))); > > - } > > - I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); > > + return new->pipe[pipe].start == old->pipe[pipe].start && > > +        new->pipe[pipe].end == old->pipe[pipe].end; > >  } > >   > >  static bool > > -skl_ddb_allocation_included(const struct skl_ddb_allocation *old, > > +skl_ddb_allocation_overlaps(struct drm_atomic_state *state, > > +     const struct skl_ddb_allocation *old, > >       const struct skl_ddb_allocation *new, > >       enum pipe pipe) > >  { > > - uint16_t old_size, new_size; > > - > > - old_size = skl_ddb_entry_size(&old->pipe[pipe]); > > - new_size = skl_ddb_entry_size(&new->pipe[pipe]); > > - > > - return old_size != new_size && > > -        new->pipe[pipe].start >= old->pipe[pipe].start && > > -        new->pipe[pipe].end <= old->pipe[pipe].end; > > -} > > - > > -static void skl_flush_wm_values(struct drm_i915_private *dev_priv, > > - struct skl_wm_values *new_values) > > -{ > > - struct drm_device *dev = &dev_priv->drm; > > - struct skl_ddb_allocation *cur_ddb, *new_ddb; > > - bool reallocated[I915_MAX_PIPES] = {}; > > - struct intel_crtc *crtc; > > - enum pipe pipe; > > - > > - new_ddb = &new_values->ddb; > > - cur_ddb = &dev_priv->wm.skl_hw.ddb; > > - > > - /* > > -  * First pass: flush the pipes with the new allocation contained > > into > > -  * the old space. > > -  * > > -  * We'll wait for the vblank on those pipes to ensure we can safely > > -  * re-allocate the freed space without this pipe fetching from it. > > -  */ > > - for_each_intel_crtc(dev, crtc) { > > - if (!crtc->active) > > - continue; > > - > > - pipe = crtc->pipe; > > - > > - if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) > > - continue; > > - > > - skl_wm_flush_pipe(dev_priv, pipe, 1); > > - intel_wait_for_vblank(dev, pipe); > > - > > - reallocated[pipe] = true; > > - } > > - > > - > > - /* > > -  * Second pass: flush the pipes that are having their allocation > > -  * reduced, but overlapping with a previous allocation. > > -  * > > -  * Here as well we need to wait for the vblank to make sure the > > freed > > -  * space is not used anymore. > > -  */ > > - for_each_intel_crtc(dev, crtc) { > > - if (!crtc->active) > > - continue; > > - > > - pipe = crtc->pipe; > > - > > - if (reallocated[pipe]) > > - continue; > > - > > - if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < > > -     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { > > - skl_wm_flush_pipe(dev_priv, pipe, 2); > > - intel_wait_for_vblank(dev, pipe); > > - reallocated[pipe] = true; > > - } > > - } > > - > > - /* > > -  * Third pass: flush the pipes that got more space allocated. > > -  * > > -  * We don't need to actively wait for the update here, next vblank > > -  * will just get more DDB space with the correct WM values. > > -  */ > > - for_each_intel_crtc(dev, crtc) { > > - if (!crtc->active) > > - continue; > > + struct drm_device *dev = state->dev; > > + struct intel_crtc *intel_crtc; > > + enum pipe otherp; > >   > > - pipe = crtc->pipe; > > + for_each_intel_crtc(dev, intel_crtc) { > > + otherp = intel_crtc->pipe; > >   > >   /* > > -  * At this point, only the pipes more space than before are > > -  * left to re-allocate. > > +  * When checking for overlaps, we don't want to: > > +  *  - Compare against ourselves > > +  *  - Compare against pipes that will be disabled in step 0 > > +  *  - Compare against pipes that won't be enabled until > > step 3 > >    */ > > - if (reallocated[pipe]) > > + if (otherp == pipe || !new->pipe[otherp].end || > > +     !old->pipe[otherp].end) > >   continue; > >   > > - skl_wm_flush_pipe(dev_priv, pipe, 3); > > + if ((new->pipe[pipe].start >= old->pipe[otherp].start && > > +      new->pipe[pipe].start < old->pipe[otherp].end) || > > +     (old->pipe[otherp].start >= new->pipe[pipe].start && > > +      old->pipe[otherp].start < new->pipe[pipe].end)) > > + return true; > >   } > > + > > + return false; > >  } > >   > >  static int skl_update_pipe_wm(struct drm_crtc_state *cstate, > > @@ -4038,8 +3924,10 @@ skl_compute_ddb(struct drm_atomic_state *state) > >   struct drm_device *dev = state->dev; > >   struct drm_i915_private *dev_priv = to_i915(dev); > >   struct intel_atomic_state *intel_state = > > to_intel_atomic_state(state); > > + struct intel_crtc_state *cstate; > >   struct intel_crtc *intel_crtc; > > - struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb; > > + struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb; > > + struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb; > >   uint32_t realloc_pipes = pipes_modified(state); > >   int ret; > >   > > @@ -4071,13 +3959,11 @@ skl_compute_ddb(struct drm_atomic_state *state) > >   } > >   > >   for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) { > > - struct intel_crtc_state *cstate; > > - > >   cstate = intel_atomic_get_crtc_state(state, intel_crtc); > >   if (IS_ERR(cstate)) > >   return PTR_ERR(cstate); > >   > > - ret = skl_allocate_pipe_ddb(cstate, ddb); > > + ret = skl_allocate_pipe_ddb(cstate, new_ddb); > >   if (ret) > >   return ret; > >   > > @@ -4086,6 +3972,73 @@ skl_compute_ddb(struct drm_atomic_state *state) > >   return ret; > >   } > >   > > + /* > > +  * When setting up a new DDB allocation arrangement, we need to > > +  * correctly sequence the times at which the new allocations for > > the > > +  * pipes are taken into account or we'll have pipes fetching from > > space > > +  * previously allocated to another pipe. > > +  * > > +  * Roughly the final sequence we want looks like this: > > +  *  1. Disable any pipes we're not going to be using anymore > > +  *  2. Reallocate all of the active pipes whose new ddb allocations > > +  *  won't overlap with another active pipe's ddb allocation. > > +  *  3. Reallocate remaining active pipes, if any. > > +  *  4. Enable any new pipes, if any. > > +  * > > +  * Example: > > +  * Initially DDB looks like this: > > +  *   |   B    |   C    | > > +  * And the final DDB should look like this: > > +  *   |  B  |  C  |  A  | > > +  * > > +  * 1. We're not disabling any pipes, so do nothing on this step. > > +  * 2. Pipe B's new allocation wouldn't overlap with pipe C, however > > +  * pipe C's new allocation does overlap with pipe B's current > > +  * allocation. Reallocate B first so the DDB looks like this: > > +  *   |  B  |xx|   C    | > > +  * 3. Now we can safely reallocate pipe C to it's new location: > > +  *   |  B  |  C  |xxxxx| > > +  * 4. Enable any remaining pipes, in this case A > > +  *   |  B  |  C  |  A  | > > +  * > > +  * As well, between every pipe reallocation we have to wait for a > > +  * vblank on the pipe so that we ensure it's new allocation has > > taken > > +  * effect by the time we start moving the next pipe. This can be > > +  * skipped on the last step we need to perform, which is why we > > keep > > +  * track of that information here. For example, if we've > > reallocated > > +  * all the pipes that need changing by the time we reach step 3, we > > can > > +  * finish without waiting for the pipes we changed in step 3 to > > update. > > +  */ > > + for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) { > > + enum pipe pipe = intel_crtc->pipe; > > + enum skl_ddb_step step; > > + > > + cstate = intel_atomic_get_crtc_state(state, intel_crtc); > > + if (IS_ERR(cstate)) > > + return PTR_ERR(cstate); > > + > > + /* Step 1: Pipes we're disabling / haven't changed */ > > + if (skl_ddb_allocation_equals(old_ddb, new_ddb, pipe) || > > +     new_ddb->pipe[pipe].end == 0) { > > + step = SKL_DDB_STEP_NONE; > > + /* Step 2-3: Active pipes we're reallocating */ > > + } else if (old_ddb->pipe[pipe].end != 0) { > > + if (skl_ddb_allocation_overlaps(state, old_ddb, > > new_ddb, > > + pipe)) > > + step = SKL_DDB_STEP_OVERLAP; > > + else > > + step = SKL_DDB_STEP_NO_OVERLAP; > > + /* Step 4: Pipes we're enabling */ > > + } else { > > + step = SKL_DDB_STEP_FINAL; > > + } > > + > > + cstate->wm.skl.ddb_realloc = step; > > + > > + if (step > intel_state->last_ddb_step) > > + intel_state->last_ddb_step = step; > > + } > > + > >   return 0; > >  } > >   > > @@ -4110,10 +4063,13 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst, > >  static int > >  skl_compute_wm(struct drm_atomic_state *state) > >  { > > + struct drm_i915_private *dev_priv = to_i915(state->dev); > >   struct drm_crtc *crtc; > >   struct drm_crtc_state *cstate; > >   struct intel_atomic_state *intel_state = > > to_intel_atomic_state(state); > >   struct skl_wm_values *results = &intel_state->wm_results; > > + struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb; > > + struct skl_ddb_allocation *new_ddb = &results->ddb; > >   struct skl_pipe_wm *pipe_wm; > >   bool changed = false; > >   int ret, i; > > @@ -4152,7 +4108,10 @@ skl_compute_wm(struct drm_atomic_state *state) > >   struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > >   struct intel_crtc_state *intel_cstate = > >   to_intel_crtc_state(cstate); > > + enum skl_ddb_step step; > > + enum pipe pipe; > >   > > + pipe = intel_crtc->pipe; > >   pipe_wm = &intel_cstate->wm.skl.optimal; > >   ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm, > >    &changed); > > @@ -4167,7 +4126,18 @@ skl_compute_wm(struct drm_atomic_state *state) > >   continue; > >   > >   intel_cstate->update_wm_pre = true; > > + step = intel_cstate->wm.skl.ddb_realloc; > >   skl_compute_wm_results(crtc->dev, pipe_wm, results, > > intel_crtc); > > + > > + if (!skl_ddb_entry_equal(&old_ddb->pipe[pipe], > > +  &new_ddb->pipe[pipe])) { > > + DRM_DEBUG_KMS( > > +     "DDB changes for [CRTC:%d:pipe %c]: (%3d - %3d) > > -> (%3d - %3d) on step %d\n", > > +     intel_crtc->base.base.id, pipe_name(pipe), > > +     old_ddb->pipe[pipe].start, old_ddb- > > >pipe[pipe].end, > > +     new_ddb->pipe[pipe].start, new_ddb- > > >pipe[pipe].end, > > +     step); > > + } > >   } > >   > >   return 0; > > @@ -4191,8 +4161,20 @@ static void skl_update_wm(struct drm_crtc *crtc) > >   > >   mutex_lock(&dev_priv->wm.wm_mutex); > >   > > - skl_write_wm_values(dev_priv, results); > > - skl_flush_wm_values(dev_priv, results); > > + /* > > +  * If this pipe isn't active already, we're going to be enabling it > > +  * very soon. Since it's safe to update these while the pipe's shut > > off, > > +  * just do so here. Already active pipes will have their watermarks > > +  * updated once we update their planes. > > +  */ > > + if (!intel_crtc->active) { > > + int plane; > > + > > + for (plane = 0; plane < intel_num_planes(intel_crtc); > > plane++) > > + skl_write_plane_wm(intel_crtc, results, plane); > > + > > + skl_write_cursor_wm(intel_crtc, results); > > + } > >   > >   /* > >    * Store the new configuration (but only for the pipes that have > > --  > > 2.7.4 >