From mboxrd@z Thu Jan 1 00:00:00 1970 From: YT Shen Subject: [PATCH v6 09/10] drm/mediatek: add support for Mediatek SoC MT2701 Date: Thu, 4 Aug 2016 19:07:23 +0800 Message-ID: <1470308844-20895-10-git-send-email-yt.shen@mediatek.com> References: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org, Philipp Zabel Cc: Mark Rutland , devicetree@vger.kernel.org, Russell King , srv_heupstream@mediatek.com, Pawel Moll , Ian Campbell , emil.l.velikov@gmail.com, linux-kernel@vger.kernel.org, Mao Huang , Rob Herring , linux-mediatek@lists.infradead.org, Kumar Gala , Matthias Brugger , yingjoe.chen@mediatek.com, Sascha Hauer , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org VGhpcyBwYXRjaCBhZGQgc3VwcG9ydCBmb3IgdGhlIE1lZGlhdGVrIE1UMjcwMSBESVNQIHN1YnN5 c3RlbS4KVGhlcmUgaXMgb25seSBvbmUgT1ZMIGVuZ2luZSBpbiBNVDI3MDEuCgpTaWduZWQtb2Zm LWJ5OiBZVCBTaGVuIDx5dC5zaGVuQG1lZGlhdGVrLmNvbT4KLS0tCiBkcml2ZXJzL2dwdS9kcm0v bWVkaWF0ZWsvbXRrX2Rpc3Bfb3ZsLmMgICAgIHwgICAgNiArKysrKysKIGRyaXZlcnMvZ3B1L2Ry bS9tZWRpYXRlay9tdGtfZGlzcF9yZG1hLmMgICAgfCAgICA2ICsrKysrKwogZHJpdmVycy9ncHUv ZHJtL21lZGlhdGVrL210a19kcm1fZGRwLmMgICAgICB8ICAgMTcgKysrKysrKysrKysrKysrCiBk cml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jIHwgICAgNyArKysrKysK IGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmggfCAgICAxICsKIGRy aXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2Rydi5jICAgICAgfCAgIDI5ICsrKysrKysr KysrKysrKysrKysrKysrKysKIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHNpLmMgICAg ICAgICAgfCAgICAxICsKIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfbWlwaV90eC5jICAg ICAgfCAgIDMxICsrKysrKysrKysrKysrKysrKysrKysrKysrLQogOCBmaWxlcyBjaGFuZ2VkLCA5 NyBpbnNlcnRpb25zKCspLCAxIGRlbGV0aW9uKC0pCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUv ZHJtL21lZGlhdGVrL210a19kaXNwX292bC5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210 a19kaXNwX292bC5jCmluZGV4IGViNWMwNWUuLjFkYTBhNzEgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMv Z3B1L2RybS9tZWRpYXRlay9tdGtfZGlzcF9vdmwuYworKysgYi9kcml2ZXJzL2dwdS9kcm0vbWVk aWF0ZWsvbXRrX2Rpc3Bfb3ZsLmMKQEAgLTI4NiwxMSArMjg2LDE3IEBAIHN0YXRpYyBpbnQgbXRr X2Rpc3Bfb3ZsX3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQogCXJldHVybiAw OwogfQogCitzdGF0aWMgY29uc3Qgc3RydWN0IG10a19kZHBfY29tcF9kcml2ZXJfZGF0YSBtdDI3 MDFfb3ZsX2RyaXZlcl9kYXRhID0geworCS5vdmwgPSB7MHgwMDQwLCAxIDw8IDEyLCAwfQorfTsK Kwogc3RhdGljIGNvbnN0IHN0cnVjdCBtdGtfZGRwX2NvbXBfZHJpdmVyX2RhdGEgbXQ4MTczX292 bF9kcml2ZXJfZGF0YSA9IHsKIAkub3ZsID0gezB4MGY0MCwgMCwgMSA8PCAxMn0KIH07CiAKIHN0 YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIG10a19kaXNwX292bF9kcml2ZXJfZHRfbWF0 Y2hbXSA9IHsKKwl7IC5jb21wYXRpYmxlID0gIm1lZGlhdGVrLG10MjcwMS1kaXNwLW92bCIsCisJ ICAuZGF0YSA9ICZtdDI3MDFfb3ZsX2RyaXZlcl9kYXRhfSwKIAl7IC5jb21wYXRpYmxlID0gIm1l ZGlhdGVrLG10ODE3My1kaXNwLW92bCIsCiAJICAuZGF0YSA9ICZtdDgxNzNfb3ZsX2RyaXZlcl9k YXRhfSwKIAl7fSwKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZGlz cF9yZG1hLmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2Rpc3BfcmRtYS5jCmluZGV4 IGZiMGRiNTAuLjUwNmEzNTMgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9t dGtfZGlzcF9yZG1hLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kaXNwX3Jk bWEuYwpAQCAtMjI1LDExICsyMjUsMTcgQEAgc3RhdGljIGludCBtdGtfZGlzcF9yZG1hX3JlbW92 ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQogCXJldHVybiAwOwogfQogCitzdGF0aWMg Y29uc3Qgc3RydWN0IG10a19kZHBfY29tcF9kcml2ZXJfZGF0YSBtdDI3MDFfcmRtYV9kcml2ZXJf ZGF0YSA9IHsKKwkucmRtYV9maWZvX3BzZXVkb19zaXplID0gU1pfNEssCit9OworCiBzdGF0aWMg Y29uc3Qgc3RydWN0IG10a19kZHBfY29tcF9kcml2ZXJfZGF0YSBtdDgxNzNfcmRtYV9kcml2ZXJf ZGF0YSA9IHsKIAkucmRtYV9maWZvX3BzZXVkb19zaXplID0gU1pfOEssCiB9OwogCiBzdGF0aWMg Y29uc3Qgc3RydWN0IG9mX2RldmljZV9pZCBtdGtfZGlzcF9yZG1hX2RyaXZlcl9kdF9tYXRjaFtd ID0geworCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQyNzAxLWRpc3AtcmRtYSIsCisJICAu ZGF0YSA9ICZtdDI3MDFfcmRtYV9kcml2ZXJfZGF0YX0sCiAJeyAuY29tcGF0aWJsZSA9ICJtZWRp YXRlayxtdDgxNzMtZGlzcC1yZG1hIiwKIAkgIC5kYXRhID0gJm10ODE3M19yZG1hX2RyaXZlcl9k YXRhfSwKIAl7fSwKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJt X2RkcC5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwLmMKaW5kZXggYTli MjA5Yy4uODEzMGYzZCAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19k cm1fZGRwLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwLmMKQEAg LTYwLDYgKzYwLDEzIEBACiAjZGVmaW5lIE1UODE3M19NVVRFWF9NT0RfRElTUF9QV00xCQlCSVQo MjQpCiAjZGVmaW5lIE1UODE3M19NVVRFWF9NT0RfRElTUF9PRAkJQklUKDI1KQogCisjZGVmaW5l IE1UMjcwMV9NVVRFWF9NT0RfRElTUF9PVkwJCUJJVCgzKQorI2RlZmluZSBNVDI3MDFfTVVURVhf TU9EX0RJU1BfV0RNQQkJQklUKDYpCisjZGVmaW5lIE1UMjcwMV9NVVRFWF9NT0RfRElTUF9DT0xP UgkJQklUKDcpCisjZGVmaW5lIE1UMjcwMV9NVVRFWF9NT0RfRElTUF9CTFMJCUJJVCg5KQorI2Rl ZmluZSBNVDI3MDFfTVVURVhfTU9EX0RJU1BfUkRNQTAJCUJJVCgxMCkKKyNkZWZpbmUgTVQyNzAx X01VVEVYX01PRF9ESVNQX1JETUExCQlCSVQoMTIpCisKICNkZWZpbmUgTVVURVhfU09GX1NJTkdM RV9NT0RFCQkwCiAjZGVmaW5lIE1VVEVYX1NPRl9EU0kwCQkJMQogI2RlZmluZSBNVVRFWF9TT0Zf RFNJMQkJCTIKQEAgLTkyLDYgKzk5LDE1IEBAIHN0cnVjdCBtdGtfZGRwIHsKIAljb25zdCB1bnNp Z25lZCBpbnQJCSptdXRleF9tb2Q7CiB9OwogCitzdGF0aWMgY29uc3QgdW5zaWduZWQgaW50IG10 MjcwMV9tdXRleF9tb2RbRERQX0NPTVBPTkVOVF9JRF9NQVhdID0geworCVtERFBfQ09NUE9ORU5U X0JMU10gPSBNVDI3MDFfTVVURVhfTU9EX0RJU1BfQkxTLAorCVtERFBfQ09NUE9ORU5UX0NPTE9S MF0gPSBNVDI3MDFfTVVURVhfTU9EX0RJU1BfQ09MT1IsCisJW0REUF9DT01QT05FTlRfT1ZMMF0g PSBNVDI3MDFfTVVURVhfTU9EX0RJU1BfT1ZMLAorCVtERFBfQ09NUE9ORU5UX1JETUEwXSA9IE1U MjcwMV9NVVRFWF9NT0RfRElTUF9SRE1BMCwKKwlbRERQX0NPTVBPTkVOVF9SRE1BMV0gPSBNVDI3 MDFfTVVURVhfTU9EX0RJU1BfUkRNQTEsCisJW0REUF9DT01QT05FTlRfV0RNQTBdID0gTVQyNzAx X01VVEVYX01PRF9ESVNQX1dETUEsCit9OworCiBzdGF0aWMgY29uc3QgdW5zaWduZWQgaW50IG10 ODE3M19tdXRleF9tb2RbRERQX0NPTVBPTkVOVF9JRF9NQVhdID0gewogCVtERFBfQ09NUE9ORU5U X0FBTF0gPSBNVDgxNzNfTVVURVhfTU9EX0RJU1BfQUFMLAogCVtERFBfQ09NUE9ORU5UX0NPTE9S MF0gPSBNVDgxNzNfTVVURVhfTU9EX0RJU1BfQ09MT1IwLApAQCAtMzkwLDYgKzQwNiw3IEBAIHN0 YXRpYyBpbnQgbXRrX2RkcF9yZW1vdmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKIH0K IAogc3RhdGljIGNvbnN0IHN0cnVjdCBvZl9kZXZpY2VfaWQgZGRwX2RyaXZlcl9kdF9tYXRjaFtd ID0geworCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQyNzAxLWRpc3AtbXV0ZXgiLCAuZGF0 YSA9IG10MjcwMV9tdXRleF9tb2R9LAogCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTcz LWRpc3AtbXV0ZXgiLCAuZGF0YSA9IG10ODE3M19tdXRleF9tb2R9LAogCXt9LAogfTsKZGlmZiAt LWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmMgYi9kcml2 ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jCmluZGV4IDRiNGU0NDkuLjQ2 NTgxOWIgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9j b21wLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwX2NvbXAuYwpA QCAtMTEyLDYgKzExMiw3IEBAIHN0cnVjdCBtdGtfZGRwX2NvbXBfbWF0Y2ggewogCiBzdGF0aWMg Y29uc3Qgc3RydWN0IG10a19kZHBfY29tcF9tYXRjaCBtdGtfZGRwX21hdGNoZXNbRERQX0NPTVBP TkVOVF9JRF9NQVhdID0gewogCVtERFBfQ09NUE9ORU5UX0FBTF0JPSB7IE1US19ESVNQX0FBTCwJ MCwgTlVMTCB9LAorCVtERFBfQ09NUE9ORU5UX0JMU10JPSB7IE1US19ESVNQX1BXTSwJMCwgTlVM TCB9LAogCVtERFBfQ09NUE9ORU5UX0NPTE9SMF0JPSB7IE1US19ESVNQX0NPTE9SLAkwLCAmZGRw X2NvbG9yIH0sCiAJW0REUF9DT01QT05FTlRfQ09MT1IxXQk9IHsgTVRLX0RJU1BfQ09MT1IsCTEs ICZkZHBfY29sb3IgfSwKIAlbRERQX0NPTVBPTkVOVF9EUEkwXQk9IHsgTVRLX0RQSSwJCTAsIE5V TEwgfSwKQEAgLTEzMCwxMSArMTMxLDE3IEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3QgbXRrX2RkcF9j b21wX21hdGNoIG10a19kZHBfbWF0Y2hlc1tERFBfQ09NUE9ORU5UX0lEX01BWF0gPSB7CiAJW0RE UF9DT01QT05FTlRfV0RNQTFdCT0geyBNVEtfRElTUF9XRE1BLAkxLCBOVUxMIH0sCiB9OwogCitz dGF0aWMgY29uc3Qgc3RydWN0IG10a19kZHBfY29tcF9kcml2ZXJfZGF0YSBtdDI3MDFfY29sb3Jf ZHJpdmVyX2RhdGEgPSB7CisJLmNvbG9yX29mZnNldCA9IDB4MGYwMCwKK307CisKIHN0YXRpYyBj b25zdCBzdHJ1Y3QgbXRrX2RkcF9jb21wX2RyaXZlcl9kYXRhIG10ODE3M19jb2xvcl9kcml2ZXJf ZGF0YSA9IHsKIAkuY29sb3Jfb2Zmc2V0ID0gMHgwYzAwLAogfTsKIAogc3RhdGljIGNvbnN0IHN0 cnVjdCBvZl9kZXZpY2VfaWQgbXRrX2Rpc3BfY29sb3JfZHJpdmVyX2R0X21hdGNoW10gPSB7CisJ eyAuY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDI3MDEtZGlzcC1jb2xvciIsCisJICAuZGF0YSA9 ICZtdDI3MDFfY29sb3JfZHJpdmVyX2RhdGF9LAogCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWss bXQ4MTczLWRpc3AtY29sb3IiLAogCSAgLmRhdGEgPSAmbXQ4MTczX2NvbG9yX2RyaXZlcl9kYXRh fSwKIAl7fSwKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2Rk cF9jb21wLmggYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5oCmlu ZGV4IDUzMDY1YzcuLjA4NTBhYTQgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRl ay9tdGtfZHJtX2RkcF9jb21wLmgKKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19k cm1fZGRwX2NvbXAuaApAQCAtNDAsNiArNDAsNyBAQCBlbnVtIG10a19kZHBfY29tcF90eXBlIHsK IAogZW51bSBtdGtfZGRwX2NvbXBfaWQgewogCUREUF9DT01QT05FTlRfQUFMLAorCUREUF9DT01Q T05FTlRfQkxTLAogCUREUF9DT01QT05FTlRfQ09MT1IwLAogCUREUF9DT01QT05FTlRfQ09MT1Ix LAogCUREUF9DT01QT05FTlRfRFBJMCwKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRp YXRlay9tdGtfZHJtX2Rydi5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZHJ2 LmMKaW5kZXggODBiNGY1NC4uMjUwM2YwNCAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL21l ZGlhdGVrL210a19kcm1fZHJ2LmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19k cm1fZHJ2LmMKQEAgLTEwOSw2ICsxMDksMTkgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBkcm1fbW9k ZV9jb25maWdfZnVuY3MgbXRrX2RybV9tb2RlX2NvbmZpZ19mdW5jcyA9IHsKIAkuYXRvbWljX2Nv bW1pdCA9IG10a19hdG9taWNfY29tbWl0LAogfTsKIAorc3RhdGljIGNvbnN0IGVudW0gbXRrX2Rk cF9jb21wX2lkIG10MjcwMV9tdGtfZGRwX21haW5bXSA9IHsKKwlERFBfQ09NUE9ORU5UX09WTDAs CisJRERQX0NPTVBPTkVOVF9SRE1BMCwKKwlERFBfQ09NUE9ORU5UX0NPTE9SMCwKKwlERFBfQ09N UE9ORU5UX0JMUywKKwlERFBfQ09NUE9ORU5UX0RTSTAsCit9OworCitzdGF0aWMgY29uc3QgZW51 bSBtdGtfZGRwX2NvbXBfaWQgbXQyNzAxX210a19kZHBfZXh0W10gPSB7CisJRERQX0NPTVBPTkVO VF9SRE1BMSwKKwlERFBfQ09NUE9ORU5UX0RQSTAsCit9OworCiBzdGF0aWMgY29uc3QgZW51bSBt dGtfZGRwX2NvbXBfaWQgbXQ4MTczX210a19kZHBfbWFpbltdID0gewogCUREUF9DT01QT05FTlRf T1ZMMCwKIAlERFBfQ09NUE9ORU5UX0NPTE9SMCwKQEAgLTEyOCw2ICsxNDEsMTQgQEAgc3RhdGlj IGNvbnN0IGVudW0gbXRrX2RkcF9jb21wX2lkIG10ODE3M19tdGtfZGRwX2V4dFtdID0gewogCURE UF9DT01QT05FTlRfRFBJMCwKIH07CiAKK3N0YXRpYyBjb25zdCBzdHJ1Y3QgbXRrX21tc3lzX2Ry aXZlcl9kYXRhIG10MjcwMV9tbXN5c19kcml2ZXJfZGF0YSA9IHsKKwkubWFpbl9wYXRoID0gbXQy NzAxX210a19kZHBfbWFpbiwKKwkubWFpbl9sZW4gPSBBUlJBWV9TSVpFKG10MjcwMV9tdGtfZGRw X21haW4pLAorCS5leHRfcGF0aCA9IG10MjcwMV9tdGtfZGRwX2V4dCwKKwkuZXh0X2xlbiA9IEFS UkFZX1NJWkUobXQyNzAxX210a19kZHBfZXh0KSwKKwkuc2hhZG93X3JlZ2lzdGVyID0gdHJ1ZSwK K307CisKIHN0YXRpYyBjb25zdCBzdHJ1Y3QgbXRrX21tc3lzX2RyaXZlcl9kYXRhIG10ODE3M19t bXN5c19kcml2ZXJfZGF0YSA9IHsKIAkubWFpbl9wYXRoID0gbXQ4MTczX210a19kZHBfbWFpbiwK IAkubWFpbl9sZW4gPSBBUlJBWV9TSVpFKG10ODE3M19tdGtfZGRwX21haW4pLApAQCAtMzMxLDE2 ICszNTIsMjIgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBjb21wb25lbnRfbWFzdGVyX29wcyBtdGtf ZHJtX29wcyA9IHsKIH07CiAKIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIG10a19k ZHBfY29tcF9kdF9pZHNbXSA9IHsKKwl7IC5jb21wYXRpYmxlID0gIm1lZGlhdGVrLG10MjcwMS1k aXNwLW92bCIsICAgLmRhdGEgPSAodm9pZCAqKU1US19ESVNQX09WTCB9LAogCXsgLmNvbXBhdGli bGUgPSAibWVkaWF0ZWssbXQ4MTczLWRpc3Atb3ZsIiwgICAuZGF0YSA9ICh2b2lkICopTVRLX0RJ U1BfT1ZMIH0sCisJeyAuY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDI3MDEtZGlzcC1yZG1hIiwg IC5kYXRhID0gKHZvaWQgKilNVEtfRElTUF9SRE1BIH0sCiAJeyAuY29tcGF0aWJsZSA9ICJtZWRp YXRlayxtdDgxNzMtZGlzcC1yZG1hIiwgIC5kYXRhID0gKHZvaWQgKilNVEtfRElTUF9SRE1BIH0s CiAJeyAuY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDgxNzMtZGlzcC13ZG1hIiwgIC5kYXRhID0g KHZvaWQgKilNVEtfRElTUF9XRE1BIH0sCisJeyAuY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDI3 MDEtZGlzcC1jb2xvciIsIC5kYXRhID0gKHZvaWQgKilNVEtfRElTUF9DT0xPUiB9LAogCXsgLmNv bXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTczLWRpc3AtY29sb3IiLCAuZGF0YSA9ICh2b2lkICop TVRLX0RJU1BfQ09MT1IgfSwKIAl7IC5jb21wYXRpYmxlID0gIm1lZGlhdGVrLG10ODE3My1kaXNw LWFhbCIsICAgLmRhdGEgPSAodm9pZCAqKU1US19ESVNQX0FBTH0sCiAJeyAuY29tcGF0aWJsZSA9 ICJtZWRpYXRlayxtdDgxNzMtZGlzcC1nYW1tYSIsIC5kYXRhID0gKHZvaWQgKilNVEtfRElTUF9H QU1NQSwgfSwKIAl7IC5jb21wYXRpYmxlID0gIm1lZGlhdGVrLG10ODE3My1kaXNwLXVmb2UiLCAg LmRhdGEgPSAodm9pZCAqKU1US19ESVNQX1VGT0UgfSwKKwl7IC5jb21wYXRpYmxlID0gIm1lZGlh dGVrLG10MjcwMS1kc2kiLAkgICAgICAuZGF0YSA9ICh2b2lkICopTVRLX0RTSSB9LAogCXsgLmNv bXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTczLWRzaSIsICAgICAgICAuZGF0YSA9ICh2b2lkICop TVRLX0RTSSB9LAogCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTczLWRwaSIsICAgICAg ICAuZGF0YSA9ICh2b2lkICopTVRLX0RQSSB9LAorCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWss bXQyNzAxLWRpc3AtbXV0ZXgiLCAuZGF0YSA9ICh2b2lkICopTVRLX0RJU1BfTVVURVggfSwKIAl7 IC5jb21wYXRpYmxlID0gIm1lZGlhdGVrLG10ODE3My1kaXNwLW11dGV4IiwgLmRhdGEgPSAodm9p ZCAqKU1US19ESVNQX01VVEVYIH0sCisJeyAuY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDI3MDEt ZGlzcC1wd20iLCAgIC5kYXRhID0gKHZvaWQgKilNVEtfRElTUF9QV00gfSwKIAl7IC5jb21wYXRp YmxlID0gIm1lZGlhdGVrLG10ODE3My1kaXNwLXB3bSIsICAgLmRhdGEgPSAodm9pZCAqKU1US19E SVNQX1BXTSB9LAogCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTczLWRpc3Atb2QiLCAg ICAuZGF0YSA9ICh2b2lkICopTVRLX0RJU1BfT0QgfSwKIAl7IH0KQEAgLTUxNCw2ICs1NDEsOCBA QCBzdGF0aWMgU0lNUExFX0RFVl9QTV9PUFMobXRrX2RybV9wbV9vcHMsIG10a19kcm1fc3lzX3N1 c3BlbmQsCiAJCQkgbXRrX2RybV9zeXNfcmVzdW1lKTsKIAogc3RhdGljIGNvbnN0IHN0cnVjdCBv Zl9kZXZpY2VfaWQgbXRrX2RybV9vZl9pZHNbXSA9IHsKKwl7IC5jb21wYXRpYmxlID0gIm1lZGlh dGVrLG10MjcwMS1tbXN5cyIsCisJICAuZGF0YSA9ICZtdDI3MDFfbW1zeXNfZHJpdmVyX2RhdGF9 LAogCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTczLW1tc3lzIiwKIAkgIC5kYXRhID0g Jm10ODE3M19tbXN5c19kcml2ZXJfZGF0YX0sCiAJeyB9CmRpZmYgLS1naXQgYS9kcml2ZXJzL2dw dS9kcm0vbWVkaWF0ZWsvbXRrX2RzaS5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19k c2kuYwppbmRleCAzMzczMDE5Li44YjhhNjI5IDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0v bWVkaWF0ZWsvbXRrX2RzaS5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHNp LmMKQEAgLTEzMDAsNiArMTMwMCw3IEBAIHN0YXRpYyBpbnQgbXRrX2RzaV9yZW1vdmUoc3RydWN0 IHBsYXRmb3JtX2RldmljZSAqcGRldikKIH0KIAogc3RhdGljIGNvbnN0IHN0cnVjdCBvZl9kZXZp Y2VfaWQgbXRrX2RzaV9vZl9tYXRjaFtdID0geworCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWss bXQyNzAxLWRzaSIgfSwKIAl7IC5jb21wYXRpYmxlID0gIm1lZGlhdGVrLG10ODE3My1kc2kiIH0s CiAJeyB9LAogfTsKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfbWlw aV90eC5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19taXBpX3R4LmMKaW5kZXggMDY2 NmYxNS4uNmMyYWVjMCAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19t aXBpX3R4LmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19taXBpX3R4LmMKQEAg LTE2LDYgKzE2LDcgQEAKICNpbmNsdWRlIDxsaW51eC9kZWxheS5oPgogI2luY2x1ZGUgPGxpbnV4 L2lvLmg+CiAjaW5jbHVkZSA8bGludXgvbW9kdWxlLmg+CisjaW5jbHVkZSA8bGludXgvb2ZfZGV2 aWNlLmg+CiAjaW5jbHVkZSA8bGludXgvcGxhdGZvcm1fZGV2aWNlLmg+CiAjaW5jbHVkZSA8bGlu dXgvcGh5L3BoeS5oPgogCkBAIC04Nyw2ICs4OCw5IEBACiAKICNkZWZpbmUgTUlQSVRYX0RTSV9Q TExfQ09OMgkweDU4CiAKKyNkZWZpbmUgTUlQSVRYX0RTSV9QTExfVE9QCTB4NjQKKyNkZWZpbmUg UkdfRFNJX01QUExMX1BSRVNFUlZFCQkoMHhmZiA8PCA4KQorCiAjZGVmaW5lIE1JUElUWF9EU0lf UExMX1BXUgkweDY4CiAjZGVmaW5lIFJHX0RTSV9NUFBMTF9TRE1fUFdSX09OCQlCSVQoMCkKICNk ZWZpbmUgUkdfRFNJX01QUExMX1NETV9JU09fRU4JCUJJVCgxKQpAQCAtMTIzLDEwICsxMjcsMTYg QEAKICNkZWZpbmUgU1dfTE5UMl9IU1RYX1BSRV9PRQkJQklUKDI0KQogI2RlZmluZSBTV19MTlQy X0hTVFhfT0UJCQlCSVQoMjUpCiAKK3N0cnVjdCBtdGtfbWlwaXR4X2RhdGEgeworCWNvbnN0IHUz MiBkYXRhOworfTsKKwogc3RydWN0IG10a19taXBpX3R4IHsKIAlzdHJ1Y3QgZGV2aWNlICpkZXY7 CiAJdm9pZCBfX2lvbWVtICpyZWdzOwogCXUzMiBkYXRhX3JhdGU7CisJY29uc3Qgc3RydWN0IG10 a19taXBpdHhfZGF0YSAqZHJpdmVyX2RhdGE7CisKIAlzdHJ1Y3QgY2xrX2h3IHBsbF9odzsKIAlz dHJ1Y3QgY2xrICpwbGw7CiB9OwpAQCAtMjQ1LDYgKzI1NSwxMCBAQCBzdGF0aWMgaW50IG10a19t aXBpX3R4X3BsbF9wcmVwYXJlKHN0cnVjdCBjbGtfaHcgKmh3KQogCW10a19taXBpX3R4X2NsZWFy X2JpdHMobWlwaV90eCwgTUlQSVRYX0RTSV9QTExfQ09OMSwKIAkJCSAgICAgICBSR19EU0lfTVBQ TExfU0RNX1NTQ19FTik7CiAKKwltdGtfbWlwaV90eF91cGRhdGVfYml0cyhtaXBpX3R4LCBNSVBJ VFhfRFNJX1BMTF9UT1AsCisJCQkJUkdfRFNJX01QUExMX1BSRVNFUlZFLAorCQkJCW1pcGlfdHgt PmRyaXZlcl9kYXRhLT5kYXRhKTsKKwogCXJldHVybiAwOwogfQogCkBAIC0yNTcsNiArMjcxLDkg QEAgc3RhdGljIHZvaWQgbXRrX21pcGlfdHhfcGxsX3VucHJlcGFyZShzdHJ1Y3QgY2xrX2h3ICpo dykKIAltdGtfbWlwaV90eF9jbGVhcl9iaXRzKG1pcGlfdHgsIE1JUElUWF9EU0lfUExMX0NPTjAs CiAJCQkgICAgICAgUkdfRFNJX01QUExMX1BMTF9FTik7CiAKKwltdGtfbWlwaV90eF91cGRhdGVf Yml0cyhtaXBpX3R4LCBNSVBJVFhfRFNJX1BMTF9UT1AsCisJCQkJUkdfRFNJX01QUExMX1BSRVNF UlZFLCAwKTsKKwogCW10a19taXBpX3R4X3VwZGF0ZV9iaXRzKG1pcGlfdHgsIE1JUElUWF9EU0lf UExMX1BXUiwKIAkJCQlSR19EU0lfTVBQTExfU0RNX0lTT19FTiB8CiAJCQkJUkdfRFNJX01QUExM X1NETV9QV1JfT04sCkBAIC0zOTMsNiArNDEwLDcgQEAgc3RhdGljIGludCBtdGtfbWlwaV90eF9w cm9iZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQogCWlmICghbWlwaV90eCkKIAkJcmV0 dXJuIC1FTk9NRU07CiAKKwltaXBpX3R4LT5kcml2ZXJfZGF0YSA9IG9mX2RldmljZV9nZXRfbWF0 Y2hfZGF0YShkZXYpOwogCW1lbSA9IHBsYXRmb3JtX2dldF9yZXNvdXJjZShwZGV2LCBJT1JFU09V UkNFX01FTSwgMCk7CiAJbWlwaV90eC0+cmVncyA9IGRldm1faW9yZW1hcF9yZXNvdXJjZShkZXYs IG1lbSk7CiAJaWYgKElTX0VSUihtaXBpX3R4LT5yZWdzKSkgewpAQCAtNDUwLDggKzQ2OCwxOSBA QCBzdGF0aWMgaW50IG10a19taXBpX3R4X3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpw ZGV2KQogCXJldHVybiAwOwogfQogCitzdGF0aWMgY29uc3Qgc3RydWN0IG10a19taXBpdHhfZGF0 YSBtdDI3MDFfbWlwaXR4X2RhdGEgPSB7CisJLmRhdGEgPSAoMyA8PCA4KQorfTsKKworc3RhdGlj IGNvbnN0IHN0cnVjdCBtdGtfbWlwaXR4X2RhdGEgbXQ4MTczX21pcGl0eF9kYXRhID0geworCS5k YXRhID0gKDAgPDwgOCkKK307CisKIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIG10 a19taXBpX3R4X21hdGNoW10gPSB7Ci0JeyAuY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDgxNzMt bWlwaS10eCIsIH0sCisJeyAuY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDI3MDEtbWlwaS10eCIs CisJICAuZGF0YSA9ICZtdDI3MDFfbWlwaXR4X2RhdGEgfSwKKwl7IC5jb21wYXRpYmxlID0gIm1l ZGlhdGVrLG10ODE3My1taXBpLXR4IiwKKwkgIC5kYXRhID0gJm10ODE3M19taXBpdHhfZGF0YSB9 LAogCXt9LAogfTsKIAotLSAKMS43LjkuNQoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMu ZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlz dGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: yt.shen@mediatek.com (YT Shen) Date: Thu, 4 Aug 2016 19:07:23 +0800 Subject: [PATCH v6 09/10] drm/mediatek: add support for Mediatek SoC MT2701 In-Reply-To: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> References: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> Message-ID: <1470308844-20895-10-git-send-email-yt.shen@mediatek.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This patch add support for the Mediatek MT2701 DISP subsystem. There is only one OVL engine in MT2701. Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 17 +++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 7 ++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 29 +++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dsi.c | 1 + drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 31 ++++++++++++++++++++++++++- 8 files changed, 97 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index eb5c05e..1da0a71 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -286,11 +286,17 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) return 0; } +static const struct mtk_ddp_comp_driver_data mt2701_ovl_driver_data = { + .ovl = {0x0040, 1 << 12, 0} +}; + static const struct mtk_ddp_comp_driver_data mt8173_ovl_driver_data = { .ovl = {0x0f40, 0, 1 << 12} }; static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-ovl", + .data = &mt2701_ovl_driver_data}, { .compatible = "mediatek,mt8173-disp-ovl", .data = &mt8173_ovl_driver_data}, {}, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index fb0db50..506a353 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -225,11 +225,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) return 0; } +static const struct mtk_ddp_comp_driver_data mt2701_rdma_driver_data = { + .rdma_fifo_pseudo_size = SZ_4K, +}; + static const struct mtk_ddp_comp_driver_data mt8173_rdma_driver_data = { .rdma_fifo_pseudo_size = SZ_8K, }; static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-rdma", + .data = &mt2701_rdma_driver_data}, { .compatible = "mediatek,mt8173-disp-rdma", .data = &mt8173_rdma_driver_data}, {}, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index a9b209c..8130f3d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -60,6 +60,13 @@ #define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) #define MT8173_MUTEX_MOD_DISP_OD BIT(25) +#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) +#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) +#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) +#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) +#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) +#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) + #define MUTEX_SOF_SINGLE_MODE 0 #define MUTEX_SOF_DSI0 1 #define MUTEX_SOF_DSI1 2 @@ -92,6 +99,15 @@ struct mtk_ddp { const unsigned int *mutex_mod; }; +static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, + [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, + [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, + [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, +}; + static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, @@ -390,6 +406,7 @@ static int mtk_ddp_remove(struct platform_device *pdev) } static const struct of_device_id ddp_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, {}, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 4b4e449..465819b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -112,6 +112,7 @@ struct mtk_ddp_comp_match { static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, NULL }, + [DDP_COMPONENT_BLS] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, @@ -130,11 +131,17 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, }; +static const struct mtk_ddp_comp_driver_data mt2701_color_driver_data = { + .color_offset = 0x0f00, +}; + static const struct mtk_ddp_comp_driver_data mt8173_color_driver_data = { .color_offset = 0x0c00, }; static const struct of_device_id mtk_disp_color_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-color", + .data = &mt2701_color_driver_data}, { .compatible = "mediatek,mt8173-disp-color", .data = &mt8173_color_driver_data}, {}, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 53065c7..0850aa4 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -40,6 +40,7 @@ enum mtk_ddp_comp_type { enum mtk_ddp_comp_id { DDP_COMPONENT_AAL, + DDP_COMPONENT_BLS, DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, DDP_COMPONENT_DPI0, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 80b4f54..2503f04 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -109,6 +109,19 @@ static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { .atomic_commit = mtk_atomic_commit, }; +static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_BLS, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI0, +}; + static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, @@ -128,6 +141,14 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { + .main_path = mt2701_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), + .ext_path = mt2701_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), + .shadow_register = true, +}; + static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .main_path = mt8173_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), @@ -331,16 +352,22 @@ static const struct component_master_ops mtk_drm_ops = { }; static const struct of_device_id mtk_ddp_comp_dt_ids[] = { + { .compatible = "mediatek,mt2701-disp-ovl", .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, + { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, + { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, { } @@ -514,6 +541,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, mtk_drm_sys_resume); static const struct of_device_id mtk_drm_of_ids[] = { + { .compatible = "mediatek,mt2701-mmsys", + .data = &mt2701_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, { } diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 3373019..8b8a629 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -1300,6 +1300,7 @@ static int mtk_dsi_remove(struct platform_device *pdev) } static const struct of_device_id mtk_dsi_of_match[] = { + { .compatible = "mediatek,mt2701-dsi" }, { .compatible = "mediatek,mt8173-dsi" }, { }, }; diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index 0666f15..6c2aec0 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -87,6 +88,9 @@ #define MIPITX_DSI_PLL_CON2 0x58 +#define MIPITX_DSI_PLL_TOP 0x64 +#define RG_DSI_MPPLL_PRESERVE (0xff << 8) + #define MIPITX_DSI_PLL_PWR 0x68 #define RG_DSI_MPPLL_SDM_PWR_ON BIT(0) #define RG_DSI_MPPLL_SDM_ISO_EN BIT(1) @@ -123,10 +127,16 @@ #define SW_LNT2_HSTX_PRE_OE BIT(24) #define SW_LNT2_HSTX_OE BIT(25) +struct mtk_mipitx_data { + const u32 data; +}; + struct mtk_mipi_tx { struct device *dev; void __iomem *regs; u32 data_rate; + const struct mtk_mipitx_data *driver_data; + struct clk_hw pll_hw; struct clk *pll; }; @@ -245,6 +255,10 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_SSC_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP, + RG_DSI_MPPLL_PRESERVE, + mipi_tx->driver_data->data); + return 0; } @@ -257,6 +271,9 @@ static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw) mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP, + RG_DSI_MPPLL_PRESERVE, 0); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR, RG_DSI_MPPLL_SDM_ISO_EN | RG_DSI_MPPLL_SDM_PWR_ON, @@ -393,6 +410,7 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev) if (!mipi_tx) return -ENOMEM; + mipi_tx->driver_data = of_device_get_match_data(dev); mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); mipi_tx->regs = devm_ioremap_resource(dev, mem); if (IS_ERR(mipi_tx->regs)) { @@ -450,8 +468,19 @@ static int mtk_mipi_tx_remove(struct platform_device *pdev) return 0; } +static const struct mtk_mipitx_data mt2701_mipitx_data = { + .data = (3 << 8) +}; + +static const struct mtk_mipitx_data mt8173_mipitx_data = { + .data = (0 << 8) +}; + static const struct of_device_id mtk_mipi_tx_match[] = { - { .compatible = "mediatek,mt8173-mipi-tx", }, + { .compatible = "mediatek,mt2701-mipi-tx", + .data = &mt2701_mipitx_data }, + { .compatible = "mediatek,mt8173-mipi-tx", + .data = &mt8173_mipitx_data }, {}, }; -- 1.7.9.5 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758610AbcHDLR4 (ORCPT ); Thu, 4 Aug 2016 07:17:56 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:7115 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1755193AbcHDLRx (ORCPT ); Thu, 4 Aug 2016 07:17:53 -0400 From: YT Shen To: , Philipp Zabel CC: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , David Airlie , Matthias Brugger , YT Shen , CK Hu , Mao Huang , Bibby Hsieh , , , , , , Sascha Hauer , , , Subject: [PATCH v6 09/10] drm/mediatek: add support for Mediatek SoC MT2701 Date: Thu, 4 Aug 2016 19:07:23 +0800 Message-ID: <1470308844-20895-10-git-send-email-yt.shen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> References: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add support for the Mediatek MT2701 DISP subsystem. There is only one OVL engine in MT2701. Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 17 +++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 7 ++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 29 +++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dsi.c | 1 + drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 31 ++++++++++++++++++++++++++- 8 files changed, 97 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index eb5c05e..1da0a71 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -286,11 +286,17 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) return 0; } +static const struct mtk_ddp_comp_driver_data mt2701_ovl_driver_data = { + .ovl = {0x0040, 1 << 12, 0} +}; + static const struct mtk_ddp_comp_driver_data mt8173_ovl_driver_data = { .ovl = {0x0f40, 0, 1 << 12} }; static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-ovl", + .data = &mt2701_ovl_driver_data}, { .compatible = "mediatek,mt8173-disp-ovl", .data = &mt8173_ovl_driver_data}, {}, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index fb0db50..506a353 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -225,11 +225,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) return 0; } +static const struct mtk_ddp_comp_driver_data mt2701_rdma_driver_data = { + .rdma_fifo_pseudo_size = SZ_4K, +}; + static const struct mtk_ddp_comp_driver_data mt8173_rdma_driver_data = { .rdma_fifo_pseudo_size = SZ_8K, }; static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-rdma", + .data = &mt2701_rdma_driver_data}, { .compatible = "mediatek,mt8173-disp-rdma", .data = &mt8173_rdma_driver_data}, {}, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index a9b209c..8130f3d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -60,6 +60,13 @@ #define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) #define MT8173_MUTEX_MOD_DISP_OD BIT(25) +#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) +#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) +#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) +#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) +#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) +#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) + #define MUTEX_SOF_SINGLE_MODE 0 #define MUTEX_SOF_DSI0 1 #define MUTEX_SOF_DSI1 2 @@ -92,6 +99,15 @@ struct mtk_ddp { const unsigned int *mutex_mod; }; +static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, + [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, + [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, + [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, +}; + static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, @@ -390,6 +406,7 @@ static int mtk_ddp_remove(struct platform_device *pdev) } static const struct of_device_id ddp_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, {}, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 4b4e449..465819b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -112,6 +112,7 @@ struct mtk_ddp_comp_match { static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, NULL }, + [DDP_COMPONENT_BLS] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, @@ -130,11 +131,17 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, }; +static const struct mtk_ddp_comp_driver_data mt2701_color_driver_data = { + .color_offset = 0x0f00, +}; + static const struct mtk_ddp_comp_driver_data mt8173_color_driver_data = { .color_offset = 0x0c00, }; static const struct of_device_id mtk_disp_color_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-color", + .data = &mt2701_color_driver_data}, { .compatible = "mediatek,mt8173-disp-color", .data = &mt8173_color_driver_data}, {}, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 53065c7..0850aa4 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -40,6 +40,7 @@ enum mtk_ddp_comp_type { enum mtk_ddp_comp_id { DDP_COMPONENT_AAL, + DDP_COMPONENT_BLS, DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, DDP_COMPONENT_DPI0, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 80b4f54..2503f04 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -109,6 +109,19 @@ static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { .atomic_commit = mtk_atomic_commit, }; +static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_BLS, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI0, +}; + static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, @@ -128,6 +141,14 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { + .main_path = mt2701_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), + .ext_path = mt2701_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), + .shadow_register = true, +}; + static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .main_path = mt8173_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), @@ -331,16 +352,22 @@ static const struct component_master_ops mtk_drm_ops = { }; static const struct of_device_id mtk_ddp_comp_dt_ids[] = { + { .compatible = "mediatek,mt2701-disp-ovl", .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, + { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, + { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, { } @@ -514,6 +541,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, mtk_drm_sys_resume); static const struct of_device_id mtk_drm_of_ids[] = { + { .compatible = "mediatek,mt2701-mmsys", + .data = &mt2701_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, { } diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 3373019..8b8a629 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -1300,6 +1300,7 @@ static int mtk_dsi_remove(struct platform_device *pdev) } static const struct of_device_id mtk_dsi_of_match[] = { + { .compatible = "mediatek,mt2701-dsi" }, { .compatible = "mediatek,mt8173-dsi" }, { }, }; diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index 0666f15..6c2aec0 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -87,6 +88,9 @@ #define MIPITX_DSI_PLL_CON2 0x58 +#define MIPITX_DSI_PLL_TOP 0x64 +#define RG_DSI_MPPLL_PRESERVE (0xff << 8) + #define MIPITX_DSI_PLL_PWR 0x68 #define RG_DSI_MPPLL_SDM_PWR_ON BIT(0) #define RG_DSI_MPPLL_SDM_ISO_EN BIT(1) @@ -123,10 +127,16 @@ #define SW_LNT2_HSTX_PRE_OE BIT(24) #define SW_LNT2_HSTX_OE BIT(25) +struct mtk_mipitx_data { + const u32 data; +}; + struct mtk_mipi_tx { struct device *dev; void __iomem *regs; u32 data_rate; + const struct mtk_mipitx_data *driver_data; + struct clk_hw pll_hw; struct clk *pll; }; @@ -245,6 +255,10 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_SSC_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP, + RG_DSI_MPPLL_PRESERVE, + mipi_tx->driver_data->data); + return 0; } @@ -257,6 +271,9 @@ static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw) mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP, + RG_DSI_MPPLL_PRESERVE, 0); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR, RG_DSI_MPPLL_SDM_ISO_EN | RG_DSI_MPPLL_SDM_PWR_ON, @@ -393,6 +410,7 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev) if (!mipi_tx) return -ENOMEM; + mipi_tx->driver_data = of_device_get_match_data(dev); mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); mipi_tx->regs = devm_ioremap_resource(dev, mem); if (IS_ERR(mipi_tx->regs)) { @@ -450,8 +468,19 @@ static int mtk_mipi_tx_remove(struct platform_device *pdev) return 0; } +static const struct mtk_mipitx_data mt2701_mipitx_data = { + .data = (3 << 8) +}; + +static const struct mtk_mipitx_data mt8173_mipitx_data = { + .data = (0 << 8) +}; + static const struct of_device_id mtk_mipi_tx_match[] = { - { .compatible = "mediatek,mt8173-mipi-tx", }, + { .compatible = "mediatek,mt2701-mipi-tx", + .data = &mt2701_mipitx_data }, + { .compatible = "mediatek,mt8173-mipi-tx", + .data = &mt8173_mipitx_data }, {}, }; -- 1.7.9.5