From mboxrd@z Thu Jan 1 00:00:00 1970 From: YT Shen Subject: [PATCH v6 10/10] arm: dts: mt2701: Add display subsystem related nodes for MT2701 Date: Thu, 4 Aug 2016 19:07:24 +0800 Message-ID: <1470308844-20895-11-git-send-email-yt.shen@mediatek.com> References: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org, Philipp Zabel Cc: Mark Rutland , devicetree@vger.kernel.org, Russell King , srv_heupstream@mediatek.com, Pawel Moll , Ian Campbell , emil.l.velikov@gmail.com, linux-kernel@vger.kernel.org, Mao Huang , Rob Herring , linux-mediatek@lists.infradead.org, Kumar Gala , Matthias Brugger , yingjoe.chen@mediatek.com, Sascha Hauer , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org VGhpcyBwYXRjaCBhZGRzIHRoZSBkZXZpY2Ugbm9kZXMgZm9yIHRoZSBESVNQIGZ1bmN0aW9uIGJs b2NrcyBmb3IgTVQyNzAxCgpTaWduZWQtb2ZmLWJ5OiBZVCBTaGVuIDx5dC5zaGVuQG1lZGlhdGVr LmNvbT4KLS0tCiBhcmNoL2FybS9ib290L2R0cy9tdDI3MDEuZHRzaSB8ICAgODYgKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysKIDEgZmlsZSBjaGFuZ2VkLCA4NiBpbnNl cnRpb25zKCspCgpkaWZmIC0tZ2l0IGEvYXJjaC9hcm0vYm9vdC9kdHMvbXQyNzAxLmR0c2kgYi9h cmNoL2FybS9ib290L2R0cy9tdDI3MDEuZHRzaQppbmRleCBmMzEzNmJkLi44ZjM1YTBkIDEwMDY0 NAotLS0gYS9hcmNoL2FybS9ib290L2R0cy9tdDI3MDEuZHRzaQorKysgYi9hcmNoL2FybS9ib290 L2R0cy9tdDI3MDEuZHRzaQpAQCAtMjQsNiArMjQsMTEgQEAKIAljb21wYXRpYmxlID0gIm1lZGlh dGVrLG10MjcwMSI7CiAJaW50ZXJydXB0LXBhcmVudCA9IDwmc3lzaXJxPjsKIAorCWFsaWFzZXMg eworCQlyZG1hMCA9ICZyZG1hMDsKKwkJcmRtYTEgPSAmcmRtYTE7CisJfTsKKwogCWNwdXMgewog CQkjYWRkcmVzcy1jZWxscyA9IDwxPjsKIAkJI3NpemUtY2VsbHMgPSA8MD47CkBAIC0xNzEsNiAr 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aWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMu ZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: yt.shen@mediatek.com (YT Shen) Date: Thu, 4 Aug 2016 19:07:24 +0800 Subject: [PATCH v6 10/10] arm: dts: mt2701: Add display subsystem related nodes for MT2701 In-Reply-To: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> References: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> Message-ID: <1470308844-20895-11-git-send-email-yt.shen@mediatek.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This patch adds the device nodes for the DISP function blocks for MT2701 Signed-off-by: YT Shen --- arch/arm/boot/dts/mt2701.dtsi | 86 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index f3136bd..8f35a0d 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -24,6 +24,11 @@ compatible = "mediatek,mt2701"; interrupt-parent = <&sysirq>; + aliases { + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -171,6 +176,16 @@ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; }; + mipi_tx0: mipi-dphy at 10010000 { + compatible = "mediatek,mt2701-mipi-tx"; + reg = <0 0x10010000 0 0x90>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + sysirq: interrupt-controller at 10200100 { compatible = "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq"; @@ -255,6 +270,68 @@ status = "disabled"; }; + ovl at 14007000 { + compatible = "mediatek,mt2701-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_OVL>; + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; + mediatek,larb = <&larb0>; + }; + + rdma0: rdma at 14008000 { + compatible = "mediatek,mt2701-disp-rdma"; + reg = <0 0x14008000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_RDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; + mediatek,larb = <&larb0>; + }; + + wdma at 14009000 { + compatible = "mediatek,mt2701-disp-wdma"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_WDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; + mediatek,larb = <&larb0>; + }; + + bls at 1400a000 { + compatible = "mediatek,mt2701-disp-pwm"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_BLS>; + }; + + color at 1400b000 { + compatible = "mediatek,mt2701-disp-color"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + }; + + dsi0: dsi at 1400c000 { + compatible = "mediatek,mt2701-dsi"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIG>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + mediatek,syscon-dsi = <&mmsys 0x138>; + mediatek,ssc-range = <5>; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + + mutex: mutex at 1400e000 { + compatible = "mediatek,mt2701-disp-mutex"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_MUTEX_32K>; + }; + larb0: larb at 14010000 { compatible = "mediatek,mt2701-smi-larb"; reg = <0 0x14010000 0 0x1000>; @@ -266,6 +343,15 @@ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; }; + rdma1: rdma at 14012000 { + compatible = "mediatek,mt2701-disp-rdma"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb0>; + }; + imgsys: syscon at 15000000 { compatible = "mediatek,mt2701-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; -- 1.7.9.5 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758513AbcHDLRy (ORCPT ); Thu, 4 Aug 2016 07:17:54 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:59871 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1754287AbcHDLRx (ORCPT ); Thu, 4 Aug 2016 07:17:53 -0400 From: YT Shen To: , Philipp Zabel CC: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , David Airlie , Matthias Brugger , YT Shen , CK Hu , Mao Huang , Bibby Hsieh , , , , , , Sascha Hauer , , , Subject: [PATCH v6 10/10] arm: dts: mt2701: Add display subsystem related nodes for MT2701 Date: Thu, 4 Aug 2016 19:07:24 +0800 Message-ID: <1470308844-20895-11-git-send-email-yt.shen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> References: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the device nodes for the DISP function blocks for MT2701 Signed-off-by: YT Shen --- arch/arm/boot/dts/mt2701.dtsi | 86 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index f3136bd..8f35a0d 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -24,6 +24,11 @@ compatible = "mediatek,mt2701"; interrupt-parent = <&sysirq>; + aliases { + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -171,6 +176,16 @@ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; }; + mipi_tx0: mipi-dphy@10010000 { + compatible = "mediatek,mt2701-mipi-tx"; + reg = <0 0x10010000 0 0x90>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + sysirq: interrupt-controller@10200100 { compatible = "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq"; @@ -255,6 +270,68 @@ status = "disabled"; }; + ovl@14007000 { + compatible = "mediatek,mt2701-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_OVL>; + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; + mediatek,larb = <&larb0>; + }; + + rdma0: rdma@14008000 { + compatible = "mediatek,mt2701-disp-rdma"; + reg = <0 0x14008000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_RDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; + mediatek,larb = <&larb0>; + }; + + wdma@14009000 { + compatible = "mediatek,mt2701-disp-wdma"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_WDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; + mediatek,larb = <&larb0>; + }; + + bls@1400a000 { + compatible = "mediatek,mt2701-disp-pwm"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_BLS>; + }; + + color@1400b000 { + compatible = "mediatek,mt2701-disp-color"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + }; + + dsi0: dsi@1400c000 { + compatible = "mediatek,mt2701-dsi"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIG>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + mediatek,syscon-dsi = <&mmsys 0x138>; + mediatek,ssc-range = <5>; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + + mutex: mutex@1400e000 { + compatible = "mediatek,mt2701-disp-mutex"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_MUTEX_32K>; + }; + larb0: larb@14010000 { compatible = "mediatek,mt2701-smi-larb"; reg = <0 0x14010000 0 0x1000>; @@ -266,6 +343,15 @@ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; }; + rdma1: rdma@14012000 { + compatible = "mediatek,mt2701-disp-rdma"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb0>; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt2701-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; -- 1.7.9.5