From mboxrd@z Thu Jan 1 00:00:00 1970 From: YT Shen Subject: [PATCH v6 08/10] drm/mediatek: update DSI sub driver flow Date: Thu, 4 Aug 2016 19:07:22 +0800 Message-ID: <1470308844-20895-9-git-send-email-yt.shen@mediatek.com> References: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org, Philipp Zabel Cc: Mark Rutland , Russell King , Mao Huang , yingjoe.chen@mediatek.com, devicetree@vger.kernel.org, Pawel Moll , Ian Campbell , Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , shaoming chen , linux-arm-kernel@lists.infradead.org, srv_heupstream@mediatek.com, emil.l.velikov@gmail.com, linux-kernel@vger.kernel.org, Sascha Hauer , Kumar Gala List-Id: linux-mediatek@lists.infradead.org VGhpcyBwYXRjaCB1cGRhdGUgZW5hYmxlL2Rpc2FibGUgZmxvdyBvZiBEU0kgbW9kdWxlIGFuZCBN SVBJIFRYIG1vZHVsZQoKU2lnbmVkLW9mZi1ieTogc2hhb21pbmcgY2hlbiA8c2hhb21pbmcuY2hl bkBtZWRpYXRlay5jb20+ClNpZ25lZC1vZmYtYnk6IFlUIFNoZW4gPHl0LnNoZW5AbWVkaWF0ZWsu Y29tPgotLS0KIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHNpLmMgICAgIHwgIDEwMyAr KysrKysrKysrKysrKysrKysrKysrKysrKy0tLS0tLQogZHJpdmVycy9ncHUvZHJtL21lZGlhdGVr L210a19taXBpX3R4LmMgfCAgIDMyICsrKysrLS0tLS0KIDIgZmlsZXMgY2hhbmdlZCwgMTAyIGlu c2VydGlvbnMoKyksIDMzIGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2Ry bS9tZWRpYXRlay9tdGtfZHNpLmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RzaS5j CmluZGV4IDQ1NDFmNTkuLjMzNzMwMTkgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZWRp YXRlay9tdGtfZHNpLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kc2kuYwpA QCAtOTUsNiArOTUsOCBAQAogI2RlZmluZSBEU0lfUkFDSwkJMHg4NAogI2RlZmluZSBSQUNLCQkJ CUJJVCgwKQogCisjZGVmaW5lIERTSV9NRU1fQ09OVEkJCTB4OTAKKwogI2RlZmluZSBEU0lfUEhZ X0xDQ09OCQkweDEwNAogI2RlZmluZSBMQ19IU19UWF9FTgkJCUJJVCgwKQogI2RlZmluZSBMQ19V TFBNX0VOCQkJQklUKDEpCkBAIC0xMjcsNiArMTI5LDEwIEBACiAjZGVmaW5lIENMS19IU19QT1NU CQkJKDB4ZmYgPDwgOCkKICNkZWZpbmUgQ0xLX0hTX0VYSVQJCQkoMHhmZiA8PCAxNikKIAorI2Rl ZmluZSBEU0lfVk1fQ01EX0NPTgkJMHgxMzAKKyNkZWZpbmUgVk1fQ01EX0VOCQkJQklUKDApCisj ZGVmaW5lIFRTX1ZGUF9FTgkJCUJJVCg1KQorCiAjZGVmaW5lIERTSV9DTURRMAkJMHgxODAKIAog I2RlZmluZSBOU19UT19DWUNMRShuLCBjKSAgICAoKG4pIC8gKGMpICsgKCgobikgJSAoYykpID8g MSA6IDApKQpAQCAtMjYwLDcgKzI2Niw5IEBAIHN0YXRpYyBpbnQgbXRrX2RzaV9wb3dlcm9uKHN0 cnVjdCBtdGtfZHNpICpkc2kpCiAJICogbWlwaV9yYXRpbyBpcyBtaXBpIGNsayBjb2VmZmljaWVu dCBmb3IgYmFsYW5jZSB0aGUgcGl4ZWwgY2xrIGluIG1pcGkuCiAJICogd2Ugc2V0IG1pcGlfcmF0 aW8gaXMgMS4wNS4KIAkgKi8KLQlkc2ktPmRhdGFfcmF0ZSA9IGRzaS0+dm0ucGl4ZWxjbG9jayAq IDMgKiAyMSAvICgxICogMTAwMCAqIDEwKTsKKwlkc2ktPmRhdGFfcmF0ZSA9IGRzaS0+dm0ucGl4 ZWxjbG9jayAqIDEyICogMjE7CisJZHNpLT5kYXRhX3JhdGUgLz0gKGRzaS0+bGFuZXMgKiAxMDAw ICogMTApOworCWRldl9pbmZvKGRldiwgInNldCBtaXBpdHgncyBkYXRhIHJhdGU6ICVkTUh6XG4i LCBkc2ktPmRhdGFfcmF0ZSk7CiAKIAlyZXQgPSBjbGtfc2V0X3JhdGUoZHNpLT5oc19jbGssIGRz aS0+ZGF0YV9yYXRlICogMTAwMDAwMCk7CiAJaWYgKHJldCA8IDApIHsKQEAgLTI4MiwxMCArMjkw LDYgQEAgc3RhdGljIGludCBtdGtfZHNpX3Bvd2Vyb24oc3RydWN0IG10a19kc2kgKmRzaSkKIAkJ Z290byBlcnJfZGlzYWJsZV9lbmdpbmVfY2xrOwogCX0KIAotCW10a19kc2lfZW5hYmxlKGRzaSk7 Ci0JbXRrX2RzaV9yZXNldF9lbmdpbmUoZHNpKTsKLQltdGtfZHNpX3BoeV90aW1jb25maWcoZHNp KTsKLQogCXJldHVybiAwOwogCiBlcnJfZGlzYWJsZV9lbmdpbmVfY2xrOgpAQCAtMzAwLDcgKzMw NCw3IEBAIGVycl9yZWZjb3VudDoKIHN0YXRpYyB2b2lkIG10a19kc2lfY2xrX3VscF9tb2RlX2Vu dGVyKHN0cnVjdCBtdGtfZHNpICpkc2kpCiB7CiAJbXRrX2RzaV9tYXNrKGRzaSwgRFNJX1BIWV9M Q0NPTiwgTENfSFNfVFhfRU4sIDApOwotCW10a19kc2lfbWFzayhkc2ksIERTSV9QSFlfTENDT04s IExDX1VMUE1fRU4sIDApOworCW10a19kc2lfbWFzayhkc2ksIERTSV9QSFlfTENDT04sIExDX1VM UE1fRU4sIExDX1VMUE1fRU4pOwogfQogCiBzdGF0aWMgdm9pZCBtdGtfZHNpX2Nsa191bHBfbW9k ZV9sZWF2ZShzdHJ1Y3QgbXRrX2RzaSAqZHNpKQpAQCAtMzEzLDcgKzMxNyw3IEBAIHN0YXRpYyB2 b2lkIG10a19kc2lfY2xrX3VscF9tb2RlX2xlYXZlKHN0cnVjdCBtdGtfZHNpICpkc2kpCiBzdGF0 aWMgdm9pZCBtdGtfZHNpX2xhbmUwX3VscF9tb2RlX2VudGVyKHN0cnVjdCBtdGtfZHNpICpkc2kp CiB7CiAJbXRrX2RzaV9tYXNrKGRzaSwgRFNJX1BIWV9MRDBDT04sIExEMF9IU19UWF9FTiwgMCk7 Ci0JbXRrX2RzaV9tYXNrKGRzaSwgRFNJX1BIWV9MRDBDT04sIExEMF9VTFBNX0VOLCAwKTsKKwlt dGtfZHNpX21hc2soZHNpLCBEU0lfUEhZX0xEMENPTiwgTEQwX1VMUE1fRU4sIExEMF9VTFBNX0VO KTsKIH0KIAogc3RhdGljIHZvaWQgbXRrX2RzaV9sYW5lMF91bHBfbW9kZV9sZWF2ZShzdHJ1Y3Qg bXRrX2RzaSAqZHNpKQpAQCAtMzQ5LDExICszNTMsMjEgQEAgc3RhdGljIHZvaWQgbXRrX2RzaV9z ZXRfbW9kZShzdHJ1Y3QgbXRrX2RzaSAqZHNpKQogCQlpZiAoKGRzaS0+bW9kZV9mbGFncyAmIE1J UElfRFNJX01PREVfVklERU9fQlVSU1QpICYmCiAJCSAgICAhKGRzaS0+bW9kZV9mbGFncyAmIE1J UElfRFNJX01PREVfVklERU9fU1lOQ19QVUxTRSkpCiAJCQl2aWRfbW9kZSA9IEJVUlNUX01PREU7 CisJCWVsc2UKKwkJCXZpZF9tb2RlID0gU1lOQ19FVkVOVF9NT0RFOwogCX0KIAogCXdyaXRlbCh2 aWRfbW9kZSwgZHNpLT5yZWdzICsgRFNJX01PREVfQ1RSTCk7CiB9CiAKK3N0YXRpYyB2b2lkIG10 a19kc2lfc2V0X3ZtX2NtZChzdHJ1Y3QgbXRrX2RzaSAqZHNpKQoreworCXdyaXRlbCgweDNjLCBk c2ktPnJlZ3MgKyBEU0lfTUVNX0NPTlRJKTsKKworCW10a19kc2lfbWFzayhkc2ksIERTSV9WTV9D TURfQ09OLCBWTV9DTURfRU4sIFZNX0NNRF9FTik7CisJbXRrX2RzaV9tYXNrKGRzaSwgRFNJX1ZN X0NNRF9DT04sIFRTX1ZGUF9FTiwgVFNfVkZQX0VOKTsKK30KKwogc3RhdGljIHZvaWQgbXRrX2Rz aV9wc19jb250cm9sX3ZhY3Qoc3RydWN0IG10a19kc2kgKmRzaSkKIHsKIAlzdHJ1Y3QgdmlkZW9t b2RlICp2bSA9ICZkc2ktPnZtOwpAQCAtNDEwLDYgKzQyNCw5IEBAIHN0YXRpYyB2b2lkIG10a19k c2lfcnh0eF9jb250cm9sKHN0cnVjdCBtdGtfZHNpICpkc2kpCiAJCWJyZWFrOwogCX0KIAorCXRt cF9yZWcgfD0gKGRzaS0+bW9kZV9mbGFncyAmIE1JUElfRFNJX0NMT0NLX05PTl9DT05USU5VT1VT KSA8PCA2OworCXRtcF9yZWcgfD0gKGRzaS0+bW9kZV9mbGFncyAmIE1JUElfRFNJX01PREVfRU9U X1BBQ0tFVCkgPj4gMzsKKwogCXdyaXRlbCh0bXBfcmVnLCBkc2ktPnJlZ3MgKyBEU0lfVFhSWF9D VFJMKTsKIH0KIApAQCAtNDg4LDYgKzUwNSwxNiBAQCBzdGF0aWMgdm9pZCBtdGtfZHNpX3N0YXJ0 KHN0cnVjdCBtdGtfZHNpICpkc2kpCiAJd3JpdGVsKDEsIGRzaS0+cmVncyArIERTSV9TVEFSVCk7 CiB9CiAKK3N0YXRpYyB2b2lkIG10a19kc2lfc3RvcChzdHJ1Y3QgbXRrX2RzaSAqZHNpKQorewor CXdyaXRlbCgwLCBkc2ktPnJlZ3MgKyBEU0lfU1RBUlQpOworfQorCitzdGF0aWMgdm9pZCBtdGtf ZHNpX3NldF9jbWRfbW9kZShzdHJ1Y3QgbXRrX2RzaSAqZHNpKQoreworCXdyaXRlbChDTURfTU9E RSwgZHNpLT5yZWdzICsgRFNJX01PREVfQ1RSTCk7Cit9CisKIHN0YXRpYyB2b2lkIG10a19kc2lf c2V0X2ludGVycnVwdF9lbmFibGUoc3RydWN0IG10a19kc2kgKmRzaSkKIHsKIAl1MzIgaW50ZW4g PSBEU0lfSU5UX0FMTF9CSVRTOwpAQCAtNTI1LDYgKzU1MiwyNiBAQCBzdGF0aWMgaXJxcmV0dXJu X3QgbXRrX2RzaV9pcnEoaW50IGlycSwgdm9pZCAqZGV2X2lkKQogCXJldHVybiBJUlFfSEFORExF RDsKIH0KIAorc3RhdGljIHZvaWQgbXRrX2RzaV9zd2l0Y2hfdG9fY21kX21vZGUoc3RydWN0IG10 a19kc2kgKmRzaSkKK3sKKwlzMzIgcmV0ID0gMDsKKwl1bnNpZ25lZCBsb25nIHRpbWVvdXQgPSBt c2Vjc190b19qaWZmaWVzKDUwMCk7CisKKwlkc2ktPmlycV9kYXRhICY9IH5WTV9ET05FX0lOVF9G TEFHOworCisJbXRrX2RzaV9zZXRfY21kX21vZGUoZHNpKTsKKworCXJldCA9IHdhaXRfZXZlbnRf aW50ZXJydXB0aWJsZV90aW1lb3V0KF9kc2lfaXJxX3dhaXRfcXVldWUsCisJCQkJCSAgICAgICBk c2ktPmlycV9kYXRhICYgVk1fRE9ORV9JTlRfRkxBRywKKwkJCQkJICAgICAgIHRpbWVvdXQpOwor CWlmIChyZXQgPT0gMCkgeworCQlkZXZfaW5mbyhkc2ktPmRldiwgImRzaSB3YWl0IGVuZ2luZSBp ZGxlIHRpbWVvdXRcbiIpOworCisJCW10a19kc2lfZW5hYmxlKGRzaSk7CisJCW10a19kc2lfcmVz ZXRfZW5naW5lKGRzaSk7CisJfQorfQorCiBzdGF0aWMgdm9pZCBtdGtfZHNpX3Bvd2Vyb2ZmKHN0 cnVjdCBtdGtfZHNpICpkc2kpCiB7CiAJaWYgKFdBUk5fT04oZHNpLT5yZWZjb3VudCA9PSAwKSkK QEAgLTUzMyw2ICs1ODAsMTcgQEAgc3RhdGljIHZvaWQgbXRrX2RzaV9wb3dlcm9mZihzdHJ1Y3Qg bXRrX2RzaSAqZHNpKQogCWlmICgtLWRzaS0+cmVmY291bnQgIT0gMCkKIAkJcmV0dXJuOwogCisJ bXRrX2RzaV9zd2l0Y2hfdG9fY21kX21vZGUoZHNpKTsKKworCWlmIChkc2ktPnBhbmVsKSB7CisJ CWlmIChkcm1fcGFuZWxfdW5wcmVwYXJlKGRzaS0+cGFuZWwpKSB7CisJCQlEUk1fRVJST1IoImZh aWxlZCB0byB1bnByZXBhcmUgdGhlIHBhbmVsXG4iKTsKKwkJCXJldHVybjsKKwkJfQorCX0KKwor CW10a19kc2lfcmVzZXRfZW5naW5lKGRzaSk7CisKIAltdGtfZHNpX2xhbmUwX3VscF9tb2RlX2Vu dGVyKGRzaSk7CiAJbXRrX2RzaV9jbGtfdWxwX21vZGVfZW50ZXIoZHNpKTsKIApAQCAtNTUxLDI5 ICs2MDksMzcgQEAgc3RhdGljIHZvaWQgbXRrX291dHB1dF9kc2lfZW5hYmxlKHN0cnVjdCBtdGtf ZHNpICpkc2kpCiAJaWYgKGRzaS0+ZW5hYmxlZCkKIAkJcmV0dXJuOwogCi0JaWYgKGRzaS0+cGFu ZWwpIHsKLQkJaWYgKGRybV9wYW5lbF9wcmVwYXJlKGRzaS0+cGFuZWwpKSB7Ci0JCQlEUk1fRVJS T1IoImZhaWxlZCB0byBzZXR1cCB0aGUgcGFuZWxcbiIpOwotCQkJcmV0dXJuOwotCQl9Ci0JfQot CiAJcmV0ID0gbXRrX2RzaV9wb3dlcm9uKGRzaSk7CiAJaWYgKHJldCA8IDApIHsKIAkJRFJNX0VS Uk9SKCJmYWlsZWQgdG8gcG93ZXIgb24gZHNpXG4iKTsKIAkJcmV0dXJuOwogCX0KIAorCXVzbGVl cF9yYW5nZSgyMDAwMCwgMjEwMDApOworCiAJbXRrX2RzaV9yeHR4X2NvbnRyb2woZHNpKTsKKwlt dGtfZHNpX3BoeV90aW1jb25maWcoZHNpKTsKKwltdGtfZHNpX3BzX2NvbnRyb2xfdmFjdChkc2kp OworCW10a19kc2lfc2V0X3ZtX2NtZChkc2kpOworCW10a19kc2lfY29uZmlnX3Zkb190aW1pbmco ZHNpKTsKKwltdGtfZHNpX3NldF9pbnRlcnJ1cHRfZW5hYmxlKGRzaSk7CiAKKwltdGtfZHNpX2Vu YWJsZShkc2kpOwogCW10a19kc2lfY2xrX3VscF9tb2RlX2xlYXZlKGRzaSk7CiAJbXRrX2RzaV9s YW5lMF91bHBfbW9kZV9sZWF2ZShkc2kpOwogCW10a19kc2lfY2xrX2hzX21vZGUoZHNpLCAwKTsK LQltdGtfZHNpX3NldF9tb2RlKGRzaSk7CiAKLQltdGtfZHNpX3BzX2NvbnRyb2xfdmFjdChkc2kp OwotCW10a19kc2lfY29uZmlnX3Zkb190aW1pbmcoZHNpKTsKLQltdGtfZHNpX3NldF9pbnRlcnJ1 cHRfZW5hYmxlKGRzaSk7CisJaWYgKGRzaS0+cGFuZWwpIHsKKwkJaWYgKGRybV9wYW5lbF9wcmVw YXJlKGRzaS0+cGFuZWwpKSB7CisJCQlEUk1fRVJST1IoImZhaWxlZCB0byBwcmVwYXJlIHRoZSBw YW5lbFxuIik7CisJCQlyZXR1cm47CisJCX0KKworCQlpZiAoZHJtX3BhbmVsX2VuYWJsZShkc2kt PnBhbmVsKSkgeworCQkJRFJNX0VSUk9SKCJmYWlsZWQgdG8gZW5hYmxlIHRoZSBwYW5lbFxuIik7 CisJCQlyZXR1cm47CisJCX0KKwl9CiAKIAltdGtfZHNpX3NldF9tb2RlKGRzaSk7CiAJbXRrX2Rz aV9jbGtfaHNfbW9kZShkc2ksIDEpOwpAQCAtNTk1LDYgKzY2MSw3IEBAIHN0YXRpYyB2b2lkIG10 a19vdXRwdXRfZHNpX2Rpc2FibGUoc3RydWN0IG10a19kc2kgKmRzaSkKIAkJfQogCX0KIAorCW10 a19kc2lfc3RvcChkc2kpOwogCW10a19kc2lfcG93ZXJvZmYoZHNpKTsKIAogCWRzaS0+ZW5hYmxl ZCA9IGZhbHNlOwpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19taXBp X3R4LmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX21pcGlfdHguYwppbmRleCAxOTQ4 MWM3Li4wNjY2ZjE1IDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX21p cGlfdHguYworKysgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX21pcGlfdHguYwpAQCAt MTY4LDcgKzE2OCw5IEBAIHN0YXRpYyBpbnQgbXRrX21pcGlfdHhfcGxsX3ByZXBhcmUoc3RydWN0 IGNsa19odyAqaHcpCiAKIAlkZXZfZGJnKG1pcGlfdHgtPmRldiwgInByZXBhcmU6ICV1IEh6XG4i LCBtaXBpX3R4LT5kYXRhX3JhdGUpOwogCi0JaWYgKG1pcGlfdHgtPmRhdGFfcmF0ZSA+PSA1MDAw MDAwMDApIHsKKwlpZiAobWlwaV90eC0+ZGF0YV9yYXRlID4gMTI1MDAwMDAwMCkgeworCQlyZXR1 cm4gLUVJTlZBTDsKKwl9IGVsc2UgaWYgKG1pcGlfdHgtPmRhdGFfcmF0ZSA+PSA1MDAwMDAwMDAp IHsKIAkJdHhkaXYgPSAxOwogCQl0eGRpdjAgPSAwOwogCQl0eGRpdjEgPSAwOwpAQCAtMTkyLDYg KzE5NCwxMCBAQCBzdGF0aWMgaW50IG10a19taXBpX3R4X3BsbF9wcmVwYXJlKHN0cnVjdCBjbGtf aHcgKmh3KQogCQlyZXR1cm4gLUVJTlZBTDsKIAl9CiAKKwltdGtfbWlwaV90eF91cGRhdGVfYml0 cyhtaXBpX3R4LCBNSVBJVFhfRFNJX1RPUF9DT04sCisJCQkJUkdfRFNJX0xOVF9JTVBfQ0FMX0NP REUgfCBSR19EU0lfTE5UX0hTX0JJQVNfRU4sCisJCQkJKDggPDwgNCkgfCBSR19EU0lfTE5UX0hT X0JJQVNfRU4pOworCiAJbXRrX21pcGlfdHhfdXBkYXRlX2JpdHMobWlwaV90eCwgTUlQSVRYX0RT SV9CR19DT04sCiAJCQkJUkdfRFNJX1ZPVVRfTVNLIHwKIAkJCQlSR19EU0lfQkdfQ0tFTiB8IFJH X0RTSV9CR19DT1JFX0VOLApAQCAtMjAxLDI0ICsyMDcsMTggQEAgc3RhdGljIGludCBtdGtfbWlw aV90eF9wbGxfcHJlcGFyZShzdHJ1Y3QgY2xrX2h3ICpodykKIAogCXVzbGVlcF9yYW5nZSgzMCwg MTAwKTsKIAotCW10a19taXBpX3R4X3VwZGF0ZV9iaXRzKG1pcGlfdHgsIE1JUElUWF9EU0lfVE9Q X0NPTiwKLQkJCQlSR19EU0lfTE5UX0lNUF9DQUxfQ09ERSB8IFJHX0RTSV9MTlRfSFNfQklBU19F TiwKLQkJCQkoOCA8PCA0KSB8IFJHX0RTSV9MTlRfSFNfQklBU19FTik7Ci0KLQltdGtfbWlwaV90 eF9zZXRfYml0cyhtaXBpX3R4LCBNSVBJVFhfRFNJX0NPTiwKLQkJCSAgICAgUkdfRFNJX0NLR19M RE9PVVRfRU4gfCBSR19EU0lfTERPQ09SRV9FTik7CisJbXRrX21pcGlfdHhfdXBkYXRlX2JpdHMo bWlwaV90eCwgTUlQSVRYX0RTSV9DT04sCisJCQkJUkdfRFNJX0NLR19MRE9PVVRfRU4gfCBSR19E U0lfTERPQ09SRV9FTiwKKwkJCQlSR19EU0lfQ0tHX0xET09VVF9FTiB8IFJHX0RTSV9MRE9DT1JF X0VOKTsKIAogCW10a19taXBpX3R4X3VwZGF0ZV9iaXRzKG1pcGlfdHgsIE1JUElUWF9EU0lfUExM X1BXUiwKIAkJCQlSR19EU0lfTVBQTExfU0RNX1BXUl9PTiB8CiAJCQkJUkdfRFNJX01QUExMX1NE TV9JU09fRU4sCiAJCQkJUkdfRFNJX01QUExMX1NETV9QV1JfT04pOwogCi0JbXRrX21pcGlfdHhf Y2xlYXJfYml0cyhtaXBpX3R4LCBNSVBJVFhfRFNJX1BMTF9DT04wLAotCQkJICAgICAgIFJHX0RT SV9NUFBMTF9QTExfRU4pOwotCiAJbXRrX21pcGlfdHhfdXBkYXRlX2JpdHMobWlwaV90eCwgTUlQ SVRYX0RTSV9QTExfQ09OMCwKLQkJCQlSR19EU0lfTVBQTExfVFhESVYwIHwgUkdfRFNJX01QUExM X1RYRElWMSB8Ci0JCQkJUkdfRFNJX01QUExMX1BSRURJViwKKwkJCQlSR19EU0lfTVBQTExfUFJF RElWIHwgUkdfRFNJX01QUExMX1RYRElWMCB8CisJCQkJUkdfRFNJX01QUExMX1RYRElWMSB8IFJH X0RTSV9NUFBMTF9QT1NESVYsCiAJCQkJKHR4ZGl2MCA8PCAzKSB8ICh0eGRpdjEgPDwgNSkpOwog CiAJLyoKQEAgLTIzMywxMCArMjMzLDEyIEBAIHN0YXRpYyBpbnQgbXRrX21pcGlfdHhfcGxsX3By ZXBhcmUoc3RydWN0IGNsa19odyAqaHcpCiAJCSAgICAgIDI2MDAwMDAwKTsKIAl3cml0ZWwocGN3 LCBtaXBpX3R4LT5yZWdzICsgTUlQSVRYX0RTSV9QTExfQ09OMik7CiAKLQltdGtfbWlwaV90eF9z ZXRfYml0cyhtaXBpX3R4LCBNSVBJVFhfRFNJX1BMTF9DT04xLAotCQkJICAgICBSR19EU0lfTVBQ TExfU0RNX0ZSQV9FTik7CisJbXRrX21pcGlfdHhfdXBkYXRlX2JpdHMobWlwaV90eCwgTUlQSVRY X0RTSV9QTExfQ09OMSwKKwkJCQlSR19EU0lfTVBQTExfU0RNX0ZSQV9FTiwKKwkJCQlSR19EU0lf TVBQTExfU0RNX0ZSQV9FTik7CiAKLQltdGtfbWlwaV90eF9zZXRfYml0cyhtaXBpX3R4LCBNSVBJ VFhfRFNJX1BMTF9DT04wLCBSR19EU0lfTVBQTExfUExMX0VOKTsKKwltdGtfbWlwaV90eF91cGRh dGVfYml0cyhtaXBpX3R4LCBNSVBJVFhfRFNJX1BMTF9DT04wLAorCQkJCVJHX0RTSV9NUFBMTF9Q TExfRU4sIFJHX0RTSV9NUFBMTF9QTExfRU4pOwogCiAJdXNsZWVwX3JhbmdlKDIwLCAxMDApOwog Ci0tIAoxLjcuOS41CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5v cmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2 ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: yt.shen@mediatek.com (YT Shen) Date: Thu, 4 Aug 2016 19:07:22 +0800 Subject: [PATCH v6 08/10] drm/mediatek: update DSI sub driver flow In-Reply-To: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> References: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> Message-ID: <1470308844-20895-9-git-send-email-yt.shen@mediatek.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This patch update enable/disable flow of DSI module and MIPI TX module Signed-off-by: shaoming chen Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_dsi.c | 103 ++++++++++++++++++++++++++------ drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 32 +++++----- 2 files changed, 102 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 4541f59..3373019 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -95,6 +95,8 @@ #define DSI_RACK 0x84 #define RACK BIT(0) +#define DSI_MEM_CONTI 0x90 + #define DSI_PHY_LCCON 0x104 #define LC_HS_TX_EN BIT(0) #define LC_ULPM_EN BIT(1) @@ -127,6 +129,10 @@ #define CLK_HS_POST (0xff << 8) #define CLK_HS_EXIT (0xff << 16) +#define DSI_VM_CMD_CON 0x130 +#define VM_CMD_EN BIT(0) +#define TS_VFP_EN BIT(5) + #define DSI_CMDQ0 0x180 #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0)) @@ -260,7 +266,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) * mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi. * we set mipi_ratio is 1.05. */ - dsi->data_rate = dsi->vm.pixelclock * 3 * 21 / (1 * 1000 * 10); + dsi->data_rate = dsi->vm.pixelclock * 12 * 21; + dsi->data_rate /= (dsi->lanes * 1000 * 10); + dev_info(dev, "set mipitx's data rate: %dMHz\n", dsi->data_rate); ret = clk_set_rate(dsi->hs_clk, dsi->data_rate * 1000000); if (ret < 0) { @@ -282,10 +290,6 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) goto err_disable_engine_clk; } - mtk_dsi_enable(dsi); - mtk_dsi_reset_engine(dsi); - mtk_dsi_phy_timconfig(dsi); - return 0; err_disable_engine_clk: @@ -300,7 +304,7 @@ err_refcount: static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi) { mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); - mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); + mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, LC_ULPM_EN); } static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) @@ -313,7 +317,7 @@ static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi) { mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0); - mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); + mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, LD0_ULPM_EN); } static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi) @@ -349,11 +353,21 @@ static void mtk_dsi_set_mode(struct mtk_dsi *dsi) if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) vid_mode = BURST_MODE; + else + vid_mode = SYNC_EVENT_MODE; } writel(vid_mode, dsi->regs + DSI_MODE_CTRL); } +static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) +{ + writel(0x3c, dsi->regs + DSI_MEM_CONTI); + + mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN); + mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); +} + static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) { struct videomode *vm = &dsi->vm; @@ -410,6 +424,9 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) break; } + tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; + tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); } @@ -488,6 +505,16 @@ static void mtk_dsi_start(struct mtk_dsi *dsi) writel(1, dsi->regs + DSI_START); } +static void mtk_dsi_stop(struct mtk_dsi *dsi) +{ + writel(0, dsi->regs + DSI_START); +} + +static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi) +{ + writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL); +} + static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi) { u32 inten = DSI_INT_ALL_BITS; @@ -525,6 +552,26 @@ static irqreturn_t mtk_dsi_irq(int irq, void *dev_id) return IRQ_HANDLED; } +static void mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi) +{ + s32 ret = 0; + unsigned long timeout = msecs_to_jiffies(500); + + dsi->irq_data &= ~VM_DONE_INT_FLAG; + + mtk_dsi_set_cmd_mode(dsi); + + ret = wait_event_interruptible_timeout(_dsi_irq_wait_queue, + dsi->irq_data & VM_DONE_INT_FLAG, + timeout); + if (ret == 0) { + dev_info(dsi->dev, "dsi wait engine idle timeout\n"); + + mtk_dsi_enable(dsi); + mtk_dsi_reset_engine(dsi); + } +} + static void mtk_dsi_poweroff(struct mtk_dsi *dsi) { if (WARN_ON(dsi->refcount == 0)) @@ -533,6 +580,17 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) if (--dsi->refcount != 0) return; + mtk_dsi_switch_to_cmd_mode(dsi); + + if (dsi->panel) { + if (drm_panel_unprepare(dsi->panel)) { + DRM_ERROR("failed to unprepare the panel\n"); + return; + } + } + + mtk_dsi_reset_engine(dsi); + mtk_dsi_lane0_ulp_mode_enter(dsi); mtk_dsi_clk_ulp_mode_enter(dsi); @@ -551,29 +609,37 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi) if (dsi->enabled) return; - if (dsi->panel) { - if (drm_panel_prepare(dsi->panel)) { - DRM_ERROR("failed to setup the panel\n"); - return; - } - } - ret = mtk_dsi_poweron(dsi); if (ret < 0) { DRM_ERROR("failed to power on dsi\n"); return; } + usleep_range(20000, 21000); + mtk_dsi_rxtx_control(dsi); + mtk_dsi_phy_timconfig(dsi); + mtk_dsi_ps_control_vact(dsi); + mtk_dsi_set_vm_cmd(dsi); + mtk_dsi_config_vdo_timing(dsi); + mtk_dsi_set_interrupt_enable(dsi); + mtk_dsi_enable(dsi); mtk_dsi_clk_ulp_mode_leave(dsi); mtk_dsi_lane0_ulp_mode_leave(dsi); mtk_dsi_clk_hs_mode(dsi, 0); - mtk_dsi_set_mode(dsi); - mtk_dsi_ps_control_vact(dsi); - mtk_dsi_config_vdo_timing(dsi); - mtk_dsi_set_interrupt_enable(dsi); + if (dsi->panel) { + if (drm_panel_prepare(dsi->panel)) { + DRM_ERROR("failed to prepare the panel\n"); + return; + } + + if (drm_panel_enable(dsi->panel)) { + DRM_ERROR("failed to enable the panel\n"); + return; + } + } mtk_dsi_set_mode(dsi); mtk_dsi_clk_hs_mode(dsi, 1); @@ -595,6 +661,7 @@ static void mtk_output_dsi_disable(struct mtk_dsi *dsi) } } + mtk_dsi_stop(dsi); mtk_dsi_poweroff(dsi); dsi->enabled = false; diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index 19481c7..0666f15 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -168,7 +168,9 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate); - if (mipi_tx->data_rate >= 500000000) { + if (mipi_tx->data_rate > 1250000000) { + return -EINVAL; + } else if (mipi_tx->data_rate >= 500000000) { txdiv = 1; txdiv0 = 0; txdiv1 = 0; @@ -192,6 +194,10 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) return -EINVAL; } + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON, + RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN, + (8 << 4) | RG_DSI_LNT_HS_BIAS_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON, RG_DSI_VOUT_MSK | RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN, @@ -201,24 +207,18 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) usleep_range(30, 100); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON, - RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN, - (8 << 4) | RG_DSI_LNT_HS_BIAS_EN); - - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON, - RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_CON, + RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN, + RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR, RG_DSI_MPPLL_SDM_PWR_ON | RG_DSI_MPPLL_SDM_ISO_EN, RG_DSI_MPPLL_SDM_PWR_ON); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, - RG_DSI_MPPLL_PLL_EN); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0, - RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 | - RG_DSI_MPPLL_PREDIV, + RG_DSI_MPPLL_PREDIV | RG_DSI_MPPLL_TXDIV0 | + RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_POSDIV, (txdiv0 << 3) | (txdiv1 << 5)); /* @@ -233,10 +233,12 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) 26000000); writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1, - RG_DSI_MPPLL_SDM_FRA_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON1, + RG_DSI_MPPLL_SDM_FRA_EN, + RG_DSI_MPPLL_SDM_FRA_EN); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0, + RG_DSI_MPPLL_PLL_EN, RG_DSI_MPPLL_PLL_EN); usleep_range(20, 100); -- 1.7.9.5 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758551AbcHDLPs (ORCPT ); Thu, 4 Aug 2016 07:15:48 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:33649 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1754205AbcHDLPp (ORCPT ); Thu, 4 Aug 2016 07:15:45 -0400 From: YT Shen To: , Philipp Zabel CC: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , David Airlie , Matthias Brugger , YT Shen , CK Hu , Mao Huang , Bibby Hsieh , , , , , , Sascha Hauer , , , , shaoming chen Subject: [PATCH v6 08/10] drm/mediatek: update DSI sub driver flow Date: Thu, 4 Aug 2016 19:07:22 +0800 Message-ID: <1470308844-20895-9-git-send-email-yt.shen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> References: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch update enable/disable flow of DSI module and MIPI TX module Signed-off-by: shaoming chen Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_dsi.c | 103 ++++++++++++++++++++++++++------ drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 32 +++++----- 2 files changed, 102 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 4541f59..3373019 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -95,6 +95,8 @@ #define DSI_RACK 0x84 #define RACK BIT(0) +#define DSI_MEM_CONTI 0x90 + #define DSI_PHY_LCCON 0x104 #define LC_HS_TX_EN BIT(0) #define LC_ULPM_EN BIT(1) @@ -127,6 +129,10 @@ #define CLK_HS_POST (0xff << 8) #define CLK_HS_EXIT (0xff << 16) +#define DSI_VM_CMD_CON 0x130 +#define VM_CMD_EN BIT(0) +#define TS_VFP_EN BIT(5) + #define DSI_CMDQ0 0x180 #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0)) @@ -260,7 +266,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) * mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi. * we set mipi_ratio is 1.05. */ - dsi->data_rate = dsi->vm.pixelclock * 3 * 21 / (1 * 1000 * 10); + dsi->data_rate = dsi->vm.pixelclock * 12 * 21; + dsi->data_rate /= (dsi->lanes * 1000 * 10); + dev_info(dev, "set mipitx's data rate: %dMHz\n", dsi->data_rate); ret = clk_set_rate(dsi->hs_clk, dsi->data_rate * 1000000); if (ret < 0) { @@ -282,10 +290,6 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) goto err_disable_engine_clk; } - mtk_dsi_enable(dsi); - mtk_dsi_reset_engine(dsi); - mtk_dsi_phy_timconfig(dsi); - return 0; err_disable_engine_clk: @@ -300,7 +304,7 @@ err_refcount: static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi) { mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); - mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); + mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, LC_ULPM_EN); } static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) @@ -313,7 +317,7 @@ static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi) { mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0); - mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); + mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, LD0_ULPM_EN); } static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi) @@ -349,11 +353,21 @@ static void mtk_dsi_set_mode(struct mtk_dsi *dsi) if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) vid_mode = BURST_MODE; + else + vid_mode = SYNC_EVENT_MODE; } writel(vid_mode, dsi->regs + DSI_MODE_CTRL); } +static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) +{ + writel(0x3c, dsi->regs + DSI_MEM_CONTI); + + mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN); + mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); +} + static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) { struct videomode *vm = &dsi->vm; @@ -410,6 +424,9 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) break; } + tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; + tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); } @@ -488,6 +505,16 @@ static void mtk_dsi_start(struct mtk_dsi *dsi) writel(1, dsi->regs + DSI_START); } +static void mtk_dsi_stop(struct mtk_dsi *dsi) +{ + writel(0, dsi->regs + DSI_START); +} + +static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi) +{ + writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL); +} + static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi) { u32 inten = DSI_INT_ALL_BITS; @@ -525,6 +552,26 @@ static irqreturn_t mtk_dsi_irq(int irq, void *dev_id) return IRQ_HANDLED; } +static void mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi) +{ + s32 ret = 0; + unsigned long timeout = msecs_to_jiffies(500); + + dsi->irq_data &= ~VM_DONE_INT_FLAG; + + mtk_dsi_set_cmd_mode(dsi); + + ret = wait_event_interruptible_timeout(_dsi_irq_wait_queue, + dsi->irq_data & VM_DONE_INT_FLAG, + timeout); + if (ret == 0) { + dev_info(dsi->dev, "dsi wait engine idle timeout\n"); + + mtk_dsi_enable(dsi); + mtk_dsi_reset_engine(dsi); + } +} + static void mtk_dsi_poweroff(struct mtk_dsi *dsi) { if (WARN_ON(dsi->refcount == 0)) @@ -533,6 +580,17 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) if (--dsi->refcount != 0) return; + mtk_dsi_switch_to_cmd_mode(dsi); + + if (dsi->panel) { + if (drm_panel_unprepare(dsi->panel)) { + DRM_ERROR("failed to unprepare the panel\n"); + return; + } + } + + mtk_dsi_reset_engine(dsi); + mtk_dsi_lane0_ulp_mode_enter(dsi); mtk_dsi_clk_ulp_mode_enter(dsi); @@ -551,29 +609,37 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi) if (dsi->enabled) return; - if (dsi->panel) { - if (drm_panel_prepare(dsi->panel)) { - DRM_ERROR("failed to setup the panel\n"); - return; - } - } - ret = mtk_dsi_poweron(dsi); if (ret < 0) { DRM_ERROR("failed to power on dsi\n"); return; } + usleep_range(20000, 21000); + mtk_dsi_rxtx_control(dsi); + mtk_dsi_phy_timconfig(dsi); + mtk_dsi_ps_control_vact(dsi); + mtk_dsi_set_vm_cmd(dsi); + mtk_dsi_config_vdo_timing(dsi); + mtk_dsi_set_interrupt_enable(dsi); + mtk_dsi_enable(dsi); mtk_dsi_clk_ulp_mode_leave(dsi); mtk_dsi_lane0_ulp_mode_leave(dsi); mtk_dsi_clk_hs_mode(dsi, 0); - mtk_dsi_set_mode(dsi); - mtk_dsi_ps_control_vact(dsi); - mtk_dsi_config_vdo_timing(dsi); - mtk_dsi_set_interrupt_enable(dsi); + if (dsi->panel) { + if (drm_panel_prepare(dsi->panel)) { + DRM_ERROR("failed to prepare the panel\n"); + return; + } + + if (drm_panel_enable(dsi->panel)) { + DRM_ERROR("failed to enable the panel\n"); + return; + } + } mtk_dsi_set_mode(dsi); mtk_dsi_clk_hs_mode(dsi, 1); @@ -595,6 +661,7 @@ static void mtk_output_dsi_disable(struct mtk_dsi *dsi) } } + mtk_dsi_stop(dsi); mtk_dsi_poweroff(dsi); dsi->enabled = false; diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index 19481c7..0666f15 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -168,7 +168,9 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate); - if (mipi_tx->data_rate >= 500000000) { + if (mipi_tx->data_rate > 1250000000) { + return -EINVAL; + } else if (mipi_tx->data_rate >= 500000000) { txdiv = 1; txdiv0 = 0; txdiv1 = 0; @@ -192,6 +194,10 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) return -EINVAL; } + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON, + RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN, + (8 << 4) | RG_DSI_LNT_HS_BIAS_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON, RG_DSI_VOUT_MSK | RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN, @@ -201,24 +207,18 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) usleep_range(30, 100); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON, - RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN, - (8 << 4) | RG_DSI_LNT_HS_BIAS_EN); - - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON, - RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_CON, + RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN, + RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR, RG_DSI_MPPLL_SDM_PWR_ON | RG_DSI_MPPLL_SDM_ISO_EN, RG_DSI_MPPLL_SDM_PWR_ON); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, - RG_DSI_MPPLL_PLL_EN); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0, - RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 | - RG_DSI_MPPLL_PREDIV, + RG_DSI_MPPLL_PREDIV | RG_DSI_MPPLL_TXDIV0 | + RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_POSDIV, (txdiv0 << 3) | (txdiv1 << 5)); /* @@ -233,10 +233,12 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) 26000000); writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1, - RG_DSI_MPPLL_SDM_FRA_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON1, + RG_DSI_MPPLL_SDM_FRA_EN, + RG_DSI_MPPLL_SDM_FRA_EN); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0, + RG_DSI_MPPLL_PLL_EN, RG_DSI_MPPLL_PLL_EN); usleep_range(20, 100); -- 1.7.9.5