From mboxrd@z Thu Jan 1 00:00:00 1970 From: YT Shen Subject: Re: [PATCH v6 06/10] drm/mediatek: add dsi interrupt control Date: Wed, 10 Aug 2016 14:59:33 +0800 Message-ID: <1470812373.27526.1.camel@mtksdaap41> References: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> <1470308844-20895-7-git-send-email-yt.shen@mediatek.com> <1470392666.16554.61.camel@mtksdaap41> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1470392666.16554.61.camel@mtksdaap41> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: CK Hu Cc: Mark Rutland , dri-devel@lists.freedesktop.org, Russell King , Mao Huang , yingjoe.chen@mediatek.com, devicetree@vger.kernel.org, Sascha Hauer , Pawel Moll , Ian Campbell , Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , shaoming chen , linux-arm-kernel@lists.infradead.org, srv_heupstream@mediatek.com, emil.l.velikov@gmail.com, linux-kernel@vger.kernel.org, Kumar Gala List-Id: linux-mediatek@lists.infradead.org SGkgQ0ssCgpPbiBGcmksIDIwMTYtMDgtMDUgYXQgMTg6MjQgKzA4MDAsIENLIEh1IHdyb3RlOgo+ IEhpLCBZVDoKPiAKPiBPbiBUaHUsIDIwMTYtMDgtMDQgYXQgMTk6MDcgKzA4MDAsIFlUIFNoZW4g d3JvdGU6Cj4gPiBGcm9tOiBzaGFvbWluZyBjaGVuIDxzaGFvbWluZy5jaGVuQG1lZGlhdGVrLmNv bT4KPiA+IAo+ID4gYWRkIGRzaSBpbnRlcnJ1cHQgY29udHJvbAo+ID4gCj4gPiBTaWduZWQtb2Zm LWJ5OiBzaGFvbWluZyBjaGVuIDxzaGFvbWluZy5jaGVuQG1lZGlhdGVrLmNvbT4KPiA+IC0tLQo+ ID4gIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHNpLmMgfCAgIDc2ICsrKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysrKwo+ID4gIDEgZmlsZSBjaGFuZ2VkLCA3NiBpbnNlcnRp b25zKCspCj4gPiAKPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRr X2RzaS5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kc2kuYwo+ID4gaW5kZXggYTlj ZjVhMS4uZWVhNjE5MiAxMDA2NDQKPiA+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9t dGtfZHNpLmMKPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHNpLmMKPiA+ IEBAIC0xOCw2ICsxOCw3IEBACj4gPiAgI2luY2x1ZGUgPGRybS9kcm1fcGFuZWwuaD4KPiA+ICAj aW5jbHVkZSA8bGludXgvY2xrLmg+Cj4gPiAgI2luY2x1ZGUgPGxpbnV4L2NvbXBvbmVudC5oPgo+ ID4gKyNpbmNsdWRlIDxsaW51eC9pcnEuaD4KPiA+ICAjaW5jbHVkZSA8bGludXgvb2YuaD4KPiA+ ICAjaW5jbHVkZSA8bGludXgvb2ZfcGxhdGZvcm0uaD4KPiA+ICAjaW5jbHVkZSA8bGludXgvb2Zf Z3JhcGguaD4KPiA+IEBAIC0yOSw2ICszMCwxNyBAQAo+ID4gIAo+ID4gICNkZWZpbmUgRFNJX1NU QVJUCQkweDAwCj4gPiAgCj4gPiArI2RlZmluZSBEU0lfSU5URU4JCTB4MDgKPiA+ICsKPiA+ICsj ZGVmaW5lIERTSV9JTlRTVEEJCTB4MGMKPiA+ICsjZGVmaW5lIExQUlhfUkRfUkRZX0lOVF9GTEFH CQlCSVQoMCkKPiA+ICsjZGVmaW5lIENNRF9ET05FX0lOVF9GTEFHCQlCSVQoMSkKPiA+ICsjZGVm aW5lIFRFX1JEWV9JTlRfRkxBRwkJCUJJVCgyKQo+ID4gKyNkZWZpbmUgVk1fRE9ORV9JTlRfRkxB RwkJQklUKDMpCj4gPiArI2RlZmluZSBFWFRfVEVfUkRZX0lOVF9GTEFHCQlCSVQoNCkKPiA+ICsj ZGVmaW5lIERTSV9JTlRfQUxMX0JJVFMJCTB4MWYKPiA+ICsjZGVmaW5lIERTSV9CVVNZCQkJQklU KDMxKQo+ID4gKwo+ID4gICNkZWZpbmUgRFNJX0NPTl9DVFJMCQkweDEwCj4gPiAgI2RlZmluZSBE U0lfUkVTRVQJCQlCSVQoMCkKPiA+ICAjZGVmaW5lIERTSV9FTgkJCQlCSVQoMSkKPiA+IEBAIC03 MSw2ICs4Myw5IEBACj4gPiAgCj4gPiAgI2RlZmluZSBEU0lfSFNUWF9DS0xfV0MJCTB4NjQKPiA+ ICAKPiA+ICsjZGVmaW5lIERTSV9SQUNLCQkweDg0Cj4gPiArI2RlZmluZSBSQUNLCQkJCUJJVCgw KQo+ID4gKwo+ID4gICNkZWZpbmUgRFNJX1BIWV9MQ0NPTgkJMHgxMDQKPiA+ICAjZGVmaW5lIExD X0hTX1RYX0VOCQkJQklUKDApCj4gPiAgI2RlZmluZSBMQ19VTFBNX0VOCQkJQklUKDEpCj4gPiBA QCAtMTMxLDggKzE0NiwxMSBAQCBzdHJ1Y3QgbXRrX2RzaSB7Cj4gPiAgCXN0cnVjdCB2aWRlb21v ZGUgdm07Cj4gPiAgCWludCByZWZjb3VudDsKPiA+ICAJYm9vbCBlbmFibGVkOwo+ID4gKwlpbnQg aXJxX2RhdGE7Cj4gCj4gdTMyIGlycV9kYXRhOwpXaWxsIGRvLgoKUmVnYXJkcywKeXQuc2hlbgo+ IAo+ID4gIH07Cj4gPiAgCj4gPiArc3RhdGljIHdhaXRfcXVldWVfaGVhZF90IF9kc2lfaXJxX3dh aXRfcXVldWU7Cj4gPiArCj4gPiAgc3RhdGljIGlubGluZSBzdHJ1Y3QgbXRrX2RzaSAqZW5jb2Rl cl90b19kc2koc3RydWN0IGRybV9lbmNvZGVyICplKQo+ID4gIHsKPiA+ICAJcmV0dXJuIGNvbnRh aW5lcl9vZihlLCBzdHJ1Y3QgbXRrX2RzaSwgZW5jb2Rlcik7Cj4gPiBAQCAtNDM3LDYgKzQ1NSw0 MyBAQCBzdGF0aWMgdm9pZCBtdGtfZHNpX3N0YXJ0KHN0cnVjdCBtdGtfZHNpICpkc2kpCj4gPiAg CXdyaXRlbCgxLCBkc2ktPnJlZ3MgKyBEU0lfU1RBUlQpOwo+ID4gIH0KPiA+ICAKPiA+ICtzdGF0 aWMgdm9pZCBtdGtfZHNpX3NldF9pbnRlcnJ1cHRfZW5hYmxlKHN0cnVjdCBtdGtfZHNpICpkc2kp Cj4gPiArewo+ID4gKwl1MzIgaW50ZW4gPSBEU0lfSU5UX0FMTF9CSVRTOwo+ID4gKwo+ID4gKwlp ZiAoZHNpLT5tb2RlX2ZsYWdzICYgTUlQSV9EU0lfTU9ERV9WSURFTykKPiA+ICsJCWludGVuICY9 IH4oVEVfUkRZX0lOVF9GTEFHIHwgRVhUX1RFX1JEWV9JTlRfRkxBRyk7Cj4gPiArCj4gPiArCXdy aXRlbChpbnRlbiwgZHNpLT5yZWdzICsgRFNJX0lOVEVOKTsKPiA+ICt9Cj4gPiArCj4gPiArc3Rh dGljIHZvaWQgbXRrX2RzaV9pcnFfd2FrZXVwKHN0cnVjdCBtdGtfZHNpICpkc2ksIHUzMiBpcnFf Yml0KQo+ID4gK3sKPiA+ICsJZHNpLT5pcnFfZGF0YSB8PSBpcnFfYml0Owo+ID4gK30KPiA+ICsK PiA+ICtzdGF0aWMgaXJxcmV0dXJuX3QgbXRrX2RzaV9pcnEoaW50IGlycSwgdm9pZCAqZGV2X2lk KQo+ID4gK3sKPiA+ICsJc3RydWN0IG10a19kc2kgKmRzaSA9IGRldl9pZDsKPiA+ICsJdTMyIHN0 YXR1cywgdG1wOwo+ID4gKwl1MzIgZmxhZyA9IExQUlhfUkRfUkRZX0lOVF9GTEFHIHwgQ01EX0RP TkVfSU5UX0ZMQUcgfCBWTV9ET05FX0lOVF9GTEFHOwo+ID4gKwo+ID4gKwlzdGF0dXMgPSByZWFk bChkc2ktPnJlZ3MgKyBEU0lfSU5UU1RBKTsKPiA+ICsKPiA+ICsJaWYgKHN0YXR1cyAmIGZsYWcp IHsKPiA+ICsJCWRvIHsKPiA+ICsJCQltdGtfZHNpX21hc2soZHNpLCBEU0lfUkFDSywgUkFDSywg UkFDSyk7Cj4gPiArCQkJdG1wID0gcmVhZGwoZHNpLT5yZWdzICsgRFNJX0lOVFNUQSk7Cj4gPiAr CQl9IHdoaWxlICh0bXAgJiBEU0lfQlVTWSk7Cj4gPiArCj4gPiArCQltdGtfZHNpX21hc2soZHNp LCBEU0lfSU5UU1RBLCBzdGF0dXMgJiBmbGFnLCAwKTsKPiA+ICsJCW10a19kc2lfaXJxX3dha2V1 cChkc2ksIHN0YXR1cyAmIGZsYWcpOwo+ID4gKwkJd2FrZV91cF9pbnRlcnJ1cHRpYmxlKCZfZHNp X2lycV93YWl0X3F1ZXVlKTsKPiA+ICsJfQo+ID4gKwo+ID4gKwlyZXR1cm4gSVJRX0hBTkRMRUQ7 Cj4gPiArfQo+ID4gKwo+ID4gIHN0YXRpYyB2b2lkIG10a19kc2lfcG93ZXJvZmYoc3RydWN0IG10 a19kc2kgKmRzaSkKPiA+ICB7Cj4gPiAgCWlmIChXQVJOX09OKGRzaS0+cmVmY291bnQgPT0gMCkp Cj4gPiBAQCAtNDg1LDYgKzU0MCw3IEBAIHN0YXRpYyB2b2lkIG10a19vdXRwdXRfZHNpX2VuYWJs ZShzdHJ1Y3QgbXRrX2RzaSAqZHNpKQo+ID4gIAo+ID4gIAltdGtfZHNpX3BzX2NvbnRyb2xfdmFj dChkc2kpOwo+ID4gIAltdGtfZHNpX2NvbmZpZ192ZG9fdGltaW5nKGRzaSk7Cj4gPiArCW10a19k c2lfc2V0X2ludGVycnVwdF9lbmFibGUoZHNpKTsKPiA+ICAKPiA+ICAJbXRrX2RzaV9zZXRfbW9k ZShkc2kpOwo+ID4gIAltdGtfZHNpX2Nsa19oc19tb2RlKGRzaSwgMSk7Cj4gPiBAQCAtODA0LDYg Kzg2MCw3IEBAIHN0YXRpYyBpbnQgbXRrX2RzaV9wcm9iZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNl ICpwZGV2KQo+ID4gIAlzdHJ1Y3QgZGV2aWNlICpkZXYgPSAmcGRldi0+ZGV2Owo+ID4gIAlzdHJ1 Y3QgZGV2aWNlX25vZGUgKnJlbW90ZV9ub2RlLCAqZW5kcG9pbnQ7Cj4gPiAgCXN0cnVjdCByZXNv dXJjZSAqcmVnczsKPiA+ICsJaW50IGlycV9udW07Cj4gPiAgCWludCBjb21wX2lkOwo+ID4gIAlp bnQgcmV0Owo+ID4gIAo+ID4gQEAgLTg4MCw4ICs5MzcsMjcgQEAgc3RhdGljIGludCBtdGtfZHNp X3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCj4gPiAgCQlyZXR1cm4gcmV0Owo+ ID4gIAl9Cj4gPiAgCj4gPiArCWlycV9udW0gPSBwbGF0Zm9ybV9nZXRfaXJxKHBkZXYsIDApOwo+ ID4gKwlpZiAoaXJxX251bSA8IDApIHsKPiA+ICsJCWRldl9lcnIoJnBkZXYtPmRldiwgImZhaWxl ZCB0byByZXF1ZXN0IGRzaSBpcnEgcmVzb3VyY2VcbiIpOwo+ID4gKwkJcmV0dXJuIC1FUFJPQkVf REVGRVI7Cj4gPiArCX0KPiA+ICsKPiA+ICsJaXJxX3NldF9zdGF0dXNfZmxhZ3MoaXJxX251bSwg SVJRX1RZUEVfTEVWRUxfTE9XKTsKPiA+ICsJcmV0ID0gZGV2bV9yZXF1ZXN0X2lycSgmcGRldi0+ ZGV2LCBpcnFfbnVtLCBtdGtfZHNpX2lycSwKPiA+ICsJCQkgICAgICAgSVJRRl9UUklHR0VSX0xP VywgZGV2X25hbWUoJnBkZXYtPmRldiksIGRzaSk7Cj4gPiArCWlmIChyZXQpIHsKPiA+ICsJCWRl dl9lcnIoJnBkZXYtPmRldiwgImZhaWxlZCB0byByZXF1ZXN0IG1lZGlhdGVrIGRzaSBpcnFcbiIp Owo+ID4gKwkJcmV0dXJuIC1FUFJPQkVfREVGRVI7Cj4gPiArCX0KPiA+ICsKPiA+ICsJZHNpLT5p cnFfZGF0YSA9IDA7Cj4gPiArCWRldl9pbmZvKGRldiwgImRzaSBpcnEgbnVtIGlzIDB4JXhcbiIs IGlycV9udW0pOwo+ID4gKwo+ID4gIAlwbGF0Zm9ybV9zZXRfZHJ2ZGF0YShwZGV2LCBkc2kpOwo+ ID4gIAo+ID4gKwlpbml0X3dhaXRxdWV1ZV9oZWFkKCZfZHNpX2lycV93YWl0X3F1ZXVlKTsKPiA+ ICsKPiA+ICAJcmV0dXJuIGNvbXBvbmVudF9hZGQoJnBkZXYtPmRldiwgJm10a19kc2lfY29tcG9u ZW50X29wcyk7Cj4gPiAgfQo+ID4gIAo+IAo+IFJlZ2FyZHMsCj4gQ0sKPiAKCgpfX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBs aXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVz a3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: yt.shen@mediatek.com (YT Shen) Date: Wed, 10 Aug 2016 14:59:33 +0800 Subject: [PATCH v6 06/10] drm/mediatek: add dsi interrupt control In-Reply-To: <1470392666.16554.61.camel@mtksdaap41> References: <1470308844-20895-1-git-send-email-yt.shen@mediatek.com> <1470308844-20895-7-git-send-email-yt.shen@mediatek.com> <1470392666.16554.61.camel@mtksdaap41> Message-ID: <1470812373.27526.1.camel@mtksdaap41> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi CK, On Fri, 2016-08-05 at 18:24 +0800, CK Hu wrote: > Hi, YT: > > On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote: > > From: shaoming chen > > > > add dsi interrupt control > > > > Signed-off-by: shaoming chen > > --- > > drivers/gpu/drm/mediatek/mtk_dsi.c | 76 ++++++++++++++++++++++++++++++++++++ > > 1 file changed, 76 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c > > index a9cf5a1..eea6192 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > > @@ -18,6 +18,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -29,6 +30,17 @@ > > > > #define DSI_START 0x00 > > > > +#define DSI_INTEN 0x08 > > + > > +#define DSI_INTSTA 0x0c > > +#define LPRX_RD_RDY_INT_FLAG BIT(0) > > +#define CMD_DONE_INT_FLAG BIT(1) > > +#define TE_RDY_INT_FLAG BIT(2) > > +#define VM_DONE_INT_FLAG BIT(3) > > +#define EXT_TE_RDY_INT_FLAG BIT(4) > > +#define DSI_INT_ALL_BITS 0x1f > > +#define DSI_BUSY BIT(31) > > + > > #define DSI_CON_CTRL 0x10 > > #define DSI_RESET BIT(0) > > #define DSI_EN BIT(1) > > @@ -71,6 +83,9 @@ > > > > #define DSI_HSTX_CKL_WC 0x64 > > > > +#define DSI_RACK 0x84 > > +#define RACK BIT(0) > > + > > #define DSI_PHY_LCCON 0x104 > > #define LC_HS_TX_EN BIT(0) > > #define LC_ULPM_EN BIT(1) > > @@ -131,8 +146,11 @@ struct mtk_dsi { > > struct videomode vm; > > int refcount; > > bool enabled; > > + int irq_data; > > u32 irq_data; Will do. Regards, yt.shen > > > }; > > > > +static wait_queue_head_t _dsi_irq_wait_queue; > > + > > static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e) > > { > > return container_of(e, struct mtk_dsi, encoder); > > @@ -437,6 +455,43 @@ static void mtk_dsi_start(struct mtk_dsi *dsi) > > writel(1, dsi->regs + DSI_START); > > } > > > > +static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi) > > +{ > > + u32 inten = DSI_INT_ALL_BITS; > > + > > + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) > > + inten &= ~(TE_RDY_INT_FLAG | EXT_TE_RDY_INT_FLAG); > > + > > + writel(inten, dsi->regs + DSI_INTEN); > > +} > > + > > +static void mtk_dsi_irq_wakeup(struct mtk_dsi *dsi, u32 irq_bit) > > +{ > > + dsi->irq_data |= irq_bit; > > +} > > + > > +static irqreturn_t mtk_dsi_irq(int irq, void *dev_id) > > +{ > > + struct mtk_dsi *dsi = dev_id; > > + u32 status, tmp; > > + u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; > > + > > + status = readl(dsi->regs + DSI_INTSTA); > > + > > + if (status & flag) { > > + do { > > + mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK); > > + tmp = readl(dsi->regs + DSI_INTSTA); > > + } while (tmp & DSI_BUSY); > > + > > + mtk_dsi_mask(dsi, DSI_INTSTA, status & flag, 0); > > + mtk_dsi_irq_wakeup(dsi, status & flag); > > + wake_up_interruptible(&_dsi_irq_wait_queue); > > + } > > + > > + return IRQ_HANDLED; > > +} > > + > > static void mtk_dsi_poweroff(struct mtk_dsi *dsi) > > { > > if (WARN_ON(dsi->refcount == 0)) > > @@ -485,6 +540,7 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi) > > > > mtk_dsi_ps_control_vact(dsi); > > mtk_dsi_config_vdo_timing(dsi); > > + mtk_dsi_set_interrupt_enable(dsi); > > > > mtk_dsi_set_mode(dsi); > > mtk_dsi_clk_hs_mode(dsi, 1); > > @@ -804,6 +860,7 @@ static int mtk_dsi_probe(struct platform_device *pdev) > > struct device *dev = &pdev->dev; > > struct device_node *remote_node, *endpoint; > > struct resource *regs; > > + int irq_num; > > int comp_id; > > int ret; > > > > @@ -880,8 +937,27 @@ static int mtk_dsi_probe(struct platform_device *pdev) > > return ret; > > } > > > > + irq_num = platform_get_irq(pdev, 0); > > + if (irq_num < 0) { > > + dev_err(&pdev->dev, "failed to request dsi irq resource\n"); > > + return -EPROBE_DEFER; > > + } > > + > > + irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW); > > + ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq, > > + IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi); > > + if (ret) { > > + dev_err(&pdev->dev, "failed to request mediatek dsi irq\n"); > > + return -EPROBE_DEFER; > > + } > > + > > + dsi->irq_data = 0; > > + dev_info(dev, "dsi irq num is 0x%x\n", irq_num); > > + > > platform_set_drvdata(pdev, dsi); > > > > + init_waitqueue_head(&_dsi_irq_wait_queue); > > + > > return component_add(&pdev->dev, &mtk_dsi_component_ops); > > } > > > > Regards, > CK >