diff for duplicates of <1470814357.27526.20.camel@mtksdaap41>

diff --git a/a/1.txt b/N1/1.txt
index 66a2bb6..0ce9e1e 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -31,7 +31,7 @@ On Fri, 2016-08-05 at 14:18 +0800, CK Hu wrote:
 > >  		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
 > >  	};
 > >  
-> > +	mipi_tx0: mipi-dphy@10010000 {
+> > +	mipi_tx0: mipi-dphy at 10010000 {
 > > +		compatible = "mediatek,mt2701-mipi-tx";
 > > +		reg = <0 0x10010000 0 0x90>;
 > > +		clocks = <&clk26m>;
@@ -41,14 +41,14 @@ On Fri, 2016-08-05 at 14:18 +0800, CK Hu wrote:
 > > +		status = "disabled";
 > > +	};
 > > +
-> >  	sysirq: interrupt-controller@10200100 {
+> >  	sysirq: interrupt-controller at 10200100 {
 > >  		compatible = "mediatek,mt2701-sysirq",
 > >  			     "mediatek,mt6577-sysirq";
 > > @@ -255,6 +270,68 @@
 > >  		status = "disabled";
 > >  	};
 > >  
-> > +	ovl@14007000 {
+> > +	ovl at 14007000 {
 > > +		compatible = "mediatek,mt2701-disp-ovl";
 > > +		reg = <0 0x14007000 0 0x1000>;
 > > +		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
@@ -57,7 +57,7 @@ On Fri, 2016-08-05 at 14:18 +0800, CK Hu wrote:
 > > +		mediatek,larb = <&larb0>;
 > > +	};
 > > +
-> > +	rdma0: rdma@14008000 {
+> > +	rdma0: rdma at 14008000 {
 > > +		compatible = "mediatek,mt2701-disp-rdma";
 > > +		reg = <0 0x14008000 0 0x1000>;
 > > +		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
@@ -66,7 +66,7 @@ On Fri, 2016-08-05 at 14:18 +0800, CK Hu wrote:
 > > +		mediatek,larb = <&larb0>;
 > > +	};
 > > +
-> > +	wdma@14009000 {
+> > +	wdma at 14009000 {
 > > +		compatible = "mediatek,mt2701-disp-wdma";
 > > +		reg = <0 0x14009000 0 0x1000>;
 > > +		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
@@ -75,7 +75,7 @@ On Fri, 2016-08-05 at 14:18 +0800, CK Hu wrote:
 > > +		mediatek,larb = <&larb0>;
 > > +	};
 > > +
-> > +	bls@1400a000 {
+> > +	bls at 1400a000 {
 > > +		compatible = "mediatek,mt2701-disp-pwm";
 > > +		reg = <0 0x1400a000 0 0x1000>;
 > > +		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_LOW>;
@@ -97,14 +97,14 @@ yt,shen
 > MediaTek display PWM bindings")
 > [2] https://patchwork.kernel.org/patch/9223005/
 > > +
-> > +	color@1400b000 {
+> > +	color at 1400b000 {
 > > +		compatible = "mediatek,mt2701-disp-color";
 > > +		reg = <0 0x1400b000 0 0x1000>;
 > > +		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
 > > +		clocks = <&mmsys CLK_MM_DISP_COLOR>;
 > > +	};
 > > +
-> > +	dsi0: dsi@1400c000 {
+> > +	dsi0: dsi at 1400c000 {
 > > +		compatible = "mediatek,mt2701-dsi";
 > > +		reg = <0 0x1400c000 0 0x1000>;
 > > +		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
@@ -118,21 +118,21 @@ yt,shen
 > > +		status = "disabled";
 > > +	};
 > > +
-> > +	mutex: mutex@1400e000 {
+> > +	mutex: mutex at 1400e000 {
 > > +		compatible = "mediatek,mt2701-disp-mutex";
 > > +		reg = <0 0x1400e000 0 0x1000>;
 > > +		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
 > > +		clocks = <&mmsys CLK_MM_MUTEX_32K>;
 > > +	};
 > > +
-> >  	larb0: larb@14010000 {
+> >  	larb0: larb at 14010000 {
 > >  		compatible = "mediatek,mt2701-smi-larb";
 > >  		reg = <0 0x14010000 0 0x1000>;
 > > @@ -266,6 +343,15 @@
 > >  		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
 > >  	};
 > >  
-> > +	rdma1: rdma@14012000 {
+> > +	rdma1: rdma at 14012000 {
 > > +		compatible = "mediatek,mt2701-disp-rdma";
 > > +		reg = <0 0x14012000 0 0x1000>;
 > > +		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
@@ -141,16 +141,10 @@ yt,shen
 > > +		mediatek,larb = <&larb0>;
 > > +	};
 > > +
-> >  	imgsys: syscon@15000000 {
+> >  	imgsys: syscon at 15000000 {
 > >  		compatible = "mediatek,mt2701-imgsys", "syscon";
 > >  		reg = <0 0x15000000 0 0x1000>;
 > 
 > Regards,
 > CK
-> 
-
-
-_______________________________________________
-dri-devel mailing list
-dri-devel@lists.freedesktop.org
-https://lists.freedesktop.org/mailman/listinfo/dri-devel
+>
diff --git a/a/content_digest b/N1/content_digest
index d88c0b6..6dd8a95 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,27 +1,10 @@
  "ref\01470308844-20895-1-git-send-email-yt.shen@mediatek.com\0"
  "ref\01470308844-20895-11-git-send-email-yt.shen@mediatek.com\0"
  "ref\01470377906.16554.23.camel@mtksdaap41\0"
- "From\0YT Shen <yt.shen@mediatek.com>\0"
- "Subject\0Re: [PATCH v6 10/10] arm: dts: mt2701: Add display subsystem related nodes for MT2701\0"
+ "From\0yt.shen@mediatek.com (YT Shen)\0"
+ "Subject\0[PATCH v6 10/10] arm: dts: mt2701: Add display subsystem related nodes for MT2701\0"
  "Date\0Wed, 10 Aug 2016 15:32:37 +0800\0"
- "To\0CK Hu <ck.hu@mediatek.com>\0"
- "Cc\0Mark Rutland <mark.rutland@arm.com>"
-  devicetree@vger.kernel.org
-  Russell King <linux@arm.linux.org.uk>
-  Pawel Moll <pawel.moll@arm.com>
-  Ian Campbell <ijc+devicetree@hellion.org.uk>
-  emil.l.velikov@gmail.com
-  linux-kernel@vger.kernel.org
-  dri-devel@lists.freedesktop.org
-  Mao Huang <littlecvr@chromium.org>
-  srv_heupstream@mediatek.com
-  Rob Herring <robh+dt@kernel.org>
-  linux-mediatek@lists.infradead.org
-  Kumar Gala <galak@codeaurora.org>
-  Matthias Brugger <matthias.bgg@gmail.com>
-  yingjoe.chen@mediatek.com
-  Sascha Hauer <kernel@pengutronix.de>
- " linux-arm-kernel@lists.infradead.org\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "Hi CK,\n"
@@ -57,7 +40,7 @@
  "> >  \t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;\n"
  "> >  \t};\n"
  "> >  \n"
- "> > +\tmipi_tx0: mipi-dphy@10010000 {\n"
+ "> > +\tmipi_tx0: mipi-dphy at 10010000 {\n"
  "> > +\t\tcompatible = \"mediatek,mt2701-mipi-tx\";\n"
  "> > +\t\treg = <0 0x10010000 0 0x90>;\n"
  "> > +\t\tclocks = <&clk26m>;\n"
@@ -67,14 +50,14 @@
  "> > +\t\tstatus = \"disabled\";\n"
  "> > +\t};\n"
  "> > +\n"
- "> >  \tsysirq: interrupt-controller@10200100 {\n"
+ "> >  \tsysirq: interrupt-controller at 10200100 {\n"
  "> >  \t\tcompatible = \"mediatek,mt2701-sysirq\",\n"
  "> >  \t\t\t     \"mediatek,mt6577-sysirq\";\n"
  "> > @@ -255,6 +270,68 @@\n"
  "> >  \t\tstatus = \"disabled\";\n"
  "> >  \t};\n"
  "> >  \n"
- "> > +\tovl@14007000 {\n"
+ "> > +\tovl at 14007000 {\n"
  "> > +\t\tcompatible = \"mediatek,mt2701-disp-ovl\";\n"
  "> > +\t\treg = <0 0x14007000 0 0x1000>;\n"
  "> > +\t\tinterrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;\n"
@@ -83,7 +66,7 @@
  "> > +\t\tmediatek,larb = <&larb0>;\n"
  "> > +\t};\n"
  "> > +\n"
- "> > +\trdma0: rdma@14008000 {\n"
+ "> > +\trdma0: rdma at 14008000 {\n"
  "> > +\t\tcompatible = \"mediatek,mt2701-disp-rdma\";\n"
  "> > +\t\treg = <0 0x14008000 0 0x1000>;\n"
  "> > +\t\tinterrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;\n"
@@ -92,7 +75,7 @@
  "> > +\t\tmediatek,larb = <&larb0>;\n"
  "> > +\t};\n"
  "> > +\n"
- "> > +\twdma@14009000 {\n"
+ "> > +\twdma at 14009000 {\n"
  "> > +\t\tcompatible = \"mediatek,mt2701-disp-wdma\";\n"
  "> > +\t\treg = <0 0x14009000 0 0x1000>;\n"
  "> > +\t\tinterrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;\n"
@@ -101,7 +84,7 @@
  "> > +\t\tmediatek,larb = <&larb0>;\n"
  "> > +\t};\n"
  "> > +\n"
- "> > +\tbls@1400a000 {\n"
+ "> > +\tbls at 1400a000 {\n"
  "> > +\t\tcompatible = \"mediatek,mt2701-disp-pwm\";\n"
  "> > +\t\treg = <0 0x1400a000 0 0x1000>;\n"
  "> > +\t\tinterrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_LOW>;\n"
@@ -123,14 +106,14 @@
  "> MediaTek display PWM bindings\")\n"
  "> [2] https://patchwork.kernel.org/patch/9223005/\n"
  "> > +\n"
- "> > +\tcolor@1400b000 {\n"
+ "> > +\tcolor at 1400b000 {\n"
  "> > +\t\tcompatible = \"mediatek,mt2701-disp-color\";\n"
  "> > +\t\treg = <0 0x1400b000 0 0x1000>;\n"
  "> > +\t\tinterrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;\n"
  "> > +\t\tclocks = <&mmsys CLK_MM_DISP_COLOR>;\n"
  "> > +\t};\n"
  "> > +\n"
- "> > +\tdsi0: dsi@1400c000 {\n"
+ "> > +\tdsi0: dsi at 1400c000 {\n"
  "> > +\t\tcompatible = \"mediatek,mt2701-dsi\";\n"
  "> > +\t\treg = <0 0x1400c000 0 0x1000>;\n"
  "> > +\t\tinterrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;\n"
@@ -144,21 +127,21 @@
  "> > +\t\tstatus = \"disabled\";\n"
  "> > +\t};\n"
  "> > +\n"
- "> > +\tmutex: mutex@1400e000 {\n"
+ "> > +\tmutex: mutex at 1400e000 {\n"
  "> > +\t\tcompatible = \"mediatek,mt2701-disp-mutex\";\n"
  "> > +\t\treg = <0 0x1400e000 0 0x1000>;\n"
  "> > +\t\tinterrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;\n"
  "> > +\t\tclocks = <&mmsys CLK_MM_MUTEX_32K>;\n"
  "> > +\t};\n"
  "> > +\n"
- "> >  \tlarb0: larb@14010000 {\n"
+ "> >  \tlarb0: larb at 14010000 {\n"
  "> >  \t\tcompatible = \"mediatek,mt2701-smi-larb\";\n"
  "> >  \t\treg = <0 0x14010000 0 0x1000>;\n"
  "> > @@ -266,6 +343,15 @@\n"
  "> >  \t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;\n"
  "> >  \t};\n"
  "> >  \n"
- "> > +\trdma1: rdma@14012000 {\n"
+ "> > +\trdma1: rdma at 14012000 {\n"
  "> > +\t\tcompatible = \"mediatek,mt2701-disp-rdma\";\n"
  "> > +\t\treg = <0 0x14012000 0 0x1000>;\n"
  "> > +\t\tinterrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;\n"
@@ -167,18 +150,12 @@
  "> > +\t\tmediatek,larb = <&larb0>;\n"
  "> > +\t};\n"
  "> > +\n"
- "> >  \timgsys: syscon@15000000 {\n"
+ "> >  \timgsys: syscon at 15000000 {\n"
  "> >  \t\tcompatible = \"mediatek,mt2701-imgsys\", \"syscon\";\n"
  "> >  \t\treg = <0 0x15000000 0 0x1000>;\n"
  "> \n"
  "> Regards,\n"
  "> CK\n"
- "> \n"
- "\n"
- "\n"
- "_______________________________________________\n"
- "dri-devel mailing list\n"
- "dri-devel@lists.freedesktop.org\n"
- https://lists.freedesktop.org/mailman/listinfo/dri-devel
+ >
 
-73a8d50b6877496f54494382e5badf2e2fd62e0960f308d9e869b76a816ad0f1
+ed7c59da95af6b99c3f5c85a2bf68d44d853ba5cc46c75219b37476f311a8d9b
