From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bibby Hsieh Subject: Re: [PATCH v3 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K Date: Mon, 15 Aug 2016 14:51:16 +0800 Message-ID: <1471243876.2906.9.camel@mtksdaap41> References: <1470278311-22528-1-git-send-email-bibby.hsieh@mediatek.com> <1470278311-22528-4-git-send-email-bibby.hsieh@mediatek.com> <1470899712.2493.16.camel@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1470899712.2493.16.camel@pengutronix.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Philipp Zabel Cc: Junzhi Zhao , linux-kernel@vger.kernel.org, Daniel Vetter , Cawa Cheng , dri-devel@lists.freedesktop.org, Mao Huang , linux-mediatek@lists.infradead.org, Sascha Hauer , Matthias Brugger , Yingjoe Chen , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org SGksIFBoaWxpcHAsCgpPbiBUaHUsIDIwMTYtMDgtMTEgYXQgMDk6MTUgKzAyMDAsIFBoaWxpcHAg WmFiZWwgd3JvdGU6Cj4gQW0gRG9ubmVyc3RhZywgZGVuIDA0LjA4LjIwMTYsIDEwOjM4ICswODAw IHNjaHJpZWIgQmliYnkgSHNpZWg6Cj4gPiBGcm9tOiBKdW56aGkgWmhhbyA8anVuemhpLnpoYW9A bWVkaWF0ZWsuY29tPgo+ID4gCj4gPiBQaXhlbCBjbG9jayBzaG91bGQgYmUgMjk3TUh6IHdoZW4g cmVzb2x1dGlvbiBpcyA0Sy4KPiA+IAo+ID4gU2lnbmVkLW9mZi1ieTogSnVuemhpIFpoYW8gPGp1 bnpoaS56aGFvQG1lZGlhdGVrLmNvbT4KPiA+IFNpZ25lZC1vZmYtYnk6IEJpYmJ5IEhzaWVoIDxi aWJieS5oc2llaEBtZWRpYXRlay5jb20+Cj4gPiAtLS0KPiA+ICBkcml2ZXJzL2dwdS9kcm0vbWVk aWF0ZWsvbXRrX2RwaS5jIHwgICAgOCArKysrKystLQo+ID4gIDEgZmlsZSBjaGFuZ2VkLCA2IGlu c2VydGlvbnMoKyksIDIgZGVsZXRpb25zKC0pCj4gPiAKPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJz L2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RwaS5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210 a19kcGkuYwo+ID4gaW5kZXggZDA1Y2E3OS4uYTkwYWY1OSAxMDA2NDQKPiA+IC0tLSBhL2RyaXZl cnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHBpLmMKPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9t ZWRpYXRlay9tdGtfZHBpLmMKPiA+IEBAIC00MzgsMTAgKzQzOCwxNCBAQCBzdGF0aWMgaW50IG10 a19kcGlfc2V0X2Rpc3BsYXlfbW9kZShzdHJ1Y3QgbXRrX2RwaSAqZHBpLAo+ID4gIAl9Cj4gPiAg Cj4gPiAgCXBpeF9yYXRlID0gMTAwMFVMICogbW9kZS0+Y2xvY2s7Cj4gPiAtCWlmIChtb2RlLT5j bG9jayA8PSA3NDAwMCkKPiA+ICsJaWYgKG1vZGUtPmNsb2NrIDw9IDI3MDAwKQo+ID4gKwkJZmFj dG9yID0gMTYgKiAzOwo+ID4gKwllbHNlIGlmIChtb2RlLT5jbG9jayA8PSA3NDI1MCkKPiA+ICAJ CWZhY3RvciA9IDggKiAzOwo+ID4gLQllbHNlCj4gPiArCWVsc2UgaWYgKG1vZGUtPmNsb2NrIDw9 IDE2NzAwMCkKPiA+ICAJCWZhY3RvciA9IDQgKiAzOwo+ID4gKwllbHNlCj4gPiArCQlmYWN0b3Ig PSAyICogMzsKPiA+ICAJcGxsX3JhdGUgPSBwaXhfcmF0ZSAqIGZhY3RvcjsKPiA+ICAKPiA+ICAJ ZGV2X2RiZyhkcGktPmRldiwgIldhbnQgUExMICVsdSBIeiwgcGl4ZWwgY2xvY2sgJWx1IEh6XG4i LAo+IAo+IENvdWxkIHlvdSBhZGQgYSBjb21tZW50IHdoeSB0aGlzIGFsc28gY2hhbmdlcyB0aGUg NzQgTUh6IGxpbWl0IHRvIDc0LjI1Cj4gTUh6IGFuZCB0aGF0IGFkZHMgYSBmYWN0b3IgMTYqMyBm b3IgY2xvY2tzIDw9IDI3IE1IeiA/Cj4gCkJlY2F1c2UgdGhlIHZhbGlkIHJhbmdlIG9mIHR2ZHBs bCBpcyBmcm9tIDFHSHogdG8gMkdIeiwgc28sIHdlIGhhdmUgdG8KbWFrZSB0aGUgY2xvY2sgdG8g Zml0IHRoYXQuCgo+IHJlZ2FyZHMKPiBQaGlsaXBwCj4gCgotLSAKQmliYnkKCl9fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxp c3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNr dG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: bibby.hsieh@mediatek.com (Bibby Hsieh) Date: Mon, 15 Aug 2016 14:51:16 +0800 Subject: [PATCH v3 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K In-Reply-To: <1470899712.2493.16.camel@pengutronix.de> References: <1470278311-22528-1-git-send-email-bibby.hsieh@mediatek.com> <1470278311-22528-4-git-send-email-bibby.hsieh@mediatek.com> <1470899712.2493.16.camel@pengutronix.de> Message-ID: <1471243876.2906.9.camel@mtksdaap41> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, Philipp, On Thu, 2016-08-11 at 09:15 +0200, Philipp Zabel wrote: > Am Donnerstag, den 04.08.2016, 10:38 +0800 schrieb Bibby Hsieh: > > From: Junzhi Zhao > > > > Pixel clock should be 297MHz when resolution is 4K. > > > > Signed-off-by: Junzhi Zhao > > Signed-off-by: Bibby Hsieh > > --- > > drivers/gpu/drm/mediatek/mtk_dpi.c | 8 ++++++-- > > 1 file changed, 6 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > > index d05ca79..a90af59 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > > @@ -438,10 +438,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, > > } > > > > pix_rate = 1000UL * mode->clock; > > - if (mode->clock <= 74000) > > + if (mode->clock <= 27000) > > + factor = 16 * 3; > > + else if (mode->clock <= 74250) > > factor = 8 * 3; > > - else > > + else if (mode->clock <= 167000) > > factor = 4 * 3; > > + else > > + factor = 2 * 3; > > pll_rate = pix_rate * factor; > > > > dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", > > Could you add a comment why this also changes the 74 MHz limit to 74.25 > MHz and that adds a factor 16*3 for clocks <= 27 MHz ? > Because the valid range of tvdpll is from 1GHz to 2GHz, so, we have to make the clock to fit that. > regards > Philipp > -- Bibby From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752883AbcHOGvX (ORCPT ); Mon, 15 Aug 2016 02:51:23 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:25958 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751488AbcHOGvU (ORCPT ); Mon, 15 Aug 2016 02:51:20 -0400 Message-ID: <1471243876.2906.9.camel@mtksdaap41> Subject: Re: [PATCH v3 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K From: Bibby Hsieh To: Philipp Zabel CC: David Airlie , Matthias Brugger , Daniel Vetter , , , Yingjoe Chen , Cawa Cheng , Daniel Kurtz , YT Shen , Thierry Reding , CK Hu , Mao Huang , , , "Sascha Hauer" , Junzhi Zhao Date: Mon, 15 Aug 2016 14:51:16 +0800 In-Reply-To: <1470899712.2493.16.camel@pengutronix.de> References: <1470278311-22528-1-git-send-email-bibby.hsieh@mediatek.com> <1470278311-22528-4-git-send-email-bibby.hsieh@mediatek.com> <1470899712.2493.16.camel@pengutronix.de> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Philipp, On Thu, 2016-08-11 at 09:15 +0200, Philipp Zabel wrote: > Am Donnerstag, den 04.08.2016, 10:38 +0800 schrieb Bibby Hsieh: > > From: Junzhi Zhao > > > > Pixel clock should be 297MHz when resolution is 4K. > > > > Signed-off-by: Junzhi Zhao > > Signed-off-by: Bibby Hsieh > > --- > > drivers/gpu/drm/mediatek/mtk_dpi.c | 8 ++++++-- > > 1 file changed, 6 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > > index d05ca79..a90af59 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > > @@ -438,10 +438,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, > > } > > > > pix_rate = 1000UL * mode->clock; > > - if (mode->clock <= 74000) > > + if (mode->clock <= 27000) > > + factor = 16 * 3; > > + else if (mode->clock <= 74250) > > factor = 8 * 3; > > - else > > + else if (mode->clock <= 167000) > > factor = 4 * 3; > > + else > > + factor = 2 * 3; > > pll_rate = pix_rate * factor; > > > > dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", > > Could you add a comment why this also changes the 74 MHz limit to 74.25 > MHz and that adds a factor 16*3 for clocks <= 27 MHz ? > Because the valid range of tvdpll is from 1GHz to 2GHz, so, we have to make the clock to fit that. > regards > Philipp > -- Bibby