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diff for duplicates of <1471264912.4887.117.camel@linux.intel.com>

diff --git a/a/1.txt b/N1/1.txt
index 3f3d4e7..607c911 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,10 +1,10 @@
-On Mon, 2016-08-15@11:10 +0000, Eugeniy Paltsev wrote:
-> On Fri, 2016-08-12@17:08 +0300, Andy Shevchenko wrote:
-> > ?
+On Mon, 2016-08-15 at 11:10 +0000, Eugeniy Paltsev wrote:
+> On Fri, 2016-08-12 at 17:08 +0300, Andy Shevchenko wrote:
+> >  
 > > > > > "nollp" parameter defines if DW DMAC channel supports multi
 > > > > > block
 > > > > > transfer or not.
-> > > > > ?
+> > > > >  
 > > > > > It is calculated in runtime, but differently depending on on
 > > > > > availability of pdata. If pdata is absent "nollp" is
 > > > > > calculated
@@ -15,18 +15,18 @@ On Mon, 2016-08-15@11:10 +0000, Eugeniy Paltsev wrote:
 > > > > > channel_writel(dwc, LLP, DWC_LLP_LOC(0xffffffff));
 > > > > > dwc->nollp = DWC_LLP_LOC(channel_readl(dwc, LLP)) == 0;
 > > > > > channel_writel(dwc, LLP, 0);
-> > > > > ?
+> > > > >  
 > > > > > I realized that these methods give different results.
 > > > > > For example on ARC AXS101 SDP in case of using autoconfig
 > > > > > "nollp"
 > > > > > was
-> > > > > calculated as "true" (and DMAC works fine),?
+> > > > > calculated as "true" (and DMAC works fine), 
 > > > > > otherwise "nollp" was calculated as "false" (and DMAC doesn't
 > > > > > work).
 > > > > Can you show out what the value you read back?
 > > > channel_readl(dwc, LLP) return 0xfffffffc
 > > Nice.
-> > ?
+> >  
 > > Oh, forgot to ask, what are the DW_PARAMS and DWC_PARAMS[x] are on
 > > the same hardware?
 > DW_PARAMS: 0x38280b0c
@@ -39,7 +39,7 @@ Wow, you have two masters with number 3 and 4? (Just out of curiosity)
 > DWC_PARAMS[3]: 0x4926d300
 
 A-ha, seems you have CHx_HC_LLP == 0. That may explain.
-?
 > > > > > So I'm wondering how the code in question really works?
 > > > > > From DW AHB DMAC databook I wasn't able to find anything
 > > > > > relevant
@@ -59,18 +59,18 @@ A-ha, seems you have CHx_HC_LLP == 0. That may explain.
 > > some
 > > internal Synopsys documentation which might shed a light. Or maybe I
 > > missed something else which should be considered.
-> Looks like this code based on idea, what if DMA ip-core doesn't have?
+> Looks like this code based on idea, what if DMA ip-core doesn't have 
 > LLP support it will not have LLP registers. It is not necessarily
 > true.
 
 Yep.
 
-Consider to review?
+Consider to review 
 http://www.spinics.net/lists/dmaengine/msg10682.html
 
 
-> > ?
-> Please add this code to read "is_memcpy" and "is_nollp" property?
+> >  
+> Please add this code to read "is_memcpy" and "is_nollp" property 
 > from device tree.
 > ----------------------------->8------------------------------
 > diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
@@ -78,21 +78,21 @@ http://www.spinics.net/lists/dmaengine/msg10682.html
 > --- a/drivers/dma/dw/platform.c
 > +++ b/drivers/dma/dw/platform.c
 > @@ -129,6 +129,12 @@ dw_dma_parse_dt(struct platform_device *pdev)
-> ????????if (of_property_read_bool(np, "is_private"))
-> ????????????????pdata->is_private = true;
-> ?
-> +???????if (of_property_read_bool(np, "is_memcpy"))
-> +???????????????pdata->is_memcpy = true;
+>         if (of_property_read_bool(np, "is_private"))
+>                 pdata->is_private = true;
+>  
+> +       if (of_property_read_bool(np, "is_memcpy"))
+> +               pdata->is_memcpy = true;
 > +
-> +???????if (of_property_read_bool(np, "is_nollp"))
-> +???????????????pdata->is_nollp = true;
+> +       if (of_property_read_bool(np, "is_nollp"))
+> +               pdata->is_nollp = true;
 > +
-> ????????if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
-> ????????????????pdata->chan_allocation_order = (unsigned char)tmp;
+>         if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
+>                 pdata->chan_allocation_order = (unsigned char)tmp;
 
 Please, make this as a patch and submit either separately, or with your
 series mentioning that it has a dependency to my 8250 LPSS series.
 
 -- 
-Andy Shevchenko <andriy.shevchenko at linux.intel.com>
+Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 Intel Finland Oy
diff --git a/a/content_digest b/N1/content_digest
index 75e141a..2d01608 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -3,19 +3,25 @@
  "ref\01471008972.21247.40.camel@synopsys.com\0"
  "ref\01471010908.4887.100.camel@linux.intel.com\0"
  "ref\01471259434.21247.47.camel@synopsys.com\0"
- "From\0andriy.shevchenko@linux.intel.com (Andy Shevchenko)\0"
- "Subject\0Wrong \"nollp\" DW DMAC parameter value on ARC SDP.\0"
+ "From\0Andy Shevchenko <andriy.shevchenko@linux.intel.com>\0"
+ "Subject\0Re: Wrong \"nollp\" DW DMAC parameter value on ARC SDP.\0"
  "Date\0Mon, 15 Aug 2016 15:41:52 +0300\0"
- "To\0linux-snps-arc@lists.infradead.org\0"
+ "To\0Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\0"
+ "Cc\0dmaengine@vger.kernel.org <dmaengine@vger.kernel.org>"
+  linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>
+  viresh.kumar@linaro.org <viresh.kumar@linaro.org>
+  Nelson.Pereira@synopsys.com <Nelson.Pereira@synopsys.com>
+  vinod.koul@intel.com <vinod.koul@intel.com>
+ " linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org>\0"
  "\00:1\0"
  "b\0"
- "On Mon, 2016-08-15@11:10 +0000, Eugeniy Paltsev wrote:\n"
- "> On Fri, 2016-08-12@17:08 +0300, Andy Shevchenko wrote:\n"
- "> > ?\n"
+ "On Mon, 2016-08-15 at 11:10 +0000, Eugeniy Paltsev wrote:\n"
+ "> On Fri, 2016-08-12 at 17:08 +0300, Andy Shevchenko wrote:\n"
+ "> > \302\240\n"
  "> > > > > \"nollp\" parameter defines if DW DMAC channel supports multi\n"
  "> > > > > block\n"
  "> > > > > transfer or not.\n"
- "> > > > > ?\n"
+ "> > > > > \302\240\n"
  "> > > > > It is calculated in runtime, but differently depending on on\n"
  "> > > > > availability of pdata. If pdata is absent \"nollp\" is\n"
  "> > > > > calculated\n"
@@ -26,18 +32,18 @@
  "> > > > > channel_writel(dwc, LLP, DWC_LLP_LOC(0xffffffff));\n"
  "> > > > > dwc->nollp = DWC_LLP_LOC(channel_readl(dwc, LLP)) == 0;\n"
  "> > > > > channel_writel(dwc, LLP, 0);\n"
- "> > > > > ?\n"
+ "> > > > > \302\240\n"
  "> > > > > I realized that these methods give different results.\n"
  "> > > > > For example on ARC AXS101 SDP in case of using autoconfig\n"
  "> > > > > \"nollp\"\n"
  "> > > > > was\n"
- "> > > > > calculated as \"true\" (and DMAC works fine),?\n"
+ "> > > > > calculated as \"true\" (and DMAC works fine),\302\240\n"
  "> > > > > otherwise \"nollp\" was calculated as \"false\" (and DMAC doesn't\n"
  "> > > > > work).\n"
  "> > > > Can you show out what the value you read back?\n"
  "> > > channel_readl(dwc, LLP) return 0xfffffffc\n"
  "> > Nice.\n"
- "> > ?\n"
+ "> > \302\240\n"
  "> > Oh, forgot to ask, what are the DW_PARAMS and DWC_PARAMS[x] are on\n"
  "> > the same hardware?\n"
  "> DW_PARAMS: 0x38280b0c\n"
@@ -50,7 +56,7 @@
  "> DWC_PARAMS[3]: 0x4926d300\n"
  "\n"
  "A-ha, seems you have CHx_HC_LLP == 0. That may explain.\n"
- "?\n"
+ "\302\240\n"
  "> > > > > So I'm wondering how the code in question really works?\n"
  "> > > > > From DW AHB DMAC databook I wasn't able to find anything\n"
  "> > > > > relevant\n"
@@ -70,18 +76,18 @@
  "> > some\n"
  "> > internal Synopsys documentation which might shed a light. Or maybe I\n"
  "> > missed something else which should be considered.\n"
- "> Looks like this code based on idea, what if DMA ip-core doesn't have?\n"
+ "> Looks like this code based on idea, what if DMA ip-core doesn't have\302\240\n"
  "> LLP support it will not have LLP registers. It is not necessarily\n"
  "> true.\n"
  "\n"
  "Yep.\n"
  "\n"
- "Consider to review?\n"
+ "Consider to review\302\240\n"
  "http://www.spinics.net/lists/dmaengine/msg10682.html\n"
  "\n"
  "\n"
- "> > ?\n"
- "> Please add this code to read \"is_memcpy\" and \"is_nollp\" property?\n"
+ "> > \302\240\n"
+ "> Please add this code to read \"is_memcpy\" and \"is_nollp\" property\302\240\n"
  "> from device tree.\n"
  "> ----------------------------->8------------------------------\n"
  "> diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c\n"
@@ -89,23 +95,23 @@
  "> --- a/drivers/dma/dw/platform.c\n"
  "> +++ b/drivers/dma/dw/platform.c\n"
  "> @@ -129,6 +129,12 @@ dw_dma_parse_dt(struct platform_device *pdev)\n"
- "> ????????if (of_property_read_bool(np, \"is_private\"))\n"
- "> ????????????????pdata->is_private = true;\n"
- "> ?\n"
- "> +???????if (of_property_read_bool(np, \"is_memcpy\"))\n"
- "> +???????????????pdata->is_memcpy = true;\n"
+ "> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (of_property_read_bool(np, \"is_private\"))\n"
+ "> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240pdata->is_private = true;\n"
+ "> \302\240\n"
+ "> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (of_property_read_bool(np, \"is_memcpy\"))\n"
+ "> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240pdata->is_memcpy = true;\n"
  "> +\n"
- "> +???????if (of_property_read_bool(np, \"is_nollp\"))\n"
- "> +???????????????pdata->is_nollp = true;\n"
+ "> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (of_property_read_bool(np, \"is_nollp\"))\n"
+ "> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240pdata->is_nollp = true;\n"
  "> +\n"
- "> ????????if (!of_property_read_u32(np, \"chan_allocation_order\", &tmp))\n"
- "> ????????????????pdata->chan_allocation_order = (unsigned char)tmp;\n"
+ "> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (!of_property_read_u32(np, \"chan_allocation_order\", &tmp))\n"
+ "> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240pdata->chan_allocation_order = (unsigned char)tmp;\n"
  "\n"
  "Please, make this as a patch and submit either separately, or with your\n"
  "series mentioning that it has a dependency to my 8250 LPSS series.\n"
  "\n"
  "-- \n"
- "Andy Shevchenko <andriy.shevchenko at linux.intel.com>\n"
+ "Andy Shevchenko <andriy.shevchenko@linux.intel.com>\n"
  Intel Finland Oy
 
-a717c564d6dff94e0f32c0981321de89ab0dbf5476801c1641dbc0395904df00
+67060993f1cd8402bb9ac0bc9ca55f3c2289214cd12becdc0bd365629fac7d06

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