diff for duplicates of <1472252234.13245.28.camel@buserror.net> diff --git a/a/1.txt b/N1/1.txt index db5e07e..9b06bc2 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,18 +1,18 @@ On Fri, 2016-08-26 at 15:57 +0530, Bhaskar Upadhaya wrote: -> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> +> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org> > --- -> ?.../devicetree/bindings/crypto/fsl-sec5.txt????????| 153 +> .../devicetree/bindings/crypto/fsl-sec5.txt | 153 > +++++++++++++++++++++ -> ?1 file changed, 153 insertions(+) -> ?create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec5.txt +> 1 file changed, 153 insertions(+) +> create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec5.txt -Again, the subject should explain what you're adding, not why. ?You're adding +Again, the subject should explain what you're adding, not why. You're adding a sec5 binding, not an LS1012A binding. Why aren't the crypto maintainers/list CCed? -Why do we need a separate binding document for each SEC version? ?What is -different from the sec4 binding or the sec6 binding? ?Especially given that +Why do we need a separate binding document for each SEC version? What is +different from the sec4 binding or the sec6 binding? Especially given that the example claims compatibility with sec4? > diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec5.txt @@ -25,60 +25,60 @@ the example claims compatibility with sec4? > +SEC 5 is Freescale's Cryptographic Accelerator and Assurance Module (CAAM). > +Currently Freescale arm chip LS1012A is embedded with SEC 5. > +SEC 5 device tree binding include: -> +???-SEC 5 Node -> +???-Job Ring Node -> +???-Full Example +> + -SEC 5 Node +> + -Job Ring Node +> + -Full Example > + > +===================================================================== > +SEC 5 Node > + > +Description > + -> +????Node defines the base address of the SEC 5 block. -> +????This block specifies the address range of all global -> +????configuration registers for the SEC 5 block. -> +????For example, In LS1012A, we could see three SEC 5 node. +> + Node defines the base address of the SEC 5 block. +> + This block specifies the address range of all global +> + configuration registers for the SEC 5 block. +> + For example, In LS1012A, we could see three SEC 5 node. > + > +PROPERTIES > + -> +???- compatible -> +??????Usage: required -> +??????Value type: <string> -> +??????Definition: Must include "fsl,sec-v5.4". +> + - compatible +> + Usage: required +> + Value type: <string> +> + Definition: Must include "fsl,sec-v5.4". There was no v5.x prior to v5.4? -> +???- fsl,sec-era -> +??????Usage: optional -> +??????Value type: <u32> -> +??????Definition: A standard property. Define the 'ERA' of the SEC -> +??????????device. +> + - fsl,sec-era +> + Usage: optional +> + Value type: <u32> +> + Definition: A standard property. Define the 'ERA' of the SEC +> + device. This is not "a standard property". -> +???- reg -> +??????Usage: required -> +??????Value type: <prop-encoded-array> -> +??????Definition: A standard property.??Specifies the physical -> +??????????address and length of the SEC 5 configuration registers. +> + - reg +> + Usage: required +> + Value type: <prop-encoded-array> +> + Definition: A standard property. Specifies the physical +> + address and length of the SEC 5 configuration registers. Whether this property expresses the raw physical address depends on the ranges -of the parent node. ?Just say that there's one reg resource which is the SEC +of the parent node. Just say that there's one reg resource which is the SEC configuration registers. > + -> +???- ranges -> +???????Usage: required -> +???????Value type: <prop-encoded-array> -> +???????Definition: A standard property.??Specifies the physical address -> +???????????range of the SEC 5.0 register space (-SNVS not included).??A -> +???????????triplet that includes the child address, parent address, & -> +???????????length. - -Likewise with the talk about "physical address". ?It's also not required that +> + - ranges +> + Usage: required +> + Value type: <prop-encoded-array> +> + Definition: A standard property. Specifies the physical address +> + range of the SEC 5.0 register space (-SNVS not included). A +> + triplet that includes the child address, parent address, & +> + length. + +Likewise with the talk about "physical address". It's also not required that it contain such a triplet -- it could theoretically be an empty ranges -property, or there could be multiple translations. ?Bindings shouldn't try to -(poorly) repeat the definition of standard properties. ?They should specify +property, or there could be multiple translations. Bindings shouldn't try to +(poorly) repeat the definition of standard properties. They should specify information that is specific to this binding. The only thing worth mentioning here about ranges is if the driver will expect @@ -88,8 +88,8 @@ a particular translation independently of whether a child reg is using it. > +Full Example > + > +Since some chips may contain more than one SEC, the dtsi contains -> +only the node contents, not the node itself.??A chip using the SEC -> +should include the dtsi inside each SEC node.??Example: +> +only the node contents, not the node itself. A chip using the SEC +> +should include the dtsi inside each SEC node. Example: Bindings generally describe what the OS expects to see, not the details of the dtsi structure. @@ -102,28 +102,28 @@ dtsi structure. > + #address-cells = <1>; > + #size-cells = <1>; > + -> + sec_jr0: jr at 10000 { +> + sec_jr0: jr@10000 { > + compatible = "fsl,sec-v5.4-job-ring", > + "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x10000 0x10000>; > + interrupts = <0 71 0x4>; > + }; -> + sec_jr1: jr at 20000 { +> + sec_jr1: jr@20000 { > + compatible = "fsl,sec-v5.4-job-ring", > + "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x20000 0x10000>; > + interrupts = <0 72 0x4>; > + }; -> + sec_jr2: jr at 30000 { +> + sec_jr2: jr@30000 { > + compatible = "fsl,sec-v5.4-job-ring", > + "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x30000 0x10000>; > + interrupts = <0 73 0x4>; > + }; -> + sec_jr3: jr at 40000 { +> + sec_jr3: jr@40000 { > + compatible = "fsl,sec-v5.4-job-ring", > + "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; @@ -134,3 +134,8 @@ dtsi structure. This is terrible whitespace. -Scott + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 2e65699..4f9182e 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,26 +1,31 @@ "ref\01472207269-18499-1-git-send-email-Bhaskar.Upadhaya@nxp.com\0" "ref\01472207269-18499-10-git-send-email-Bhaskar.Upadhaya@nxp.com\0" - "From\0oss@buserror.net (Scott Wood)\0" - "Subject\0[PATCH 10/10] dt-bindings: sec: Update bindings for LS1012A\0" + "ref\01472207269-18499-10-git-send-email-Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org\0" + "From\0Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>\0" + "Subject\0Re: [PATCH 10/10] dt-bindings: sec: Update bindings for LS1012A\0" "Date\0Fri, 26 Aug 2016 17:57:14 -0500\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org>" + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org\0" + "Cc\0stuart.yoder-3arQi8VN3Tc@public.gmane.org" + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "On Fri, 2016-08-26 at 15:57 +0530, Bhaskar Upadhaya wrote:\n" - "> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>\n" + "> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org>\n" "> ---\n" - "> ?.../devicetree/bindings/crypto/fsl-sec5.txt????????| 153\n" + "> \302\240.../devicetree/bindings/crypto/fsl-sec5.txt\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 153\n" "> +++++++++++++++++++++\n" - "> ?1 file changed, 153 insertions(+)\n" - "> ?create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec5.txt\n" + "> \302\2401 file changed, 153 insertions(+)\n" + "> \302\240create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec5.txt\n" "\n" - "Again, the subject should explain what you're adding, not why. ?You're adding\n" + "Again, the subject should explain what you're adding, not why. \302\240You're adding\n" "a sec5 binding, not an LS1012A binding.\n" "\n" "Why aren't the crypto maintainers/list CCed?\n" "\n" - "Why do we need a separate binding document for each SEC version? ?What is\n" - "different from the sec4 binding or the sec6 binding? ?Especially given that\n" + "Why do we need a separate binding document for each SEC version? \302\240What is\n" + "different from the sec4 binding or the sec6 binding? \302\240Especially given that\n" "the example claims compatibility with sec4?\n" "\n" "> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec5.txt\n" @@ -33,60 +38,60 @@ "> +SEC 5 is Freescale's Cryptographic Accelerator and Assurance Module (CAAM).\n" "> +Currently Freescale arm chip LS1012A is embedded with SEC 5.\n" "> +SEC 5 device tree binding include:\n" - "> +???-SEC 5 Node\n" - "> +???-Job Ring Node\n" - "> +???-Full Example\n" + "> +\302\240\302\240\302\240-SEC 5 Node\n" + "> +\302\240\302\240\302\240-Job Ring Node\n" + "> +\302\240\302\240\302\240-Full Example\n" "> +\n" "> +=====================================================================\n" "> +SEC 5 Node\n" "> +\n" "> +Description\n" "> +\n" - "> +????Node defines the base address of the SEC 5 block.\n" - "> +????This block specifies the address range of all global\n" - "> +????configuration registers for the SEC 5 block.\n" - "> +????For example, In LS1012A, we could see three SEC 5 node.\n" + "> +\302\240\302\240\302\240\302\240Node defines the base address of the SEC 5 block.\n" + "> +\302\240\302\240\302\240\302\240This block specifies the address range of all global\n" + "> +\302\240\302\240\302\240\302\240configuration registers for the SEC 5 block.\n" + "> +\302\240\302\240\302\240\302\240For example, In LS1012A, we could see three SEC 5 node.\n" "> +\n" "> +PROPERTIES\n" "> +\n" - "> +???- compatible\n" - "> +??????Usage: required\n" - "> +??????Value type: <string>\n" - "> +??????Definition: Must include \"fsl,sec-v5.4\".\n" + "> +\302\240\302\240\302\240- compatible\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240Usage: required\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240Value type: <string>\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240Definition: Must include \"fsl,sec-v5.4\".\n" "\n" "There was no v5.x prior to v5.4?\n" "\n" - "> +???- fsl,sec-era\n" - "> +??????Usage: optional\n" - "> +??????Value type: <u32>\n" - "> +??????Definition: A standard property. Define the 'ERA' of the SEC\n" - "> +??????????device.\n" + "> +\302\240\302\240\302\240- fsl,sec-era\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240Usage: optional\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240Value type: <u32>\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240Definition: A standard property. Define the 'ERA' of the SEC\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240device.\n" "\n" "This is not \"a standard property\".\n" "\n" - "> +???- reg\n" - "> +??????Usage: required\n" - "> +??????Value type: <prop-encoded-array>\n" - "> +??????Definition: A standard property.??Specifies the physical\n" - "> +??????????address and length of the SEC 5 configuration registers.\n" + "> +\302\240\302\240\302\240- reg\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240Usage: required\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240Value type: <prop-encoded-array>\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240Definition: A standard property.\302\240\302\240Specifies the physical\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240address and length of the SEC 5 configuration registers.\n" "\n" "Whether this property expresses the raw physical address depends on the ranges\n" - "of the parent node. ?Just say that there's one reg resource which is the SEC\n" + "of the parent node. \302\240Just say that there's one reg resource which is the SEC\n" "configuration registers.\n" "\n" "> +\n" - "> +???- ranges\n" - "> +???????Usage: required\n" - "> +???????Value type: <prop-encoded-array>\n" - "> +???????Definition: A standard property.??Specifies the physical address\n" - "> +???????????range of the SEC 5.0 register space (-SNVS not included).??A\n" - "> +???????????triplet that includes the child address, parent address, &\n" - "> +???????????length.\n" - "\n" - "Likewise with the talk about \"physical address\". ?It's also not required that\n" + "> +\302\240\302\240\302\240- ranges\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240Usage: required\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240Value type: <prop-encoded-array>\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240Definition: A standard property.\302\240\302\240Specifies the physical address\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240range of the SEC 5.0 register space (-SNVS not included).\302\240\302\240A\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240triplet that includes the child address, parent address, &\n" + "> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240length.\n" + "\n" + "Likewise with the talk about \"physical address\". \302\240It's also not required that\n" "it contain such a triplet -- it could theoretically be an empty ranges\n" - "property, or there could be multiple translations. ?Bindings shouldn't try to\n" - "(poorly) repeat the definition of standard properties. ?They should specify\n" + "property, or there could be multiple translations. \302\240Bindings shouldn't try to\n" + "(poorly) repeat the definition of standard properties. \302\240They should specify\n" "information that is specific to this binding.\n" "\n" "The only thing worth mentioning here about ranges is if the driver will expect\n" @@ -96,8 +101,8 @@ "> +Full Example\n" "> +\n" "> +Since some chips may contain more than one SEC, the dtsi contains\n" - "> +only the node contents, not the node itself.??A chip using the SEC\n" - "> +should include the dtsi inside each SEC node.??Example:\n" + "> +only the node contents, not the node itself.\302\240\302\240A chip using the SEC\n" + "> +should include the dtsi inside each SEC node.\302\240\302\240Example:\n" "\n" "Bindings generally describe what the OS expects to see, not the details of the\n" "dtsi structure.\n" @@ -110,28 +115,28 @@ "> +\t#address-cells = <1>;\n" "> +\t#size-cells = <1>;\n" "> +\n" - "> +\tsec_jr0: jr at 10000 {\n" + "> +\tsec_jr0: jr@10000 {\n" "> +\t\tcompatible = \"fsl,sec-v5.4-job-ring\",\n" "> +\t\t\t\"fsl,sec-v5.0-job-ring\",\n" "> +\t\t\t\"fsl,sec-v4.0-job-ring\";\n" "> +\t\t\treg = <0x10000 0x10000>;\n" "> +\t\t\tinterrupts = <0 71 0x4>;\n" "> +\t};\n" - "> +\tsec_jr1: jr at 20000 {\n" + "> +\tsec_jr1: jr@20000 {\n" "> +\t\tcompatible = \"fsl,sec-v5.4-job-ring\",\n" "> +\t\t\t\"fsl,sec-v5.0-job-ring\",\n" "> +\t\t\t\"fsl,sec-v4.0-job-ring\";\n" "> +\t\t\treg = <0x20000 0x10000>;\n" "> +\t\t\tinterrupts = <0 72 0x4>;\n" "> +\t};\n" - "> +\tsec_jr2: jr at 30000 {\n" + "> +\tsec_jr2: jr@30000 {\n" "> +\t\tcompatible = \"fsl,sec-v5.4-job-ring\",\n" "> +\t\t\t\"fsl,sec-v5.0-job-ring\",\n" "> +\t\t\t\"fsl,sec-v4.0-job-ring\";\n" "> +\t\t\treg = <0x30000 0x10000>;\n" "> +\t\t\tinterrupts = <0 73 0x4>;\n" "> +\t};\n" - "> +\tsec_jr3: jr at 40000 {\n" + "> +\tsec_jr3: jr@40000 {\n" "> +\t\tcompatible = \"fsl,sec-v5.4-job-ring\",\n" "> +\t\t\t\"fsl,sec-v5.0-job-ring\",\n" "> +\t\t\t\"fsl,sec-v4.0-job-ring\";\n" @@ -141,6 +146,11 @@ "\n" "This is terrible whitespace.\n" "\n" - -Scott + "-Scott\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -90c9b39e8debef34bb64b95a193a97125887471ddcb99227866d6cf1f00cee0a +f2c7b50e75d41faeadc658d8e93cc7cdb91a74a4b0cd2f84459c66b4b3004a68
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