diff for duplicates of <1472569333.5703.24.camel@toradex.com>

diff --git a/a/1.txt b/N1/1.txt
index 704756d..b7d69c4 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,114 +1,202 @@
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+On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote:
+> From: Mirza Krak <mirza.krak@gmail.com>
+> 
+> Document the devicetree bindings for the Generic Memory Interface
+> (GMI)
+> bus driver found on Tegra SOCs.
+> 
+> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
+> ---
+> Changes in v2:
+> - Updated examples and some information based on comments from Jon
+> Hunter.
+> 
+>  .../devicetree/bindings/bus/nvidia,tegra20-gmi.txt | 132
+> +++++++++++++++++++++
+>  1 file changed, 132 insertions(+)
+>  create mode 100644
+> Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
+> 
+> diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-
+> gmi.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-
+> gmi.txt
+> new file mode 100644
+> index 0000000..8c1e15f
+> --- /dev/null
+> +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
+> @@ -0,0 +1,132 @@
+> +Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
+> +
+> +The Generic Memory Interface bus enables memory transfers between
+> internal and
+> +external memory. Can be used to attach various high speed devices
+> such as
+> +synchronous/asynchronous NOR, FPGA, UARTS and more.
+> +
+> +The actual devices are instantiated from the child nodes of a GMI
+> node.
+> +
+> +Required properties:
+> + - compatible : Should contain one of the following:
+> +        For Tegra20 must contain "nvidia,tegra20-gmi".
+> +        For Tegra30 must contain "nvidia,tegra30-gmi".
+> + - reg: Should contain GMI controller registers location and length.
+> + - clocks: Must contain an entry for each entry in clock-names.
+> + - clock-names: Must include the following entries: "gmi"
+> + - resets : Must contain an entry for each entry in reset-names.
+> + - reset-names : Must include the following entries: "gmi"
+> + - #address-cells: The number of cells used to represent physical
+> base
+> +   addresses in the GMI address space. Should be 1.
+> + - #size-cells: The number of cells used to represent the size of an
+> address
+> +   range in the GMI address space. Should be 1.
+> + - ranges: Must be set up to reflect the memory layout with three
+> integer values
+> +   for each chip-select line in use (only one entry is supported,
+> see below
+> +   comments):
+> +   <cs-number> <physical address of mapping> <size>
+> +
+> +Note that the GMI controller does not have any internal chip-select
+> address
+> +decoding, because of that chip-selects either need to be managed via
+> software
+> +or by employing external chip-select decoding logic.
+> +
+> +If external chip-select logic is used to support multiple devices it
+> is assumed
+> +that the devices use the same timing and so are probably the same
+> type. It also
+> +assumes that they can fit in the 256MB address range. In this case
+> only one
+> +child device is supported which represents the active chip-select
+> line, see
+> +examples for more insight.
+> +
+> +Required child cs node properties:
+> + - reg: First entry should contain the active chip-select number
+> +
+> +Optional child cs node properties:
+> +
+> + - nvidia,snor-data-width-32bit: Use 32bit data-bus, default is
+> 16bit.
+> + - nvidia,snor-mux-mode: Enable address/data MUX mode.
+> + - nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle
+> before data.
+> +   If omitted it will be asserted with data.
+> + - nvidia,snor-rdy-inv: RDY signal is active high
+> + - nvidia,snor-adv-inv: ADV signal is active high
+> + - nvidia,snor-oe-inv: WE/OE signal is active high
+> + - nvidia,snor-cs-inv: CS signal is active high
+> +
+> +  Note that there is some special handling for the timing values.
+> +  From Tegra TRM:
+> +  Programming 0 means 1 clock cycle: actual cycle = programmed cycle
+> + 1
+> +
+> + - nvidia,snor-muxed-width: Number of cycles MUX address/data
+> asserted on the
+> +   bus. Valid values are 0-15, default is 1
+> + - nvidia,snor-hold-width: Number of cycles CE stays asserted after
+> the
+> +   de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N
+> +   (in case of MASTER Request). Valid values are 0-15, default is 1
+> + - nvidia,snor-adv-width: Number of cycles during which ADV stays
+> asserted.
+> +   Valid values are 0-15, default is 1.
+> + - nvidia,snor-ce-width: Number of cycles before CE is asserted.
+> +   Valid values are 0-15, default is 4
+> + - nvidia,snor-we-width: Number of cycles during which WE stays
+> asserted.
+> +   Valid values are 0-15, default is 1
+> + - nvidia,snor-oe-width: Number of cycles during which OE stays
+> asserted.
+> +   Valid values are 0-255, default is 1
+> + - nvidia,snor-wait-width: Number of cycles before READY is
+> asserted.
+> +   Valid values are 0-255, default is 3
+> +
+> +Example with two SJA1000 CAN controllers connected to the GMI bus.
+> We wrap the
+> +controllers with a simple-bus node since they are all connected to
+> the same
+> +chip-select (CS4), in this example external address decoding is
+> provided:
+> +
+> +gmi@70090000 {
+
+It's actually 70009000.
+
+> +	compatible = "nvidia,tegra20-gmi";
+> +	reg = <0x70009000 0x1000>;
+> +	#address-cells = <1>;
+> +	#size-cells = <1>;
+> +	clocks = <&tegra_car TEGRA20_CLK_NOR>;
+> +	clock-names = "gmi";
+> +	resets = <&tegra_car 42>;
+> +	reset-names = "gmi";
+> +	ranges = <4 0x48000000 0x7ffffff>;
+> +
+> +	status = "disabled";
+
+I guess in an example one could even set this to okay.
+
+> +
+> +	bus@4 {
+> +		compatible = "simple-bus";
+> +		reg = <4>;
+> +		#address-cells = <1>;
+> +		#size-cells = <1>;
+> +		ranges = <0 4 0x40100>;
+> +
+> +		nvidia,snor-mux-mode;
+> +		nvidia,snor-adv-inv;
+> +
+> +		can@0 {
+> +			reg = <0 0x100>;
+> +			...
+> +		};
+> +
+> +		can@40000 {
+> +			reg = <0x40000 0x100>;
+> +			...
+> +		};
+> +	};
+> +};
+> +
+> +Example with one SJA1000 CAN controller connected to the GMI bus
+> +on CS4:
+> +
+> +gmi@70090000 {
+
+Same here.
+
+> +	compatible = "nvidia,tegra20-gmi";
+> +	reg = <0x70009000 0x1000>;
+> +	#address-cells = <1>;
+> +	#size-cells = <1>;
+> +	clocks = <&tegra_car TEGRA20_CLK_NOR>;
+> +	clock-names = "gmi";
+> +	resets = <&tegra_car 42>;
+> +	reset-names = "gmi";
+> +	ranges = <4 0x48000000 0x7ffffff>;
+> +
+> +	status = "disabled";
+
+Same here.
+
+> +
+> +	can@4 {
+> +		reg = <4 0x100>;
+> +		...
+> +		nvidia,snor-mux-mode;
+> +		nvidia,snor-adv-inv;
+> +	};
+> +};
+> --
+> 2.1.4
+_______________________________________________
+linux-arm-kernel mailing list
+linux-arm-kernel@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/a/content_digest b/N1/content_digest
index 781e5ab..7a95669 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -7,134 +7,222 @@
   mirza.krak@gmail.com <mirza.krak@gmail.com>
   swarren@wwwdotorg.org <swarren@wwwdotorg.org>
  " thierry.reding@gmail.com <thierry.reding@gmail.com>\0"
- "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>"
-  robh+dt@kernel.org <robh+dt@kernel.org>
-  mturquette@baylibre.com <mturquette@baylibre.com>
-  pgaikwad@nvidia.com <pgaikwad@nvidia.com>
-  linux@armlinux.org.uk <linux@armlinux.org.uk>
+ "Cc\0mark.rutland@arm.com <mark.rutland@arm.com>"
   devicetree@vger.kernel.org <devicetree@vger.kernel.org>
+  pgaikwad@nvidia.com <pgaikwad@nvidia.com>
+  linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>
   gnurou@gmail.com <gnurou@gmail.com>
-  mark.rutland@arm.com <mark.rutland@arm.com>
-  linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>
-  pdeschrijver@nvidia.com <pdeschrijver@nvidia.com>
+  mturquette@baylibre.com <mturquette@baylibre.com>
   sboyd@codeaurora.org <sboyd@codeaurora.org>
+  linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>
+  linux@armlinux.org.uk <linux@armlinux.org.uk>
+  robh+dt@kernel.org <robh+dt@kernel.org>
   linux-tegra@vger.kernel.org <linux-tegra@vger.kernel.org>
- " linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>\0"
+  pdeschrijver@nvidia.com <pdeschrijver@nvidia.com>
+ " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0"
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+ "On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote:\n"
+ "> From: Mirza Krak <mirza.krak@gmail.com>\n"
+ "> \n"
+ "> Document the devicetree bindings for the Generic Memory Interface\n"
+ "> (GMI)\n"
+ "> bus driver found on Tegra SOCs.\n"
+ "> \n"
+ "> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>\n"
+ "> ---\n"
+ "> Changes in v2:\n"
+ "> - Updated examples and some information based on comments from Jon\n"
+ "> Hunter.\n"
+ "> \n"
+ "> \302\240.../devicetree/bindings/bus/nvidia,tegra20-gmi.txt | 132\n"
+ "> +++++++++++++++++++++\n"
+ "> \302\2401 file changed, 132 insertions(+)\n"
+ "> \302\240create mode 100644\n"
+ "> Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt\n"
+ "> \n"
+ "> diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-\n"
+ "> gmi.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-\n"
+ "> gmi.txt\n"
+ "> new file mode 100644\n"
+ "> index 0000000..8c1e15f\n"
+ "> --- /dev/null\n"
+ "> +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt\n"
+ "> @@ -0,0 +1,132 @@\n"
+ "> +Device tree bindings for NVIDIA Tegra Generic Memory Interface bus\n"
+ "> +\n"
+ "> +The Generic Memory Interface bus enables memory transfers between\n"
+ "> internal and\n"
+ "> +external memory. Can be used to attach various high speed devices\n"
+ "> such as\n"
+ "> +synchronous/asynchronous NOR, FPGA, UARTS and more.\n"
+ "> +\n"
+ "> +The actual devices are instantiated from the child nodes of a GMI\n"
+ "> node.\n"
+ "> +\n"
+ "> +Required properties:\n"
+ "> + - compatible : Should contain one of the following:\n"
+ "> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240For Tegra20 must contain \"nvidia,tegra20-gmi\".\n"
+ "> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240For Tegra30 must contain \"nvidia,tegra30-gmi\".\n"
+ "> + - reg: Should contain GMI controller registers location and length.\n"
+ "> + - clocks: Must contain an entry for each entry in clock-names.\n"
+ "> + - clock-names: Must include the following entries: \"gmi\"\n"
+ "> + - resets : Must contain an entry for each entry in reset-names.\n"
+ "> + - reset-names : Must include the following entries: \"gmi\"\n"
+ "> + - #address-cells: The number of cells used to represent physical\n"
+ "> base\n"
+ "> +\302\240\302\240\302\240addresses in the GMI address space. Should be 1.\n"
+ "> + - #size-cells: The number of cells used to represent the size of an\n"
+ "> address\n"
+ "> +\302\240\302\240\302\240range in the GMI address space. Should be 1.\n"
+ "> + - ranges: Must be set up to reflect the memory layout with three\n"
+ "> integer values\n"
+ "> +\302\240\302\240\302\240for each chip-select line in use (only one entry is supported,\n"
+ "> see below\n"
+ "> +\302\240\302\240\302\240comments):\n"
+ "> +\302\240\302\240\302\240<cs-number> <physical address of mapping> <size>\n"
+ "> +\n"
+ "> +Note that the GMI controller does not have any internal chip-select\n"
+ "> address\n"
+ "> +decoding, because of that chip-selects either need to be managed via\n"
+ "> software\n"
+ "> +or by employing external chip-select decoding logic.\n"
+ "> +\n"
+ "> +If external chip-select logic is used to support multiple devices it\n"
+ "> is assumed\n"
+ "> +that the devices use the same timing and so are probably the same\n"
+ "> type. It also\n"
+ "> +assumes that they can fit in the 256MB address range. In this case\n"
+ "> only one\n"
+ "> +child device is supported which represents the active chip-select\n"
+ "> line, see\n"
+ "> +examples for more insight.\n"
+ "> +\n"
+ "> +Required child cs node properties:\n"
+ "> + - reg: First entry should contain the active chip-select number\n"
+ "> +\n"
+ "> +Optional child cs node properties:\n"
+ "> +\n"
+ "> + - nvidia,snor-data-width-32bit: Use 32bit data-bus, default is\n"
+ "> 16bit.\n"
+ "> + - nvidia,snor-mux-mode: Enable address/data MUX mode.\n"
+ "> + - nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle\n"
+ "> before data.\n"
+ "> +\302\240\302\240\302\240If omitted it will be asserted with data.\n"
+ "> + - nvidia,snor-rdy-inv: RDY signal is active high\n"
+ "> + - nvidia,snor-adv-inv: ADV signal is active high\n"
+ "> + - nvidia,snor-oe-inv: WE/OE signal is active high\n"
+ "> + - nvidia,snor-cs-inv: CS signal is active high\n"
+ "> +\n"
+ "> +\302\240\302\240Note that there is some special handling for the timing values.\n"
+ "> +\302\240\302\240From Tegra TRM:\n"
+ "> +\302\240\302\240Programming 0 means 1 clock cycle: actual cycle = programmed cycle\n"
+ "> + 1\n"
+ "> +\n"
+ "> + - nvidia,snor-muxed-width: Number of cycles MUX address/data\n"
+ "> asserted on the\n"
+ "> +\302\240\302\240\302\240bus. Valid values are 0-15, default is 1\n"
+ "> + - nvidia,snor-hold-width: Number of cycles CE stays asserted after\n"
+ "> the\n"
+ "> +\302\240\302\240\302\240de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N\n"
+ "> +\302\240\302\240\302\240(in case of MASTER Request). Valid values are 0-15, default is 1\n"
+ "> + - nvidia,snor-adv-width: Number of cycles during which ADV stays\n"
+ "> asserted.\n"
+ "> +\302\240\302\240\302\240Valid values are 0-15, default is 1.\n"
+ "> + - nvidia,snor-ce-width: Number of cycles before CE is asserted.\n"
+ "> +\302\240\302\240\302\240Valid values are 0-15, default is 4\n"
+ "> + - nvidia,snor-we-width: Number of cycles during which WE stays\n"
+ "> asserted.\n"
+ "> +\302\240\302\240\302\240Valid values are 0-15, default is 1\n"
+ "> + - nvidia,snor-oe-width: Number of cycles during which OE stays\n"
+ "> asserted.\n"
+ "> +\302\240\302\240\302\240Valid values are 0-255, default is 1\n"
+ "> + - nvidia,snor-wait-width: Number of cycles before READY is\n"
+ "> asserted.\n"
+ "> +\302\240\302\240\302\240Valid values are 0-255, default is 3\n"
+ "> +\n"
+ "> +Example with two SJA1000 CAN controllers connected to the GMI bus.\n"
+ "> We wrap the\n"
+ "> +controllers with a simple-bus node since they are all connected to\n"
+ "> the same\n"
+ "> +chip-select (CS4), in this example external address decoding is\n"
+ "> provided:\n"
+ "> +\n"
+ "> +gmi@70090000 {\n"
+ "\n"
+ "It's actually 70009000.\n"
+ "\n"
+ "> +\tcompatible = \"nvidia,tegra20-gmi\";\n"
+ "> +\treg = <0x70009000 0x1000>;\n"
+ "> +\t#address-cells = <1>;\n"
+ "> +\t#size-cells = <1>;\n"
+ "> +\tclocks = <&tegra_car TEGRA20_CLK_NOR>;\n"
+ "> +\tclock-names = \"gmi\";\n"
+ "> +\tresets = <&tegra_car 42>;\n"
+ "> +\treset-names = \"gmi\";\n"
+ "> +\tranges = <4 0x48000000 0x7ffffff>;\n"
+ "> +\n"
+ "> +\tstatus = \"disabled\";\n"
+ "\n"
+ "I guess in an example one could even set this to okay.\n"
+ "\n"
+ "> +\n"
+ "> +\tbus@4 {\n"
+ "> +\t\tcompatible = \"simple-bus\";\n"
+ "> +\t\treg = <4>;\n"
+ "> +\t\t#address-cells = <1>;\n"
+ "> +\t\t#size-cells = <1>;\n"
+ "> +\t\tranges = <0 4 0x40100>;\n"
+ "> +\n"
+ "> +\t\tnvidia,snor-mux-mode;\n"
+ "> +\t\tnvidia,snor-adv-inv;\n"
+ "> +\n"
+ "> +\t\tcan@0 {\n"
+ "> +\t\t\treg = <0 0x100>;\n"
+ "> +\t\t\t...\n"
+ "> +\t\t};\n"
+ "> +\n"
+ "> +\t\tcan@40000 {\n"
+ "> +\t\t\treg = <0x40000 0x100>;\n"
+ "> +\t\t\t...\n"
+ "> +\t\t};\n"
+ "> +\t};\n"
+ "> +};\n"
+ "> +\n"
+ "> +Example with one SJA1000 CAN controller connected to the GMI bus\n"
+ "> +on CS4:\n"
+ "> +\n"
+ "> +gmi@70090000 {\n"
+ "\n"
+ "Same here.\n"
+ "\n"
+ "> +\tcompatible = \"nvidia,tegra20-gmi\";\n"
+ "> +\treg = <0x70009000 0x1000>;\n"
+ "> +\t#address-cells = <1>;\n"
+ "> +\t#size-cells = <1>;\n"
+ "> +\tclocks = <&tegra_car TEGRA20_CLK_NOR>;\n"
+ "> +\tclock-names = \"gmi\";\n"
+ "> +\tresets = <&tegra_car 42>;\n"
+ "> +\treset-names = \"gmi\";\n"
+ "> +\tranges = <4 0x48000000 0x7ffffff>;\n"
+ "> +\n"
+ "> +\tstatus = \"disabled\";\n"
+ "\n"
+ "Same here.\n"
+ "\n"
+ "> +\n"
+ "> +\tcan@4 {\n"
+ "> +\t\treg = <4 0x100>;\n"
+ "> +\t\t...\n"
+ "> +\t\tnvidia,snor-mux-mode;\n"
+ "> +\t\tnvidia,snor-adv-inv;\n"
+ "> +\t};\n"
+ "> +};\n"
+ "> --\n"
+ "> 2.1.4\n"
+ "_______________________________________________\n"
+ "linux-arm-kernel mailing list\n"
+ "linux-arm-kernel@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
 
-e80e60be58c895271755a1e67c11c6c15566a8b9b119a08acad3c0546592f4b1
+ad5095eaebb0c1e131d9fe376cae3c461cd7c6396f60318db83065c3999440f3
