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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Wed, 31 Aug 2016 11:06:53 +1000
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Subject: Re: [Qemu-devel] [PATCH 3/3] ppc/pnv: add a PowerNVCPUCore object
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To: David Gibson <david@gibson.dropbear.id.au>
Cc: =?ISO-8859-1?Q?C=E9dric?= Le Goater <clg@kaod.org>, qemu-ppc@nongnu.org, Alexander Graf <agraf@suse.de>, qemu-devel@nongnu.org

On Tue, 2016-08-30 at 02:28 -0400, David Gibson wrote:
> No.. the PIR itself is a cpu level construct (and we already have a
> place for that in the cpu state).=C2=A0 The DT id as such isn't, althou=
gh
> it happens to have the same value.=C2=A0 The fact it has the same value=
 is
> itself a machine type property.
>=20
> [Aside: removing dt_id from the cpu will require disentangling it from
> the kvm vcpu id]

On P8 and P9 the PIR of a thread is a chip property, as it encodes
the HW node, chip, core and thread ID (hint: it's not 0 based on P8,
well the core isn't).

So it has to match accordingly for things like core XSCOMs which we
want to start supporting some of.

It also has to match what's in the device-tree as a pretty standard
requirement of all powerpc device-trees.

Finally it also happen to be the target interrupt server on all known
implementations.

Cheers,
Ben.