diff for duplicates of <1472627744.31008.2.camel@toradex.com>

diff --git a/a/1.txt b/N1/1.txt
index 954d2b5..efc87e4 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,24 +1,45 @@
-T24gV2VkLCAyMDE2LTA4LTI0IGF0IDE1OjM3ICswMjAwLCBNaXJ6YSBLcmFrIHdyb3RlOg0KPiAN
-Cj4gRnJvbTogTWlyemEgS3JhayA8bWlyemEua3Jhay1SZTVKUUVlUXFlOEF2eHRpdU13eDN3QHB1
-YmxpYy5nbWFuZS5vcmc+DQo+IA0KPiBBZGQgVEVHUkEyMF9DTEtfTk9SIHRvIGluaXQgdGFiZWwg
-YW5kIHNldCBkZWZhdWx0IHJhdGUgdG8gOTIgTUh6DQo+IHdoaWNoDQo+IGlzIG1heCByYXRlLg0K
-DQp0YWJsZQ0KDQo+IA0KPiBTaWduZWQtb2ZmLWJ5OiBNaXJ6YSBLcmFrIDxtaXJ6YS5rcmFrLVJl
-NUpRRWVRcWU4QXZ4dGl1TXd4M3dAcHVibGljLmcNCj4gbWFuZS5vcmc+DQo+IC0tLQ0KPiBDaGFu
-Z2VzIGluIHYyOg0KPiAtIG5vIGNoYW5nZXMNCj4gDQo+IMKgZHJpdmVycy9jbGsvdGVncmEvY2xr
-LXRlZ3JhMjAuYyB8IDEgKw0KPiDCoDEgZmlsZSBjaGFuZ2VkLCAxIGluc2VydGlvbigrKQ0KPiAN
-Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvY2xrL3RlZ3JhL2Nsay10ZWdyYTIwLmMgYi9kcml2ZXJz
-L2Nsay90ZWdyYS9jbGstDQo+IHRlZ3JhMjAuYw0KPiBpbmRleCA4MzdlNWNiLi4xM2QzYjVhIDEw
-MDY0NA0KPiAtLS0gYS9kcml2ZXJzL2Nsay90ZWdyYS9jbGstdGVncmEyMC5jDQo+ICsrKyBiL2Ry
-aXZlcnMvY2xrL3RlZ3JhL2Nsay10ZWdyYTIwLmMNCj4gQEAgLTEwNDcsNiArMTA0Nyw3IEBAIHN0
-YXRpYyBzdHJ1Y3QgdGVncmFfY2xrX2luaXRfdGFibGUgaW5pdF90YWJsZVtdDQo+IF9faW5pdGRh
-dGEgPSB7DQo+IMKgCXsgVEVHUkEyMF9DTEtfU0RNTUMzLCBURUdSQTIwX0NMS19QTExfUCwgNDgw
-MDAwMDAsIDAgfSwNCj4gwqAJeyBURUdSQTIwX0NMS19TRE1NQzQsIFRFR1JBMjBfQ0xLX1BMTF9Q
-LCA0ODAwMDAwMCwgMCB9LA0KPiDCoAl7IFRFR1JBMjBfQ0xLX1NQSSwgVEVHUkEyMF9DTEtfUExM
-X1AsIDIwMDAwMDAwLCAwIH0sDQo+ICsJeyBURUdSQTIwX0NMS19OT1IsIFRFR1JBMjBfQ0xLX1BM
-TF9QLCA5MjAwMDAwMCwgMCB9LA0KDQpJJ20ganVzdCBjdXJpb3VzIHdoZXJlIHRoYXQgOTIgTUh6
-IGNhbWUgZnJvbS4gQWNjb3JkaW5nIHRvIHRoZSBUZWdyYSAyDQpJbnRlcmZhY2UgRGVzaWduIEd1
-aWRlIHVwIHRvIDEzMyBNSHogc2hvdWxkIGFjdHVhbGx5IGJlIHBvc3NpYmxlLg0KDQo+IA0KPiDC
-oAl7IFRFR1JBMjBfQ0xLX1NCQzEsIFRFR1JBMjBfQ0xLX1BMTF9QLCAxMDAwMDAwMDAsIDAgfSwN
-Cj4gwqAJeyBURUdSQTIwX0NMS19TQkMyLCBURUdSQTIwX0NMS19QTExfUCwgMTAwMDAwMDAwLCAw
-IH0sDQo+IMKgCXsgVEVHUkEyMF9DTEtfU0JDMywgVEVHUkEyMF9DTEtfUExMX1AsIDEwMDAwMDAw
-MCwgMCB9LA0KPiAtLQ0KPiAyLjEuNA==
+On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote:
+> 
+> From: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+> 
+> Add TEGRA20_CLK_NOR to init tabel and set default rate to 92 MHz
+> which
+> is max rate.
+
+table
+
+> 
+> Signed-off-by: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.g
+> mane.org>
+> ---
+> Changes in v2:
+> - no changes
+> 
+>  drivers/clk/tegra/clk-tegra20.c | 1 +
+>  1 file changed, 1 insertion(+)
+> 
+> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-
+> tegra20.c
+> index 837e5cb..13d3b5a 100644
+> --- a/drivers/clk/tegra/clk-tegra20.c
+> +++ b/drivers/clk/tegra/clk-tegra20.c
+> @@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[]
+> __initdata = {
+>  	{ TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
+>  	{ TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
+>  	{ TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
+> +	{ TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 92000000, 0 },
+
+I'm just curious where that 92 MHz came from. According to the Tegra 2
+Interface Design Guide up to 133 MHz should actually be possible.
+
+> 
+>  	{ TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
+>  	{ TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
+>  	{ TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
+> --
+> 2.1.4
+_______________________________________________
+linux-arm-kernel mailing list
+linux-arm-kernel@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/a/content_digest b/N1/content_digest
index b6b0a08..7771816 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -6,44 +6,65 @@
   mirza.krak@gmail.com <mirza.krak@gmail.com>
   swarren@wwwdotorg.org <swarren@wwwdotorg.org>
  " thierry.reding@gmail.com <thierry.reding@gmail.com>\0"
- "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>"
-  robh+dt@kernel.org <robh+dt@kernel.org>
-  mturquette@baylibre.com <mturquette@baylibre.com>
-  pgaikwad@nvidia.com <pgaikwad@nvidia.com>
-  linux@armlinux.org.uk <linux@armlinux.org.uk>
+ "Cc\0mark.rutland@arm.com <mark.rutland@arm.com>"
   devicetree@vger.kernel.org <devicetree@vger.kernel.org>
+  pgaikwad@nvidia.com <pgaikwad@nvidia.com>
+  linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>
   gnurou@gmail.com <gnurou@gmail.com>
-  mark.rutland@arm.com <mark.rutland@arm.com>
-  linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>
-  pdeschrijver@nvidia.com <pdeschrijver@nvidia.com>
+  mturquette@baylibre.com <mturquette@baylibre.com>
   sboyd@codeaurora.org <sboyd@codeaurora.org>
+  linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>
+  linux@armlinux.org.uk <linux@armlinux.org.uk>
+  robh+dt@kernel.org <robh+dt@kernel.org>
   linux-tegra@vger.kernel.org <linux-tegra@vger.kernel.org>
- " linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>\0"
+  pdeschrijver@nvidia.com <pdeschrijver@nvidia.com>
+ " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0"
  "\00:1\0"
  "b\0"
- "T24gV2VkLCAyMDE2LTA4LTI0IGF0IDE1OjM3ICswMjAwLCBNaXJ6YSBLcmFrIHdyb3RlOg0KPiAN\n"
- "Cj4gRnJvbTogTWlyemEgS3JhayA8bWlyemEua3Jhay1SZTVKUUVlUXFlOEF2eHRpdU13eDN3QHB1\n"
- "YmxpYy5nbWFuZS5vcmc+DQo+IA0KPiBBZGQgVEVHUkEyMF9DTEtfTk9SIHRvIGluaXQgdGFiZWwg\n"
- "YW5kIHNldCBkZWZhdWx0IHJhdGUgdG8gOTIgTUh6DQo+IHdoaWNoDQo+IGlzIG1heCByYXRlLg0K\n"
- "DQp0YWJsZQ0KDQo+IA0KPiBTaWduZWQtb2ZmLWJ5OiBNaXJ6YSBLcmFrIDxtaXJ6YS5rcmFrLVJl\n"
- "NUpRRWVRcWU4QXZ4dGl1TXd4M3dAcHVibGljLmcNCj4gbWFuZS5vcmc+DQo+IC0tLQ0KPiBDaGFu\n"
- "Z2VzIGluIHYyOg0KPiAtIG5vIGNoYW5nZXMNCj4gDQo+IMKgZHJpdmVycy9jbGsvdGVncmEvY2xr\n"
- "LXRlZ3JhMjAuYyB8IDEgKw0KPiDCoDEgZmlsZSBjaGFuZ2VkLCAxIGluc2VydGlvbigrKQ0KPiAN\n"
- "Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvY2xrL3RlZ3JhL2Nsay10ZWdyYTIwLmMgYi9kcml2ZXJz\n"
- "L2Nsay90ZWdyYS9jbGstDQo+IHRlZ3JhMjAuYw0KPiBpbmRleCA4MzdlNWNiLi4xM2QzYjVhIDEw\n"
- "MDY0NA0KPiAtLS0gYS9kcml2ZXJzL2Nsay90ZWdyYS9jbGstdGVncmEyMC5jDQo+ICsrKyBiL2Ry\n"
- "aXZlcnMvY2xrL3RlZ3JhL2Nsay10ZWdyYTIwLmMNCj4gQEAgLTEwNDcsNiArMTA0Nyw3IEBAIHN0\n"
- "YXRpYyBzdHJ1Y3QgdGVncmFfY2xrX2luaXRfdGFibGUgaW5pdF90YWJsZVtdDQo+IF9faW5pdGRh\n"
- "dGEgPSB7DQo+IMKgCXsgVEVHUkEyMF9DTEtfU0RNTUMzLCBURUdSQTIwX0NMS19QTExfUCwgNDgw\n"
- "MDAwMDAsIDAgfSwNCj4gwqAJeyBURUdSQTIwX0NMS19TRE1NQzQsIFRFR1JBMjBfQ0xLX1BMTF9Q\n"
- "LCA0ODAwMDAwMCwgMCB9LA0KPiDCoAl7IFRFR1JBMjBfQ0xLX1NQSSwgVEVHUkEyMF9DTEtfUExM\n"
- "X1AsIDIwMDAwMDAwLCAwIH0sDQo+ICsJeyBURUdSQTIwX0NMS19OT1IsIFRFR1JBMjBfQ0xLX1BM\n"
- "TF9QLCA5MjAwMDAwMCwgMCB9LA0KDQpJJ20ganVzdCBjdXJpb3VzIHdoZXJlIHRoYXQgOTIgTUh6\n"
- "IGNhbWUgZnJvbS4gQWNjb3JkaW5nIHRvIHRoZSBUZWdyYSAyDQpJbnRlcmZhY2UgRGVzaWduIEd1\n"
- "aWRlIHVwIHRvIDEzMyBNSHogc2hvdWxkIGFjdHVhbGx5IGJlIHBvc3NpYmxlLg0KDQo+IA0KPiDC\n"
- "oAl7IFRFR1JBMjBfQ0xLX1NCQzEsIFRFR1JBMjBfQ0xLX1BMTF9QLCAxMDAwMDAwMDAsIDAgfSwN\n"
- "Cj4gwqAJeyBURUdSQTIwX0NMS19TQkMyLCBURUdSQTIwX0NMS19QTExfUCwgMTAwMDAwMDAwLCAw\n"
- "IH0sDQo+IMKgCXsgVEVHUkEyMF9DTEtfU0JDMywgVEVHUkEyMF9DTEtfUExMX1AsIDEwMDAwMDAw\n"
- MCwgMCB9LA0KPiAtLQ0KPiAyLjEuNA==
+ "On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote:\n"
+ "> \n"
+ "> From: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n"
+ "> \n"
+ "> Add TEGRA20_CLK_NOR to init tabel and set default rate to 92 MHz\n"
+ "> which\n"
+ "> is max rate.\n"
+ "\n"
+ "table\n"
+ "\n"
+ "> \n"
+ "> Signed-off-by: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.g\n"
+ "> mane.org>\n"
+ "> ---\n"
+ "> Changes in v2:\n"
+ "> - no changes\n"
+ "> \n"
+ "> \302\240drivers/clk/tegra/clk-tegra20.c | 1 +\n"
+ "> \302\2401 file changed, 1 insertion(+)\n"
+ "> \n"
+ "> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-\n"
+ "> tegra20.c\n"
+ "> index 837e5cb..13d3b5a 100644\n"
+ "> --- a/drivers/clk/tegra/clk-tegra20.c\n"
+ "> +++ b/drivers/clk/tegra/clk-tegra20.c\n"
+ "> @@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[]\n"
+ "> __initdata = {\n"
+ "> \302\240\t{ TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },\n"
+ "> \302\240\t{ TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },\n"
+ "> \302\240\t{ TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },\n"
+ "> +\t{ TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 92000000, 0 },\n"
+ "\n"
+ "I'm just curious where that 92 MHz came from. According to the Tegra 2\n"
+ "Interface Design Guide up to 133 MHz should actually be possible.\n"
+ "\n"
+ "> \n"
+ "> \302\240\t{ TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },\n"
+ "> \302\240\t{ TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },\n"
+ "> \302\240\t{ TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },\n"
+ "> --\n"
+ "> 2.1.4\n"
+ "_______________________________________________\n"
+ "linux-arm-kernel mailing list\n"
+ "linux-arm-kernel@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
 
-dd934a44cb7e98e164ff2a7fc8f35f16f650ac23e71034af7e895aedc89271b2
+6c5d13b8bca1361ceed5a69a9f106dd2b917d5e212ef6b4d32984161bf7b96b4
