diff for duplicates of <1472642915.31008.32.camel@toradex.com> diff --git a/a/1.txt b/N1/1.txt index 1b98640..58e0462 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,24 +1,36 @@ -T24gV2VkLCAyMDE2LTA4LTMxIGF0IDExOjQ3ICswMjAwLCBNaXJ6YSBLcmFrIHdyb3RlOg0KPiBJ -J20ganVzdCBjdXJpb3VzIHdoZXJlIHRoYXQgOTIgTUh6IGNhbWUgZnJvbS4gQWNjb3JkaW5nIHRv -IHRoZQ0KPiA+IFRlZ3JhIDINCj4gPiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlIHVwIHRvIDEzMyBN -SHogc2hvdWxkIGFjdHVhbGx5IGJlIHBvc3NpYmxlLg0KPiBUaGUgbWF4aW11bSByYXRlcyBmb3Ig -Ym90aCBUMjAgYW5kIFQzMCBhcmUgdmFsdWVzIHRoYXQgYXJlIHNldCBhcw0KPiBtYXhpbXVtIGlu -IHRoZSBkb3duc3RyZWFtIEw0VCBrZXJuZWwuDQo+IA0KPiBJbiB0ZWdyYTJfY2xvY2tzLmM6DQo+ -IFBFUklQSF9DTEsoIm5vciIsICJ0ZWdyYS1ub3IiLCBOVUxMLCA0MiwgMHgxZDAsIDB4MzFFLCA5 -MjAwMDAwMCwNCj4gbXV4X3BsbHBfcGxsY19wbGxtX2Nsa20sIE1VWCB8IERJVl9VNzEpLCAvKiBy -ZXF1aXJlcyBtaW4gdm9sdGFnZSAqLw0KPiANCj4gQW5kIGluIHRlZ3JhM19jbG9ja3MuYw0KPiBQ -RVJJUEhfQ0xLKCJub3IiLCAidGVncmEtbm9yIiwgTlVMTCwgNDIsIDB4MWQwLCAxMjcwMDAwMDAs -DQo+IG11eF9wbGxwX3BsbGNfcGxsbV9jbGttLCBNVVggfCBESVZfVTcxKSwgLyogcmVxdWlyZXMg -bWluIHZvbHRhZ2UgKi8NCj4gDQo+IEkgbG9va2VkIHVwIHRoZSBjb21taXQgaW4gdGhlIGRvd25z -dHJlYW0ga2VybmVsIHRoYXQgYWRkZWQgdGhlICJub3IiDQo+IGNsb2NrLCBpdCBkb2VzIG5vdCBt -ZW50aW9uIHJlYXNvbiBiZWhpbmQgdGhlIG1heGltYWwgcmF0ZXMuIEF1dGhvcg0KPiB3YXMNCj4g -TWFub2ogQ2hvdXJhc2lhLCBhZGRlZCBoaW0gdG8gQ0MuDQoNCkxldCdzIHNlZSB3aGV0aGVyIHdl -IGRvIGdldCBhbnkgZmVlZGJhY2sgZnJvbSBoaW0uDQoNCk5vbmV0aGVsZXNzIGl0IG1heSBiZSBn -b29kIHRvIGFkZCB0aGlzIGluZm9ybWF0aW9uIHRvIHRoZSBjb21taXQNCm1lc3NhZ2Ugc28gc2hv -dWxkIHNvbWVib2R5IGV2ZXIgZmVlbCB0aGUgc2FtZSBjdXJpb3NpdHkgbGlrZSBJIGRpZCBoZQ0K -d291bGQgYXQgbGVhc3Qga25vdyB3aGVyZSBpdCBpbml0aWFsbHkgY2FtZSBmcm9tLg0KDQo+IEkg -YWN0dWFsbHkgZG8gbm90IGhhdmUgdGhlIFRlZ3JhMiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlLCBk -byBub3Qga25vdw0KPiBpZiBJIGNhbiBnZXQgYWNjZXNzIHRvIGl0Lg0KDQpJIGd1ZXNzIHRoYXQg -b25lIGlzIG9ubHkgYWNjZXNzaWJsZSB1bmRlciBOREEuIFdlIGNvdWxkIG9mIGNvdXJzZSB0cnkN -CnRvIGdldCBvbmUgaW4gcGxhY2UgZm9yIHlvdSBidXQgSSBjYW4ndCBwcm9taXNlIHlvdSBhbnl0 -aGluZy4NCg0KPiBCZXN0IFJlZ2FyZHMNCj4gTWlyemENCg0KVGhhbmtzLCBNaXJ6YQ== +On Wed, 2016-08-31 at 11:47 +0200, Mirza Krak wrote: +> I'm just curious where that 92 MHz came from. According to the +> > Tegra 2 +> > Interface Design Guide up to 133 MHz should actually be possible. +> The maximum rates for both T20 and T30 are values that are set as +> maximum in the downstream L4T kernel. +> +> In tegra2_clocks.c: +> PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 0x31E, 92000000, +> mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ +> +> And in tegra3_clocks.c +> PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, +> mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ +> +> I looked up the commit in the downstream kernel that added the "nor" +> clock, it does not mention reason behind the maximal rates. Author +> was +> Manoj Chourasia, added him to CC. + +Let's see whether we do get any feedback from him. + +Nonetheless it may be good to add this information to the commit +message so should somebody ever feel the same curiosity like I did he +would at least know where it initially came from. + +> I actually do not have the Tegra2 Interface Design Guide, do not know +> if I can get access to it. + +I guess that one is only accessible under NDA. We could of course try +to get one in place for you but I can't promise you anything. + +> Best Regards +> Mirza + +Thanks, Mirza diff --git a/a/content_digest b/N1/content_digest index 413a254..d8dcf92 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -5,48 +5,60 @@ "Subject\0Re: [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table]\0" "Date\0Wed, 31 Aug 2016 11:28:36 +0000\0" "To\0mirza.krak@gmail.com <mirza.krak@gmail.com>\0" - "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>" - robh+dt@kernel.org <robh+dt@kernel.org> - jonathanh@nvidia.com <jonathanh@nvidia.com> - mturquette@baylibre.com <mturquette@baylibre.com> - pgaikwad@nvidia.com <pgaikwad@nvidia.com> - linux@armlinux.org.uk <linux@armlinux.org.uk> + "Cc\0mark.rutland@arm.com <mark.rutland@arm.com>" devicetree@vger.kernel.org <devicetree@vger.kernel.org> + pgaikwad@nvidia.com <pgaikwad@nvidia.com> + linux-clk@vger.kernel.org <linux-clk@vger.kernel.org> gnurou@gmail.com <gnurou@gmail.com> - mchourasia@nvidia.com <mchourasia@nvidia.com> - thierry.reding@gmail.com <thierry.reding@gmail.com> - mark.rutland@arm.com <mark.rutland@arm.com> - linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> - pdeschrijver@nvidia.com <pdeschrijver@nvidia.com> + mturquette@baylibre.com <mturquette@baylibre.com> + swarren@wwwdotorg.org <swarren@wwwdotorg.org> sboyd@codeaurora.org <sboyd@codeaurora.org> + linux@armlinux.org.uk <linux@armlinux.org.uk> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + robh+dt@kernel.org <robh+dt@kernel.org> + thierry.reding@gmail.com <thierry.reding@gmail.com> + mchourasia@nvidia.com <mchourasia@nvidia.com> linux-tegra@vger.kernel.org <linux-tegra@vger.kernel.org> - swarren@wwwdotorg.org <swarren@wwwdotorg.org> - " linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>\0" + jonathanh@nvidia.com <jonathanh@nvidia.com> + pdeschrijver@nvidia.com <pdeschrijver@nvidia.com> + " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.i>\0" "\00:1\0" "b\0" - "T24gV2VkLCAyMDE2LTA4LTMxIGF0IDExOjQ3ICswMjAwLCBNaXJ6YSBLcmFrIHdyb3RlOg0KPiBJ\n" - "J20ganVzdCBjdXJpb3VzIHdoZXJlIHRoYXQgOTIgTUh6IGNhbWUgZnJvbS4gQWNjb3JkaW5nIHRv\n" - "IHRoZQ0KPiA+IFRlZ3JhIDINCj4gPiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlIHVwIHRvIDEzMyBN\n" - "SHogc2hvdWxkIGFjdHVhbGx5IGJlIHBvc3NpYmxlLg0KPiBUaGUgbWF4aW11bSByYXRlcyBmb3Ig\n" - "Ym90aCBUMjAgYW5kIFQzMCBhcmUgdmFsdWVzIHRoYXQgYXJlIHNldCBhcw0KPiBtYXhpbXVtIGlu\n" - "IHRoZSBkb3duc3RyZWFtIEw0VCBrZXJuZWwuDQo+IA0KPiBJbiB0ZWdyYTJfY2xvY2tzLmM6DQo+\n" - "IFBFUklQSF9DTEsoIm5vciIsICJ0ZWdyYS1ub3IiLCBOVUxMLCA0MiwgMHgxZDAsIDB4MzFFLCA5\n" - "MjAwMDAwMCwNCj4gbXV4X3BsbHBfcGxsY19wbGxtX2Nsa20sIE1VWCB8IERJVl9VNzEpLCAvKiBy\n" - "ZXF1aXJlcyBtaW4gdm9sdGFnZSAqLw0KPiANCj4gQW5kIGluIHRlZ3JhM19jbG9ja3MuYw0KPiBQ\n" - "RVJJUEhfQ0xLKCJub3IiLCAidGVncmEtbm9yIiwgTlVMTCwgNDIsIDB4MWQwLCAxMjcwMDAwMDAs\n" - "DQo+IG11eF9wbGxwX3BsbGNfcGxsbV9jbGttLCBNVVggfCBESVZfVTcxKSwgLyogcmVxdWlyZXMg\n" - "bWluIHZvbHRhZ2UgKi8NCj4gDQo+IEkgbG9va2VkIHVwIHRoZSBjb21taXQgaW4gdGhlIGRvd25z\n" - "dHJlYW0ga2VybmVsIHRoYXQgYWRkZWQgdGhlICJub3IiDQo+IGNsb2NrLCBpdCBkb2VzIG5vdCBt\n" - "ZW50aW9uIHJlYXNvbiBiZWhpbmQgdGhlIG1heGltYWwgcmF0ZXMuIEF1dGhvcg0KPiB3YXMNCj4g\n" - "TWFub2ogQ2hvdXJhc2lhLCBhZGRlZCBoaW0gdG8gQ0MuDQoNCkxldCdzIHNlZSB3aGV0aGVyIHdl\n" - "IGRvIGdldCBhbnkgZmVlZGJhY2sgZnJvbSBoaW0uDQoNCk5vbmV0aGVsZXNzIGl0IG1heSBiZSBn\n" - "b29kIHRvIGFkZCB0aGlzIGluZm9ybWF0aW9uIHRvIHRoZSBjb21taXQNCm1lc3NhZ2Ugc28gc2hv\n" - "dWxkIHNvbWVib2R5IGV2ZXIgZmVlbCB0aGUgc2FtZSBjdXJpb3NpdHkgbGlrZSBJIGRpZCBoZQ0K\n" - "d291bGQgYXQgbGVhc3Qga25vdyB3aGVyZSBpdCBpbml0aWFsbHkgY2FtZSBmcm9tLg0KDQo+IEkg\n" - "YWN0dWFsbHkgZG8gbm90IGhhdmUgdGhlIFRlZ3JhMiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlLCBk\n" - "byBub3Qga25vdw0KPiBpZiBJIGNhbiBnZXQgYWNjZXNzIHRvIGl0Lg0KDQpJIGd1ZXNzIHRoYXQg\n" - "b25lIGlzIG9ubHkgYWNjZXNzaWJsZSB1bmRlciBOREEuIFdlIGNvdWxkIG9mIGNvdXJzZSB0cnkN\n" - "CnRvIGdldCBvbmUgaW4gcGxhY2UgZm9yIHlvdSBidXQgSSBjYW4ndCBwcm9taXNlIHlvdSBhbnl0\n" - aGluZy4NCg0KPiBCZXN0IFJlZ2FyZHMNCj4gTWlyemENCg0KVGhhbmtzLCBNaXJ6YQ== + "On Wed, 2016-08-31 at 11:47 +0200, Mirza Krak wrote:\n" + "> I'm just curious where that 92 MHz came from. According to the\n" + "> > Tegra 2\n" + "> > Interface Design Guide up to 133 MHz should actually be possible.\n" + "> The maximum rates for both T20 and T30 are values that are set as\n" + "> maximum in the downstream L4T kernel.\n" + "> \n" + "> In tegra2_clocks.c:\n" + "> PERIPH_CLK(\"nor\", \"tegra-nor\", NULL, 42, 0x1d0, 0x31E, 92000000,\n" + "> mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */\n" + "> \n" + "> And in tegra3_clocks.c\n" + "> PERIPH_CLK(\"nor\", \"tegra-nor\", NULL, 42, 0x1d0, 127000000,\n" + "> mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */\n" + "> \n" + "> I looked up the commit in the downstream kernel that added the \"nor\"\n" + "> clock, it does not mention reason behind the maximal rates. Author\n" + "> was\n" + "> Manoj Chourasia, added him to CC.\n" + "\n" + "Let's see whether we do get any feedback from him.\n" + "\n" + "Nonetheless it may be good to add this information to the commit\n" + "message so should somebody ever feel the same curiosity like I did he\n" + "would at least know where it initially came from.\n" + "\n" + "> I actually do not have the Tegra2 Interface Design Guide, do not know\n" + "> if I can get access to it.\n" + "\n" + "I guess that one is only accessible under NDA. We could of course try\n" + "to get one in place for you but I can't promise you anything.\n" + "\n" + "> Best Regards\n" + "> Mirza\n" + "\n" + Thanks, Mirza -946b7ee938c6f3e0ae6af4850eb067c1a429bb20b471fb825ef27cf69620f5a7 +2537aee222095224b2b4af081efc4824ee0769324d0c7ea303930dd84419b10b
diff --git a/a/1.txt b/N2/1.txt index 1b98640..58e0462 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,24 +1,36 @@ -T24gV2VkLCAyMDE2LTA4LTMxIGF0IDExOjQ3ICswMjAwLCBNaXJ6YSBLcmFrIHdyb3RlOg0KPiBJ -J20ganVzdCBjdXJpb3VzIHdoZXJlIHRoYXQgOTIgTUh6IGNhbWUgZnJvbS4gQWNjb3JkaW5nIHRv -IHRoZQ0KPiA+IFRlZ3JhIDINCj4gPiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlIHVwIHRvIDEzMyBN -SHogc2hvdWxkIGFjdHVhbGx5IGJlIHBvc3NpYmxlLg0KPiBUaGUgbWF4aW11bSByYXRlcyBmb3Ig -Ym90aCBUMjAgYW5kIFQzMCBhcmUgdmFsdWVzIHRoYXQgYXJlIHNldCBhcw0KPiBtYXhpbXVtIGlu -IHRoZSBkb3duc3RyZWFtIEw0VCBrZXJuZWwuDQo+IA0KPiBJbiB0ZWdyYTJfY2xvY2tzLmM6DQo+ -IFBFUklQSF9DTEsoIm5vciIsICJ0ZWdyYS1ub3IiLCBOVUxMLCA0MiwgMHgxZDAsIDB4MzFFLCA5 -MjAwMDAwMCwNCj4gbXV4X3BsbHBfcGxsY19wbGxtX2Nsa20sIE1VWCB8IERJVl9VNzEpLCAvKiBy -ZXF1aXJlcyBtaW4gdm9sdGFnZSAqLw0KPiANCj4gQW5kIGluIHRlZ3JhM19jbG9ja3MuYw0KPiBQ -RVJJUEhfQ0xLKCJub3IiLCAidGVncmEtbm9yIiwgTlVMTCwgNDIsIDB4MWQwLCAxMjcwMDAwMDAs -DQo+IG11eF9wbGxwX3BsbGNfcGxsbV9jbGttLCBNVVggfCBESVZfVTcxKSwgLyogcmVxdWlyZXMg -bWluIHZvbHRhZ2UgKi8NCj4gDQo+IEkgbG9va2VkIHVwIHRoZSBjb21taXQgaW4gdGhlIGRvd25z -dHJlYW0ga2VybmVsIHRoYXQgYWRkZWQgdGhlICJub3IiDQo+IGNsb2NrLCBpdCBkb2VzIG5vdCBt -ZW50aW9uIHJlYXNvbiBiZWhpbmQgdGhlIG1heGltYWwgcmF0ZXMuIEF1dGhvcg0KPiB3YXMNCj4g -TWFub2ogQ2hvdXJhc2lhLCBhZGRlZCBoaW0gdG8gQ0MuDQoNCkxldCdzIHNlZSB3aGV0aGVyIHdl -IGRvIGdldCBhbnkgZmVlZGJhY2sgZnJvbSBoaW0uDQoNCk5vbmV0aGVsZXNzIGl0IG1heSBiZSBn -b29kIHRvIGFkZCB0aGlzIGluZm9ybWF0aW9uIHRvIHRoZSBjb21taXQNCm1lc3NhZ2Ugc28gc2hv -dWxkIHNvbWVib2R5IGV2ZXIgZmVlbCB0aGUgc2FtZSBjdXJpb3NpdHkgbGlrZSBJIGRpZCBoZQ0K -d291bGQgYXQgbGVhc3Qga25vdyB3aGVyZSBpdCBpbml0aWFsbHkgY2FtZSBmcm9tLg0KDQo+IEkg -YWN0dWFsbHkgZG8gbm90IGhhdmUgdGhlIFRlZ3JhMiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlLCBk -byBub3Qga25vdw0KPiBpZiBJIGNhbiBnZXQgYWNjZXNzIHRvIGl0Lg0KDQpJIGd1ZXNzIHRoYXQg -b25lIGlzIG9ubHkgYWNjZXNzaWJsZSB1bmRlciBOREEuIFdlIGNvdWxkIG9mIGNvdXJzZSB0cnkN -CnRvIGdldCBvbmUgaW4gcGxhY2UgZm9yIHlvdSBidXQgSSBjYW4ndCBwcm9taXNlIHlvdSBhbnl0 -aGluZy4NCg0KPiBCZXN0IFJlZ2FyZHMNCj4gTWlyemENCg0KVGhhbmtzLCBNaXJ6YQ== +On Wed, 2016-08-31 at 11:47 +0200, Mirza Krak wrote: +> I'm just curious where that 92 MHz came from. According to the +> > Tegra 2 +> > Interface Design Guide up to 133 MHz should actually be possible. +> The maximum rates for both T20 and T30 are values that are set as +> maximum in the downstream L4T kernel. +> +> In tegra2_clocks.c: +> PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 0x31E, 92000000, +> mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ +> +> And in tegra3_clocks.c +> PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, +> mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ +> +> I looked up the commit in the downstream kernel that added the "nor" +> clock, it does not mention reason behind the maximal rates. Author +> was +> Manoj Chourasia, added him to CC. + +Let's see whether we do get any feedback from him. + +Nonetheless it may be good to add this information to the commit +message so should somebody ever feel the same curiosity like I did he +would at least know where it initially came from. + +> I actually do not have the Tegra2 Interface Design Guide, do not know +> if I can get access to it. + +I guess that one is only accessible under NDA. We could of course try +to get one in place for you but I can't promise you anything. + +> Best Regards +> Mirza + +Thanks, Mirza diff --git a/a/content_digest b/N2/content_digest index 413a254..0a13f6e 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,52 +1,47 @@ "ref\01472569308.5703.22.camel@toradex.com\0" "ref\01472627744.31008.2.camel@toradex.com\0" "ref\0CALw8SCUHjFAr7RT3UCOkZ9W4Uf=nLHr2F3A_DqKiw1q_LOXDrg@mail.gmail.com\0" - "From\0Marcel Ziswiler <marcel.ziswiler@toradex.com>\0" - "Subject\0Re: [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table]\0" + "From\0marcel.ziswiler@toradex.com (Marcel Ziswiler)\0" + "Subject\0[Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table]\0" "Date\0Wed, 31 Aug 2016 11:28:36 +0000\0" - "To\0mirza.krak@gmail.com <mirza.krak@gmail.com>\0" - "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>" - robh+dt@kernel.org <robh+dt@kernel.org> - jonathanh@nvidia.com <jonathanh@nvidia.com> - mturquette@baylibre.com <mturquette@baylibre.com> - pgaikwad@nvidia.com <pgaikwad@nvidia.com> - linux@armlinux.org.uk <linux@armlinux.org.uk> - devicetree@vger.kernel.org <devicetree@vger.kernel.org> - gnurou@gmail.com <gnurou@gmail.com> - mchourasia@nvidia.com <mchourasia@nvidia.com> - thierry.reding@gmail.com <thierry.reding@gmail.com> - mark.rutland@arm.com <mark.rutland@arm.com> - linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> - pdeschrijver@nvidia.com <pdeschrijver@nvidia.com> - sboyd@codeaurora.org <sboyd@codeaurora.org> - linux-tegra@vger.kernel.org <linux-tegra@vger.kernel.org> - swarren@wwwdotorg.org <swarren@wwwdotorg.org> - " linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "T24gV2VkLCAyMDE2LTA4LTMxIGF0IDExOjQ3ICswMjAwLCBNaXJ6YSBLcmFrIHdyb3RlOg0KPiBJ\n" - "J20ganVzdCBjdXJpb3VzIHdoZXJlIHRoYXQgOTIgTUh6IGNhbWUgZnJvbS4gQWNjb3JkaW5nIHRv\n" - "IHRoZQ0KPiA+IFRlZ3JhIDINCj4gPiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlIHVwIHRvIDEzMyBN\n" - "SHogc2hvdWxkIGFjdHVhbGx5IGJlIHBvc3NpYmxlLg0KPiBUaGUgbWF4aW11bSByYXRlcyBmb3Ig\n" - "Ym90aCBUMjAgYW5kIFQzMCBhcmUgdmFsdWVzIHRoYXQgYXJlIHNldCBhcw0KPiBtYXhpbXVtIGlu\n" - "IHRoZSBkb3duc3RyZWFtIEw0VCBrZXJuZWwuDQo+IA0KPiBJbiB0ZWdyYTJfY2xvY2tzLmM6DQo+\n" - "IFBFUklQSF9DTEsoIm5vciIsICJ0ZWdyYS1ub3IiLCBOVUxMLCA0MiwgMHgxZDAsIDB4MzFFLCA5\n" - "MjAwMDAwMCwNCj4gbXV4X3BsbHBfcGxsY19wbGxtX2Nsa20sIE1VWCB8IERJVl9VNzEpLCAvKiBy\n" - "ZXF1aXJlcyBtaW4gdm9sdGFnZSAqLw0KPiANCj4gQW5kIGluIHRlZ3JhM19jbG9ja3MuYw0KPiBQ\n" - "RVJJUEhfQ0xLKCJub3IiLCAidGVncmEtbm9yIiwgTlVMTCwgNDIsIDB4MWQwLCAxMjcwMDAwMDAs\n" - "DQo+IG11eF9wbGxwX3BsbGNfcGxsbV9jbGttLCBNVVggfCBESVZfVTcxKSwgLyogcmVxdWlyZXMg\n" - "bWluIHZvbHRhZ2UgKi8NCj4gDQo+IEkgbG9va2VkIHVwIHRoZSBjb21taXQgaW4gdGhlIGRvd25z\n" - "dHJlYW0ga2VybmVsIHRoYXQgYWRkZWQgdGhlICJub3IiDQo+IGNsb2NrLCBpdCBkb2VzIG5vdCBt\n" - "ZW50aW9uIHJlYXNvbiBiZWhpbmQgdGhlIG1heGltYWwgcmF0ZXMuIEF1dGhvcg0KPiB3YXMNCj4g\n" - "TWFub2ogQ2hvdXJhc2lhLCBhZGRlZCBoaW0gdG8gQ0MuDQoNCkxldCdzIHNlZSB3aGV0aGVyIHdl\n" - "IGRvIGdldCBhbnkgZmVlZGJhY2sgZnJvbSBoaW0uDQoNCk5vbmV0aGVsZXNzIGl0IG1heSBiZSBn\n" - "b29kIHRvIGFkZCB0aGlzIGluZm9ybWF0aW9uIHRvIHRoZSBjb21taXQNCm1lc3NhZ2Ugc28gc2hv\n" - "dWxkIHNvbWVib2R5IGV2ZXIgZmVlbCB0aGUgc2FtZSBjdXJpb3NpdHkgbGlrZSBJIGRpZCBoZQ0K\n" - "d291bGQgYXQgbGVhc3Qga25vdyB3aGVyZSBpdCBpbml0aWFsbHkgY2FtZSBmcm9tLg0KDQo+IEkg\n" - "YWN0dWFsbHkgZG8gbm90IGhhdmUgdGhlIFRlZ3JhMiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlLCBk\n" - "byBub3Qga25vdw0KPiBpZiBJIGNhbiBnZXQgYWNjZXNzIHRvIGl0Lg0KDQpJIGd1ZXNzIHRoYXQg\n" - "b25lIGlzIG9ubHkgYWNjZXNzaWJsZSB1bmRlciBOREEuIFdlIGNvdWxkIG9mIGNvdXJzZSB0cnkN\n" - "CnRvIGdldCBvbmUgaW4gcGxhY2UgZm9yIHlvdSBidXQgSSBjYW4ndCBwcm9taXNlIHlvdSBhbnl0\n" - aGluZy4NCg0KPiBCZXN0IFJlZ2FyZHMNCj4gTWlyemENCg0KVGhhbmtzLCBNaXJ6YQ== + "On Wed, 2016-08-31 at 11:47 +0200, Mirza Krak wrote:\n" + "> I'm just curious where that 92 MHz came from. According to the\n" + "> > Tegra 2\n" + "> > Interface Design Guide up to 133 MHz should actually be possible.\n" + "> The maximum rates for both T20 and T30 are values that are set as\n" + "> maximum in the downstream L4T kernel.\n" + "> \n" + "> In tegra2_clocks.c:\n" + "> PERIPH_CLK(\"nor\", \"tegra-nor\", NULL, 42, 0x1d0, 0x31E, 92000000,\n" + "> mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */\n" + "> \n" + "> And in tegra3_clocks.c\n" + "> PERIPH_CLK(\"nor\", \"tegra-nor\", NULL, 42, 0x1d0, 127000000,\n" + "> mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */\n" + "> \n" + "> I looked up the commit in the downstream kernel that added the \"nor\"\n" + "> clock, it does not mention reason behind the maximal rates. Author\n" + "> was\n" + "> Manoj Chourasia, added him to CC.\n" + "\n" + "Let's see whether we do get any feedback from him.\n" + "\n" + "Nonetheless it may be good to add this information to the commit\n" + "message so should somebody ever feel the same curiosity like I did he\n" + "would at least know where it initially came from.\n" + "\n" + "> I actually do not have the Tegra2 Interface Design Guide, do not know\n" + "> if I can get access to it.\n" + "\n" + "I guess that one is only accessible under NDA. We could of course try\n" + "to get one in place for you but I can't promise you anything.\n" + "\n" + "> Best Regards\n" + "> Mirza\n" + "\n" + Thanks, Mirza -946b7ee938c6f3e0ae6af4850eb067c1a429bb20b471fb825ef27cf69620f5a7 +4639fcf289ffb4f7849bb1ffef89c743244491bde4ac045588fa05b69bad6977
diff --git a/a/1.txt b/N3/1.txt index 1b98640..58e0462 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -1,24 +1,36 @@ -T24gV2VkLCAyMDE2LTA4LTMxIGF0IDExOjQ3ICswMjAwLCBNaXJ6YSBLcmFrIHdyb3RlOg0KPiBJ -J20ganVzdCBjdXJpb3VzIHdoZXJlIHRoYXQgOTIgTUh6IGNhbWUgZnJvbS4gQWNjb3JkaW5nIHRv -IHRoZQ0KPiA+IFRlZ3JhIDINCj4gPiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlIHVwIHRvIDEzMyBN -SHogc2hvdWxkIGFjdHVhbGx5IGJlIHBvc3NpYmxlLg0KPiBUaGUgbWF4aW11bSByYXRlcyBmb3Ig -Ym90aCBUMjAgYW5kIFQzMCBhcmUgdmFsdWVzIHRoYXQgYXJlIHNldCBhcw0KPiBtYXhpbXVtIGlu -IHRoZSBkb3duc3RyZWFtIEw0VCBrZXJuZWwuDQo+IA0KPiBJbiB0ZWdyYTJfY2xvY2tzLmM6DQo+ -IFBFUklQSF9DTEsoIm5vciIsICJ0ZWdyYS1ub3IiLCBOVUxMLCA0MiwgMHgxZDAsIDB4MzFFLCA5 -MjAwMDAwMCwNCj4gbXV4X3BsbHBfcGxsY19wbGxtX2Nsa20sIE1VWCB8IERJVl9VNzEpLCAvKiBy -ZXF1aXJlcyBtaW4gdm9sdGFnZSAqLw0KPiANCj4gQW5kIGluIHRlZ3JhM19jbG9ja3MuYw0KPiBQ -RVJJUEhfQ0xLKCJub3IiLCAidGVncmEtbm9yIiwgTlVMTCwgNDIsIDB4MWQwLCAxMjcwMDAwMDAs -DQo+IG11eF9wbGxwX3BsbGNfcGxsbV9jbGttLCBNVVggfCBESVZfVTcxKSwgLyogcmVxdWlyZXMg -bWluIHZvbHRhZ2UgKi8NCj4gDQo+IEkgbG9va2VkIHVwIHRoZSBjb21taXQgaW4gdGhlIGRvd25z -dHJlYW0ga2VybmVsIHRoYXQgYWRkZWQgdGhlICJub3IiDQo+IGNsb2NrLCBpdCBkb2VzIG5vdCBt -ZW50aW9uIHJlYXNvbiBiZWhpbmQgdGhlIG1heGltYWwgcmF0ZXMuIEF1dGhvcg0KPiB3YXMNCj4g -TWFub2ogQ2hvdXJhc2lhLCBhZGRlZCBoaW0gdG8gQ0MuDQoNCkxldCdzIHNlZSB3aGV0aGVyIHdl -IGRvIGdldCBhbnkgZmVlZGJhY2sgZnJvbSBoaW0uDQoNCk5vbmV0aGVsZXNzIGl0IG1heSBiZSBn -b29kIHRvIGFkZCB0aGlzIGluZm9ybWF0aW9uIHRvIHRoZSBjb21taXQNCm1lc3NhZ2Ugc28gc2hv -dWxkIHNvbWVib2R5IGV2ZXIgZmVlbCB0aGUgc2FtZSBjdXJpb3NpdHkgbGlrZSBJIGRpZCBoZQ0K -d291bGQgYXQgbGVhc3Qga25vdyB3aGVyZSBpdCBpbml0aWFsbHkgY2FtZSBmcm9tLg0KDQo+IEkg -YWN0dWFsbHkgZG8gbm90IGhhdmUgdGhlIFRlZ3JhMiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlLCBk -byBub3Qga25vdw0KPiBpZiBJIGNhbiBnZXQgYWNjZXNzIHRvIGl0Lg0KDQpJIGd1ZXNzIHRoYXQg -b25lIGlzIG9ubHkgYWNjZXNzaWJsZSB1bmRlciBOREEuIFdlIGNvdWxkIG9mIGNvdXJzZSB0cnkN -CnRvIGdldCBvbmUgaW4gcGxhY2UgZm9yIHlvdSBidXQgSSBjYW4ndCBwcm9taXNlIHlvdSBhbnl0 -aGluZy4NCg0KPiBCZXN0IFJlZ2FyZHMNCj4gTWlyemENCg0KVGhhbmtzLCBNaXJ6YQ== +On Wed, 2016-08-31 at 11:47 +0200, Mirza Krak wrote: +> I'm just curious where that 92 MHz came from. According to the +> > Tegra 2 +> > Interface Design Guide up to 133 MHz should actually be possible. +> The maximum rates for both T20 and T30 are values that are set as +> maximum in the downstream L4T kernel. +> +> In tegra2_clocks.c: +> PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 0x31E, 92000000, +> mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ +> +> And in tegra3_clocks.c +> PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, +> mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ +> +> I looked up the commit in the downstream kernel that added the "nor" +> clock, it does not mention reason behind the maximal rates. Author +> was +> Manoj Chourasia, added him to CC. + +Let's see whether we do get any feedback from him. + +Nonetheless it may be good to add this information to the commit +message so should somebody ever feel the same curiosity like I did he +would at least know where it initially came from. + +> I actually do not have the Tegra2 Interface Design Guide, do not know +> if I can get access to it. + +I guess that one is only accessible under NDA. We could of course try +to get one in place for you but I can't promise you anything. + +> Best Regards +> Mirza + +Thanks, Mirza diff --git a/a/content_digest b/N3/content_digest index 413a254..8df6a2a 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -24,29 +24,41 @@ " linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>\0" "\00:1\0" "b\0" - "T24gV2VkLCAyMDE2LTA4LTMxIGF0IDExOjQ3ICswMjAwLCBNaXJ6YSBLcmFrIHdyb3RlOg0KPiBJ\n" - "J20ganVzdCBjdXJpb3VzIHdoZXJlIHRoYXQgOTIgTUh6IGNhbWUgZnJvbS4gQWNjb3JkaW5nIHRv\n" - "IHRoZQ0KPiA+IFRlZ3JhIDINCj4gPiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlIHVwIHRvIDEzMyBN\n" - "SHogc2hvdWxkIGFjdHVhbGx5IGJlIHBvc3NpYmxlLg0KPiBUaGUgbWF4aW11bSByYXRlcyBmb3Ig\n" - "Ym90aCBUMjAgYW5kIFQzMCBhcmUgdmFsdWVzIHRoYXQgYXJlIHNldCBhcw0KPiBtYXhpbXVtIGlu\n" - "IHRoZSBkb3duc3RyZWFtIEw0VCBrZXJuZWwuDQo+IA0KPiBJbiB0ZWdyYTJfY2xvY2tzLmM6DQo+\n" - "IFBFUklQSF9DTEsoIm5vciIsICJ0ZWdyYS1ub3IiLCBOVUxMLCA0MiwgMHgxZDAsIDB4MzFFLCA5\n" - "MjAwMDAwMCwNCj4gbXV4X3BsbHBfcGxsY19wbGxtX2Nsa20sIE1VWCB8IERJVl9VNzEpLCAvKiBy\n" - "ZXF1aXJlcyBtaW4gdm9sdGFnZSAqLw0KPiANCj4gQW5kIGluIHRlZ3JhM19jbG9ja3MuYw0KPiBQ\n" - "RVJJUEhfQ0xLKCJub3IiLCAidGVncmEtbm9yIiwgTlVMTCwgNDIsIDB4MWQwLCAxMjcwMDAwMDAs\n" - "DQo+IG11eF9wbGxwX3BsbGNfcGxsbV9jbGttLCBNVVggfCBESVZfVTcxKSwgLyogcmVxdWlyZXMg\n" - "bWluIHZvbHRhZ2UgKi8NCj4gDQo+IEkgbG9va2VkIHVwIHRoZSBjb21taXQgaW4gdGhlIGRvd25z\n" - "dHJlYW0ga2VybmVsIHRoYXQgYWRkZWQgdGhlICJub3IiDQo+IGNsb2NrLCBpdCBkb2VzIG5vdCBt\n" - "ZW50aW9uIHJlYXNvbiBiZWhpbmQgdGhlIG1heGltYWwgcmF0ZXMuIEF1dGhvcg0KPiB3YXMNCj4g\n" - "TWFub2ogQ2hvdXJhc2lhLCBhZGRlZCBoaW0gdG8gQ0MuDQoNCkxldCdzIHNlZSB3aGV0aGVyIHdl\n" - "IGRvIGdldCBhbnkgZmVlZGJhY2sgZnJvbSBoaW0uDQoNCk5vbmV0aGVsZXNzIGl0IG1heSBiZSBn\n" - "b29kIHRvIGFkZCB0aGlzIGluZm9ybWF0aW9uIHRvIHRoZSBjb21taXQNCm1lc3NhZ2Ugc28gc2hv\n" - "dWxkIHNvbWVib2R5IGV2ZXIgZmVlbCB0aGUgc2FtZSBjdXJpb3NpdHkgbGlrZSBJIGRpZCBoZQ0K\n" - "d291bGQgYXQgbGVhc3Qga25vdyB3aGVyZSBpdCBpbml0aWFsbHkgY2FtZSBmcm9tLg0KDQo+IEkg\n" - "YWN0dWFsbHkgZG8gbm90IGhhdmUgdGhlIFRlZ3JhMiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlLCBk\n" - "byBub3Qga25vdw0KPiBpZiBJIGNhbiBnZXQgYWNjZXNzIHRvIGl0Lg0KDQpJIGd1ZXNzIHRoYXQg\n" - "b25lIGlzIG9ubHkgYWNjZXNzaWJsZSB1bmRlciBOREEuIFdlIGNvdWxkIG9mIGNvdXJzZSB0cnkN\n" - "CnRvIGdldCBvbmUgaW4gcGxhY2UgZm9yIHlvdSBidXQgSSBjYW4ndCBwcm9taXNlIHlvdSBhbnl0\n" - aGluZy4NCg0KPiBCZXN0IFJlZ2FyZHMNCj4gTWlyemENCg0KVGhhbmtzLCBNaXJ6YQ== + "On Wed, 2016-08-31 at 11:47 +0200, Mirza Krak wrote:\n" + "> I'm just curious where that 92 MHz came from. According to the\n" + "> > Tegra 2\n" + "> > Interface Design Guide up to 133 MHz should actually be possible.\n" + "> The maximum rates for both T20 and T30 are values that are set as\n" + "> maximum in the downstream L4T kernel.\n" + "> \n" + "> In tegra2_clocks.c:\n" + "> PERIPH_CLK(\"nor\", \"tegra-nor\", NULL, 42, 0x1d0, 0x31E, 92000000,\n" + "> mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */\n" + "> \n" + "> And in tegra3_clocks.c\n" + "> PERIPH_CLK(\"nor\", \"tegra-nor\", NULL, 42, 0x1d0, 127000000,\n" + "> mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */\n" + "> \n" + "> I looked up the commit in the downstream kernel that added the \"nor\"\n" + "> clock, it does not mention reason behind the maximal rates. Author\n" + "> was\n" + "> Manoj Chourasia, added him to CC.\n" + "\n" + "Let's see whether we do get any feedback from him.\n" + "\n" + "Nonetheless it may be good to add this information to the commit\n" + "message so should somebody ever feel the same curiosity like I did he\n" + "would at least know where it initially came from.\n" + "\n" + "> I actually do not have the Tegra2 Interface Design Guide, do not know\n" + "> if I can get access to it.\n" + "\n" + "I guess that one is only accessible under NDA. We could of course try\n" + "to get one in place for you but I can't promise you anything.\n" + "\n" + "> Best Regards\n" + "> Mirza\n" + "\n" + Thanks, Mirza -946b7ee938c6f3e0ae6af4850eb067c1a429bb20b471fb825ef27cf69620f5a7 +81ac70fd3d0b5679a23af8acfa60aa6831a2049663bf338cd090bf6abfb99a6d
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