From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Marcel Ziswiler To: "mirza.krak@gmail.com" CC: "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "jonathanh@nvidia.com" , "mturquette@baylibre.com" , "pgaikwad@nvidia.com" , "linux@armlinux.org.uk" , "devicetree@vger.kernel.org" , "gnurou@gmail.com" , "mchourasia@nvidia.com" , "thierry.reding@gmail.com" , "mark.rutland@arm.com" , "linux-arm-kernel@lists.infradead.org" , "pdeschrijver@nvidia.com" , "sboyd@codeaurora.org" , "linux-tegra@vger.kernel.org" , "swarren@wwwdotorg.org" , "linux-clk@vger.kernel.org" Subject: Re: [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table] Date: Wed, 31 Aug 2016 11:28:36 +0000 Message-ID: <1472642915.31008.32.camel@toradex.com> References: <1472569308.5703.22.camel@toradex.com> <1472627744.31008.2.camel@toradex.com> In-Reply-To: Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 List-ID: T24gV2VkLCAyMDE2LTA4LTMxIGF0IDExOjQ3ICswMjAwLCBNaXJ6YSBLcmFrIHdyb3RlOg0KPiBJ J20ganVzdCBjdXJpb3VzIHdoZXJlIHRoYXQgOTIgTUh6IGNhbWUgZnJvbS4gQWNjb3JkaW5nIHRv IHRoZQ0KPiA+IFRlZ3JhIDINCj4gPiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlIHVwIHRvIDEzMyBN SHogc2hvdWxkIGFjdHVhbGx5IGJlIHBvc3NpYmxlLg0KPiBUaGUgbWF4aW11bSByYXRlcyBmb3Ig Ym90aCBUMjAgYW5kIFQzMCBhcmUgdmFsdWVzIHRoYXQgYXJlIHNldCBhcw0KPiBtYXhpbXVtIGlu IHRoZSBkb3duc3RyZWFtIEw0VCBrZXJuZWwuDQo+IA0KPiBJbiB0ZWdyYTJfY2xvY2tzLmM6DQo+ IFBFUklQSF9DTEsoIm5vciIsICJ0ZWdyYS1ub3IiLCBOVUxMLCA0MiwgMHgxZDAsIDB4MzFFLCA5 MjAwMDAwMCwNCj4gbXV4X3BsbHBfcGxsY19wbGxtX2Nsa20sIE1VWCB8IERJVl9VNzEpLCAvKiBy ZXF1aXJlcyBtaW4gdm9sdGFnZSAqLw0KPiANCj4gQW5kIGluIHRlZ3JhM19jbG9ja3MuYw0KPiBQ RVJJUEhfQ0xLKCJub3IiLCAidGVncmEtbm9yIiwgTlVMTCwgNDIsIDB4MWQwLCAxMjcwMDAwMDAs DQo+IG11eF9wbGxwX3BsbGNfcGxsbV9jbGttLCBNVVggfCBESVZfVTcxKSwgLyogcmVxdWlyZXMg bWluIHZvbHRhZ2UgKi8NCj4gDQo+IEkgbG9va2VkIHVwIHRoZSBjb21taXQgaW4gdGhlIGRvd25z dHJlYW0ga2VybmVsIHRoYXQgYWRkZWQgdGhlICJub3IiDQo+IGNsb2NrLCBpdCBkb2VzIG5vdCBt ZW50aW9uIHJlYXNvbiBiZWhpbmQgdGhlIG1heGltYWwgcmF0ZXMuIEF1dGhvcg0KPiB3YXMNCj4g TWFub2ogQ2hvdXJhc2lhLCBhZGRlZCBoaW0gdG8gQ0MuDQoNCkxldCdzIHNlZSB3aGV0aGVyIHdl IGRvIGdldCBhbnkgZmVlZGJhY2sgZnJvbSBoaW0uDQoNCk5vbmV0aGVsZXNzIGl0IG1heSBiZSBn b29kIHRvIGFkZCB0aGlzIGluZm9ybWF0aW9uIHRvIHRoZSBjb21taXQNCm1lc3NhZ2Ugc28gc2hv dWxkIHNvbWVib2R5IGV2ZXIgZmVlbCB0aGUgc2FtZSBjdXJpb3NpdHkgbGlrZSBJIGRpZCBoZQ0K d291bGQgYXQgbGVhc3Qga25vdyB3aGVyZSBpdCBpbml0aWFsbHkgY2FtZSBmcm9tLg0KDQo+IEkg YWN0dWFsbHkgZG8gbm90IGhhdmUgdGhlIFRlZ3JhMiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlLCBk byBub3Qga25vdw0KPiBpZiBJIGNhbiBnZXQgYWNjZXNzIHRvIGl0Lg0KDQpJIGd1ZXNzIHRoYXQg b25lIGlzIG9ubHkgYWNjZXNzaWJsZSB1bmRlciBOREEuIFdlIGNvdWxkIG9mIGNvdXJzZSB0cnkN CnRvIGdldCBvbmUgaW4gcGxhY2UgZm9yIHlvdSBidXQgSSBjYW4ndCBwcm9taXNlIHlvdSBhbnl0 aGluZy4NCg0KPiBCZXN0IFJlZ2FyZHMNCj4gTWlyemENCg0KVGhhbmtzLCBNaXJ6YQ== From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marcel Ziswiler Subject: Re: [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table] Date: Wed, 31 Aug 2016 11:28:36 +0000 Message-ID: <1472642915.31008.32.camel@toradex.com> References: <1472569308.5703.22.camel@toradex.com> <1472627744.31008.2.camel@toradex.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Content-Language: en-US Content-ID: <8BF3CE870D8E8A48AC8687332C0011DD@eurprd05.prod.outlook.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: "mirza.krak@gmail.com" Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , "pgaikwad@nvidia.com" , "linux-clk@vger.kernel.org" , "gnurou@gmail.com" , "mturquette@baylibre.com" , "swarren@wwwdotorg.org" , "sboyd@codeaurora.org" , "linux@armlinux.org.uk" , "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "thierry.reding@gmail.com" , "mchourasia@nvidia.com" , "linux-tegra@vger.kernel.org" , "jonathanh@nvidia.com" , "pdeschrijver@nvidia.com" , "linux-arm-kernel@lists.infradead.org" List-Id: linux-tegra@vger.kernel.org On Wed, 2016-08-31 at 11:47 +0200, Mirza Krak wrote: > I'm just curious where that 92 MHz came from. According to the > > Tegra 2 > > Interface Design Guide up to 133 MHz should actually be possible. > The maximum rates for both T20 and T30 are values that are set as > maximum in the downstream L4T kernel. > > In tegra2_clocks.c: > PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 0x31E, 92000000, > mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ > > And in tegra3_clocks.c > PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, > mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ > > I looked up the commit in the downstream kernel that added the "nor" > clock, it does not mention reason behind the maximal rates. Author > was > Manoj Chourasia, added him to CC. Let's see whether we do get any feedback from him. Nonetheless it may be good to add this information to the commit message so should somebody ever feel the same curiosity like I did he would at least know where it initially came from. > I actually do not have the Tegra2 Interface Design Guide, do not know > if I can get access to it. I guess that one is only accessible under NDA. We could of course try to get one in place for you but I can't promise you anything. > Best Regards > Mirza Thanks, Mirza From mboxrd@z Thu Jan 1 00:00:00 1970 From: marcel.ziswiler@toradex.com (Marcel Ziswiler) Date: Wed, 31 Aug 2016 11:28:36 +0000 Subject: [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table] In-Reply-To: References: <1472569308.5703.22.camel@toradex.com> <1472627744.31008.2.camel@toradex.com> Message-ID: <1472642915.31008.32.camel@toradex.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, 2016-08-31 at 11:47 +0200, Mirza Krak wrote: > I'm just curious where that 92 MHz came from. According to the > > Tegra 2 > > Interface Design Guide up to 133 MHz should actually be possible. > The maximum rates for both T20 and T30 are values that are set as > maximum in the downstream L4T kernel. > > In tegra2_clocks.c: > PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 0x31E, 92000000, > mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ > > And in tegra3_clocks.c > PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, > mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ > > I looked up the commit in the downstream kernel that added the "nor" > clock, it does not mention reason behind the maximal rates. Author > was > Manoj Chourasia, added him to CC. Let's see whether we do get any feedback from him. Nonetheless it may be good to add this information to the commit message so should somebody ever feel the same curiosity like I did he would at least know where it initially came from. > I actually do not have the Tegra2 Interface Design Guide, do not know > if I can get access to it. I guess that one is only accessible under NDA. We could of course try to get one in place for you but I can't promise you anything. > Best Regards > Mirza Thanks, Mirza From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933784AbcHaLns (ORCPT ); Wed, 31 Aug 2016 07:43:48 -0400 Received: from mail-db5eur01on0108.outbound.protection.outlook.com ([104.47.2.108]:4280 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933027AbcHaLnn (ORCPT ); Wed, 31 Aug 2016 07:43:43 -0400 From: Marcel Ziswiler To: "mirza.krak@gmail.com" CC: "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "jonathanh@nvidia.com" , "mturquette@baylibre.com" , "pgaikwad@nvidia.com" , "linux@armlinux.org.uk" , "devicetree@vger.kernel.org" , "gnurou@gmail.com" , "mchourasia@nvidia.com" , "thierry.reding@gmail.com" , "mark.rutland@arm.com" , "linux-arm-kernel@lists.infradead.org" , "pdeschrijver@nvidia.com" , "sboyd@codeaurora.org" , "linux-tegra@vger.kernel.org" , "swarren@wwwdotorg.org" , "linux-clk@vger.kernel.org" Subject: Re: [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table] Thread-Topic: [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table] Thread-Index: AQHSA1d98ujtJjBPR0ydcsViq/bvhKBi0pGAgAAcX4A= Date: Wed, 31 Aug 2016 11:28:36 +0000 Message-ID: <1472642915.31008.32.camel@toradex.com> References: <1472569308.5703.22.camel@toradex.com> <1472627744.31008.2.camel@toradex.com> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=marcel.ziswiler@toradex.com; x-originating-ip: [46.140.72.82] x-ms-office365-filtering-correlation-id: 64c454b8-52ea-48f1-6f60-08d3d191f2ed x-microsoft-exchange-diagnostics: 1;HE1PR05MB1884;6:xeWVovHVd7FGEiFw6C1DS5FoyJzlahgg188TIhXvF9viWVfxDjSy2r7CSCIZCZ//Er8uimaC/rdKXBjYs7sItURGctFjXb7EFNh387BvvD92+CpoQD73sS6U8RDJFg+Rx4XKI6mmmn1j+kl6ISq4zBPhZDBqqXAgNsodyaOM/adyN4rZVf6azd3sBjRnl+ADt4qQsOq800pSfyNpfsqkUt9dIro4SF/SHi3uSaA9cctudGjATDkdzZ97Y08YiCgm+JYXG1UnAWitDUoEEjjRXcKkq+yDOYjMnY8mPkslBUU=;5:73JPkL59yO6wQ9IrswONRBz2RJBK+uhRvM/nyYdBJRVBlg4HkIERGIgbtP3PmO21vwzL38G3TH7JJdoh9XIKAFU2BsXxjB1D35bNSNI5nU8o03NnMqAerFQqFL4vpuCAQ44FWsq5IZcGMgqUWmHfHg==;24:oKxpap6opP7ASHkU8DTS+I265mmnLH3LV9xAH5CBGl2mm1exh8rtytwIMlP1CMHt5d8vc1og/SJZzRSJxAmHoKIkMWwpi9kOEfTmHKJuD6Q=;7:IJSq8bV4wEFl8AbYHCVPtMOPkYTFC0omD78QIIiVFleCgAuqSAYqgn2UfRWr7JPrUUYQENfckpw9BZIRG1tixlZuVkCtDJ/E0eLenQx2UVHfen6hcIK9Mt6jl/WQFqRabSf4I/BHBzn4/GCBo4juYArvW/ZnwHLUl7sewawXM+Njj3LDSFNrDfT6njRTUdJsDk3KlmI7NN4PM0l3GK5WTTVYpdvB6+1hMRCY0Ebb7RdOtV4RnwQMrBe1soyYDt2y x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:HE1PR05MB1884; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040176)(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001);SRVR:HE1PR05MB1884;BCL:0;PCL:0;RULEID:;SRVR:HE1PR05MB1884; x-forefront-prvs: 00514A2FE6 x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(6009001)(7916002)(189002)(199003)(2473001)(24454002)(377424004)(76176999)(54356999)(87936001)(8936002)(81166006)(5002640100001)(86362001)(81156014)(586003)(11100500001)(5640700001)(3846002)(6116002)(8676002)(77096005)(7736002)(7846002)(101416001)(33646002)(105586002)(102836003)(2906002)(4326007)(305945005)(106116001)(97736004)(66066001)(2900100001)(103116003)(122556002)(68736007)(3280700002)(92566002)(2950100001)(7416002)(50986999)(10400500002)(110136002)(36756003)(2351001)(3660700001)(5660300001)(2501003)(106356001)(189998001);DIR:OUT;SFP:1102;SCL:1;SRVR:HE1PR05MB1884;H:HE1PR05MB1882.eurprd05.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;MX:1;A:1;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" Content-ID: <8BF3CE870D8E8A48AC8687332C0011DD@eurprd05.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: toradex.com X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Aug 2016 11:28:36.0347 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d9995866-0d9b-4251-8315-093f062abab4 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR05MB1884 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id u7VBhsx4003917 On Wed, 2016-08-31 at 11:47 +0200, Mirza Krak wrote: > I'm just curious where that 92 MHz came from. According to the > > Tegra 2 > > Interface Design Guide up to 133 MHz should actually be possible. > The maximum rates for both T20 and T30 are values that are set as > maximum in the downstream L4T kernel. > > In tegra2_clocks.c: > PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 0x31E, 92000000, > mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ > > And in tegra3_clocks.c > PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, > mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ > > I looked up the commit in the downstream kernel that added the "nor" > clock, it does not mention reason behind the maximal rates. Author > was > Manoj Chourasia, added him to CC. Let's see whether we do get any feedback from him. Nonetheless it may be good to add this information to the commit message so should somebody ever feel the same curiosity like I did he would at least know where it initially came from. > I actually do not have the Tegra2 Interface Design Guide, do not know > if I can get access to it. I guess that one is only accessible under NDA. We could of course try to get one in place for you but I can't promise you anything. > Best Regards > Mirza Thanks, Mirza