From mboxrd@z Thu Jan 1 00:00:00 1970 From: YT Shen Subject: [PATCH v7 8/9] drm/mediatek: update DSI sub driver flow Date: Fri, 2 Sep 2016 19:24:43 +0800 Message-ID: <1472815484-43821-9-git-send-email-yt.shen@mediatek.com> References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org, Philipp Zabel Cc: Daniel Vetter , Jie Qiu , Mao Huang , yingjoe.chen@mediatek.com, Dan Carpenter , Jitao Shi , linux-mediatek@lists.infradead.org, Matthias Brugger , shaoming chen , linux-arm-kernel@lists.infradead.org, srv_heupstream@mediatek.com, emil.l.velikov@gmail.com, linux-kernel@vger.kernel.org, Sascha Hauer , Maxime Ripard List-Id: linux-mediatek@lists.infradead.org VGhpcyBwYXRjaCB1cGRhdGUgZW5hYmxlL2Rpc2FibGUgZmxvdyBvZiBEU0kgbW9kdWxlIGFuZCBN SVBJIFRYIG1vZHVsZQoKU2lnbmVkLW9mZi1ieTogc2hhb21pbmcgY2hlbiA8c2hhb21pbmcuY2hl bkBtZWRpYXRlay5jb20+ClNpZ25lZC1vZmYtYnk6IFlUIFNoZW4gPHl0LnNoZW5AbWVkaWF0ZWsu Y29tPgotLS0KIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHNpLmMgICAgIHwgMTAyICsr KysrKysrKysrKysrKysrKysrKysrKysrKy0tLS0tLQogZHJpdmVycy9ncHUvZHJtL21lZGlhdGVr L210a19taXBpX3R4LmMgfCAgMzIgKysrKysrLS0tLS0KIDIgZmlsZXMgY2hhbmdlZCwgMTAxIGlu c2VydGlvbnMoKyksIDMzIGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2Ry bS9tZWRpYXRlay9tdGtfZHNpLmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RzaS5j CmluZGV4IDExMDNmZjQuLmY4MDc2MjEgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZWRp YXRlay9tdGtfZHNpLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kc2kuYwpA QCAtOTUsNiArOTUsOCBAQAogI2RlZmluZSBEU0lfUkFDSwkJMHg4NAogI2RlZmluZSBSQUNLCQkJ CUJJVCgwKQogCisjZGVmaW5lIERTSV9NRU1fQ09OVEkJCTB4OTAKKwogI2RlZmluZSBEU0lfUEhZ X0xDQ09OCQkweDEwNAogI2RlZmluZSBMQ19IU19UWF9FTgkJCUJJVCgwKQogI2RlZmluZSBMQ19V TFBNX0VOCQkJQklUKDEpCkBAIC0xMjcsNiArMTI5LDEwIEBACiAjZGVmaW5lIENMS19IU19QT1NU CQkJKDB4ZmYgPDwgOCkKICNkZWZpbmUgQ0xLX0hTX0VYSVQJCQkoMHhmZiA8PCAxNikKIAorI2Rl ZmluZSBEU0lfVk1fQ01EX0NPTgkJMHgxMzAKKyNkZWZpbmUgVk1fQ01EX0VOCQkJQklUKDApCisj ZGVmaW5lIFRTX1ZGUF9FTgkJCUJJVCg1KQorCiAjZGVmaW5lIERTSV9DTURRMAkJMHgxODAKICNk ZWZpbmUgQ09ORklHCQkJCSgweGZmIDw8IDApCiAjZGVmaW5lIFNIT1JUX1BBQ0tFVAkJCTAKQEAg LTI1MSw3ICsyNTcsOSBAQCBzdGF0aWMgaW50IG10a19kc2lfcG93ZXJvbihzdHJ1Y3QgbXRrX2Rz aSAqZHNpKQogCSAqIG1pcGlfcmF0aW8gaXMgbWlwaSBjbGsgY29lZmZpY2llbnQgZm9yIGJhbGFu Y2UgdGhlIHBpeGVsIGNsayBpbiBtaXBpLgogCSAqIHdlIHNldCBtaXBpX3JhdGlvIGlzIDEuMDUu CiAJICovCi0JZHNpLT5kYXRhX3JhdGUgPSBkc2ktPnZtLnBpeGVsY2xvY2sgKiAzICogMjEgLyAo MSAqIDEwMDAgKiAxMCk7CisJZHNpLT5kYXRhX3JhdGUgPSBkc2ktPnZtLnBpeGVsY2xvY2sgKiAx MiAqIDIxOworCWRzaS0+ZGF0YV9yYXRlIC89IChkc2ktPmxhbmVzICogMTAwMCAqIDEwKTsKKwlk ZXZfaW5mbyhkZXYsICJzZXQgbWlwaXR4J3MgZGF0YSByYXRlOiAlZE1IelxuIiwgZHNpLT5kYXRh X3JhdGUpOwogCiAJcmV0ID0gY2xrX3NldF9yYXRlKGRzaS0+aHNfY2xrLCBkc2ktPmRhdGFfcmF0 ZSAqIDEwMDAwMDApOwogCWlmIChyZXQgPCAwKSB7CkBAIC0yNzMsMTAgKzI4MSw2IEBAIHN0YXRp YyBpbnQgbXRrX2RzaV9wb3dlcm9uKHN0cnVjdCBtdGtfZHNpICpkc2kpCiAJCWdvdG8gZXJyX2Rp c2FibGVfZW5naW5lX2NsazsKIAl9CiAKLQltdGtfZHNpX2VuYWJsZShkc2kpOwotCW10a19kc2lf cmVzZXRfZW5naW5lKGRzaSk7Ci0JbXRrX2RzaV9waHlfdGltY29uZmlnKGRzaSk7Ci0KIAlyZXR1 cm4gMDsKIAogZXJyX2Rpc2FibGVfZW5naW5lX2NsazoKQEAgLTI5MSw3ICsyOTUsNyBAQCBlcnJf cmVmY291bnQ6CiBzdGF0aWMgdm9pZCBtdGtfZHNpX2Nsa191bHBfbW9kZV9lbnRlcihzdHJ1Y3Qg bXRrX2RzaSAqZHNpKQogewogCW10a19kc2lfbWFzayhkc2ksIERTSV9QSFlfTENDT04sIExDX0hT X1RYX0VOLCAwKTsKLQltdGtfZHNpX21hc2soZHNpLCBEU0lfUEhZX0xDQ09OLCBMQ19VTFBNX0VO LCAwKTsKKwltdGtfZHNpX21hc2soZHNpLCBEU0lfUEhZX0xDQ09OLCBMQ19VTFBNX0VOLCBMQ19V TFBNX0VOKTsKIH0KIAogc3RhdGljIHZvaWQgbXRrX2RzaV9jbGtfdWxwX21vZGVfbGVhdmUoc3Ry dWN0IG10a19kc2kgKmRzaSkKQEAgLTMwNCw3ICszMDgsNyBAQCBzdGF0aWMgdm9pZCBtdGtfZHNp X2Nsa191bHBfbW9kZV9sZWF2ZShzdHJ1Y3QgbXRrX2RzaSAqZHNpKQogc3RhdGljIHZvaWQgbXRr X2RzaV9sYW5lMF91bHBfbW9kZV9lbnRlcihzdHJ1Y3QgbXRrX2RzaSAqZHNpKQogewogCW10a19k c2lfbWFzayhkc2ksIERTSV9QSFlfTEQwQ09OLCBMRDBfSFNfVFhfRU4sIDApOwotCW10a19kc2lf bWFzayhkc2ksIERTSV9QSFlfTEQwQ09OLCBMRDBfVUxQTV9FTiwgMCk7CisJbXRrX2RzaV9tYXNr KGRzaSwgRFNJX1BIWV9MRDBDT04sIExEMF9VTFBNX0VOLCBMRDBfVUxQTV9FTik7CiB9CiAKIHN0 YXRpYyB2b2lkIG10a19kc2lfbGFuZTBfdWxwX21vZGVfbGVhdmUoc3RydWN0IG10a19kc2kgKmRz aSkKQEAgLTM0MCwxMSArMzQ0LDIxIEBAIHN0YXRpYyB2b2lkIG10a19kc2lfc2V0X21vZGUoc3Ry dWN0IG10a19kc2kgKmRzaSkKIAkJaWYgKChkc2ktPm1vZGVfZmxhZ3MgJiBNSVBJX0RTSV9NT0RF X1ZJREVPX0JVUlNUKSAmJgogCQkgICAgIShkc2ktPm1vZGVfZmxhZ3MgJiBNSVBJX0RTSV9NT0RF X1ZJREVPX1NZTkNfUFVMU0UpKQogCQkJdmlkX21vZGUgPSBCVVJTVF9NT0RFOworCQllbHNlCisJ CQl2aWRfbW9kZSA9IFNZTkNfRVZFTlRfTU9ERTsKIAl9CiAKIAl3cml0ZWwodmlkX21vZGUsIGRz aS0+cmVncyArIERTSV9NT0RFX0NUUkwpOwogfQogCitzdGF0aWMgdm9pZCBtdGtfZHNpX3NldF92 bV9jbWQoc3RydWN0IG10a19kc2kgKmRzaSkKK3sKKwl3cml0ZWwoMHgzYywgZHNpLT5yZWdzICsg RFNJX01FTV9DT05USSk7CisKKwltdGtfZHNpX21hc2soZHNpLCBEU0lfVk1fQ01EX0NPTiwgVk1f Q01EX0VOLCBWTV9DTURfRU4pOworCW10a19kc2lfbWFzayhkc2ksIERTSV9WTV9DTURfQ09OLCBU U19WRlBfRU4sIFRTX1ZGUF9FTik7Cit9CisKIHN0YXRpYyB2b2lkIG10a19kc2lfcHNfY29udHJv bF92YWN0KHN0cnVjdCBtdGtfZHNpICpkc2kpCiB7CiAJc3RydWN0IHZpZGVvbW9kZSAqdm0gPSAm ZHNpLT52bTsKQEAgLTQwMSw2ICs0MTUsOSBAQCBzdGF0aWMgdm9pZCBtdGtfZHNpX3J4dHhfY29u dHJvbChzdHJ1Y3QgbXRrX2RzaSAqZHNpKQogCQlicmVhazsKIAl9CiAKKwl0bXBfcmVnIHw9IChk c2ktPm1vZGVfZmxhZ3MgJiBNSVBJX0RTSV9DTE9DS19OT05fQ09OVElOVU9VUykgPDwgNjsKKwl0 bXBfcmVnIHw9IChkc2ktPm1vZGVfZmxhZ3MgJiBNSVBJX0RTSV9NT0RFX0VPVF9QQUNLRVQpID4+ IDM7CisKIAl3cml0ZWwodG1wX3JlZywgZHNpLT5yZWdzICsgRFNJX1RYUlhfQ1RSTCk7CiB9CiAK QEAgLTQ3OSw2ICs0OTYsMTYgQEAgc3RhdGljIHZvaWQgbXRrX2RzaV9zdGFydChzdHJ1Y3QgbXRr X2RzaSAqZHNpKQogCXdyaXRlbCgxLCBkc2ktPnJlZ3MgKyBEU0lfU1RBUlQpOwogfQogCitzdGF0 aWMgdm9pZCBtdGtfZHNpX3N0b3Aoc3RydWN0IG10a19kc2kgKmRzaSkKK3sKKwl3cml0ZWwoMCwg ZHNpLT5yZWdzICsgRFNJX1NUQVJUKTsKK30KKworc3RhdGljIHZvaWQgbXRrX2RzaV9zZXRfY21k X21vZGUoc3RydWN0IG10a19kc2kgKmRzaSkKK3sKKwl3cml0ZWwoQ01EX01PREUsIGRzaS0+cmVn cyArIERTSV9NT0RFX0NUUkwpOworfQorCiBzdGF0aWMgdm9pZCBtdGtfZHNpX3NldF9pbnRlcnJ1 cHRfZW5hYmxlKHN0cnVjdCBtdGtfZHNpICpkc2kpCiB7CiAJdTMyIGludGVuID0gRFNJX0lOVF9B TExfQklUUzsKQEAgLTUyMSw2ICs1NDgsMjUgQEAgc3RhdGljIGlycXJldHVybl90IG10a19kc2lf aXJxKGludCBpcnEsIHZvaWQgKmRldl9pZCkKIAlyZXR1cm4gSVJRX0hBTkRMRUQ7CiB9CiAKK3N0 YXRpYyB2b2lkIG10a19kc2lfc3dpdGNoX3RvX2NtZF9tb2RlKHN0cnVjdCBtdGtfZHNpICpkc2kp Cit7CisJczMyIHJldCA9IDA7CisJdW5zaWduZWQgbG9uZyB0aW1lb3V0ID0gbXNlY3NfdG9famlm Zmllcyg1MDApOworCisJbXRrX2RzaV9pcnFfZGF0YV9jbGVhcihkc2ksIFZNX0RPTkVfSU5UX0ZM QUcpOworCW10a19kc2lfc2V0X2NtZF9tb2RlKGRzaSk7CisKKwlyZXQgPSB3YWl0X2V2ZW50X2lu dGVycnVwdGlibGVfdGltZW91dChfZHNpX2lycV93YWl0X3F1ZXVlLAorCQkJCQkgICAgICAgZHNp LT5pcnFfZGF0YSAmIFZNX0RPTkVfSU5UX0ZMQUcsCisJCQkJCSAgICAgICB0aW1lb3V0KTsKKwlp ZiAocmV0ID09IDApIHsKKwkJZGV2X2luZm8oZHNpLT5kZXYsICJkc2kgd2FpdCBlbmdpbmUgaWRs ZSB0aW1lb3V0XG4iKTsKKworCQltdGtfZHNpX2VuYWJsZShkc2kpOworCQltdGtfZHNpX3Jlc2V0 X2VuZ2luZShkc2kpOworCX0KK30KKwogc3RhdGljIHZvaWQgbXRrX2RzaV9wb3dlcm9mZihzdHJ1 Y3QgbXRrX2RzaSAqZHNpKQogewogCWlmIChXQVJOX09OKGRzaS0+cmVmY291bnQgPT0gMCkpCkBA IC01MjksNiArNTc1LDE3IEBAIHN0YXRpYyB2b2lkIG10a19kc2lfcG93ZXJvZmYoc3RydWN0IG10 a19kc2kgKmRzaSkKIAlpZiAoLS1kc2ktPnJlZmNvdW50ICE9IDApCiAJCXJldHVybjsKIAorCW10 a19kc2lfc3dpdGNoX3RvX2NtZF9tb2RlKGRzaSk7CisKKwlpZiAoZHNpLT5wYW5lbCkgeworCQlp ZiAoZHJtX3BhbmVsX3VucHJlcGFyZShkc2ktPnBhbmVsKSkgeworCQkJRFJNX0VSUk9SKCJmYWls ZWQgdG8gdW5wcmVwYXJlIHRoZSBwYW5lbFxuIik7CisJCQlyZXR1cm47CisJCX0KKwl9CisKKwlt dGtfZHNpX3Jlc2V0X2VuZ2luZShkc2kpOworCiAJbXRrX2RzaV9sYW5lMF91bHBfbW9kZV9lbnRl cihkc2kpOwogCW10a19kc2lfY2xrX3VscF9tb2RlX2VudGVyKGRzaSk7CiAKQEAgLTU0NywyOSAr NjA0LDM3IEBAIHN0YXRpYyB2b2lkIG10a19vdXRwdXRfZHNpX2VuYWJsZShzdHJ1Y3QgbXRrX2Rz aSAqZHNpKQogCWlmIChkc2ktPmVuYWJsZWQpCiAJCXJldHVybjsKIAotCWlmIChkc2ktPnBhbmVs KSB7Ci0JCWlmIChkcm1fcGFuZWxfcHJlcGFyZShkc2ktPnBhbmVsKSkgewotCQkJRFJNX0VSUk9S KCJmYWlsZWQgdG8gc2V0dXAgdGhlIHBhbmVsXG4iKTsKLQkJCXJldHVybjsKLQkJfQotCX0KLQog CXJldCA9IG10a19kc2lfcG93ZXJvbihkc2kpOwogCWlmIChyZXQgPCAwKSB7CiAJCURSTV9FUlJP UigiZmFpbGVkIHRvIHBvd2VyIG9uIGRzaVxuIik7CiAJCXJldHVybjsKIAl9CiAKKwl1c2xlZXBf cmFuZ2UoMjAwMDAsIDIxMDAwKTsKKwogCW10a19kc2lfcnh0eF9jb250cm9sKGRzaSk7CisJbXRr X2RzaV9waHlfdGltY29uZmlnKGRzaSk7CisJbXRrX2RzaV9wc19jb250cm9sX3ZhY3QoZHNpKTsK KwltdGtfZHNpX3NldF92bV9jbWQoZHNpKTsKKwltdGtfZHNpX2NvbmZpZ192ZG9fdGltaW5nKGRz aSk7CisJbXRrX2RzaV9zZXRfaW50ZXJydXB0X2VuYWJsZShkc2kpOwogCisJbXRrX2RzaV9lbmFi bGUoZHNpKTsKIAltdGtfZHNpX2Nsa191bHBfbW9kZV9sZWF2ZShkc2kpOwogCW10a19kc2lfbGFu ZTBfdWxwX21vZGVfbGVhdmUoZHNpKTsKIAltdGtfZHNpX2Nsa19oc19tb2RlKGRzaSwgMCk7Ci0J bXRrX2RzaV9zZXRfbW9kZShkc2kpOwogCi0JbXRrX2RzaV9wc19jb250cm9sX3ZhY3QoZHNpKTsK LQltdGtfZHNpX2NvbmZpZ192ZG9fdGltaW5nKGRzaSk7Ci0JbXRrX2RzaV9zZXRfaW50ZXJydXB0 X2VuYWJsZShkc2kpOworCWlmIChkc2ktPnBhbmVsKSB7CisJCWlmIChkcm1fcGFuZWxfcHJlcGFy ZShkc2ktPnBhbmVsKSkgeworCQkJRFJNX0VSUk9SKCJmYWlsZWQgdG8gcHJlcGFyZSB0aGUgcGFu ZWxcbiIpOworCQkJcmV0dXJuOworCQl9CisKKwkJaWYgKGRybV9wYW5lbF9lbmFibGUoZHNpLT5w YW5lbCkpIHsKKwkJCURSTV9FUlJPUigiZmFpbGVkIHRvIGVuYWJsZSB0aGUgcGFuZWxcbiIpOwor CQkJcmV0dXJuOworCQl9CisJfQogCiAJbXRrX2RzaV9zZXRfbW9kZShkc2kpOwogCW10a19kc2lf Y2xrX2hzX21vZGUoZHNpLCAxKTsKQEAgLTU5MSw2ICs2NTYsNyBAQCBzdGF0aWMgdm9pZCBtdGtf b3V0cHV0X2RzaV9kaXNhYmxlKHN0cnVjdCBtdGtfZHNpICpkc2kpCiAJCX0KIAl9CiAKKwltdGtf ZHNpX3N0b3AoZHNpKTsKIAltdGtfZHNpX3Bvd2Vyb2ZmKGRzaSk7CiAKIAlkc2ktPmVuYWJsZWQg PSBmYWxzZTsKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfbWlwaV90 eC5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19taXBpX3R4LmMKaW5kZXggMTA4ZDMx YS4uMzRlOTVjNiAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19taXBp X3R4LmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19taXBpX3R4LmMKQEAgLTE3 Nyw3ICsxNzcsOSBAQCBzdGF0aWMgaW50IG10a19taXBpX3R4X3BsbF9wcmVwYXJlKHN0cnVjdCBj bGtfaHcgKmh3KQogCiAJZGV2X2RiZyhtaXBpX3R4LT5kZXYsICJwcmVwYXJlOiAldSBIelxuIiwg bWlwaV90eC0+ZGF0YV9yYXRlKTsKIAotCWlmIChtaXBpX3R4LT5kYXRhX3JhdGUgPj0gNTAwMDAw MDAwKSB7CisJaWYgKG1pcGlfdHgtPmRhdGFfcmF0ZSA+IDEyNTAwMDAwMDApIHsKKwkJcmV0dXJu IC1FSU5WQUw7CisJfSBlbHNlIGlmIChtaXBpX3R4LT5kYXRhX3JhdGUgPj0gNTAwMDAwMDAwKSB7 CiAJCXR4ZGl2ID0gMTsKIAkJdHhkaXYwID0gMDsKIAkJdHhkaXYxID0gMDsKQEAgLTIwMSw2ICsy MDMsMTAgQEAgc3RhdGljIGludCBtdGtfbWlwaV90eF9wbGxfcHJlcGFyZShzdHJ1Y3QgY2xrX2h3 ICpodykKIAkJcmV0dXJuIC1FSU5WQUw7CiAJfQogCisJbXRrX21pcGlfdHhfdXBkYXRlX2JpdHMo bWlwaV90eCwgTUlQSVRYX0RTSV9UT1BfQ09OLAorCQkJCVJHX0RTSV9MTlRfSU1QX0NBTF9DT0RF IHwgUkdfRFNJX0xOVF9IU19CSUFTX0VOLAorCQkJCSg4IDw8IDQpIHwgUkdfRFNJX0xOVF9IU19C SUFTX0VOKTsKKwogCW10a19taXBpX3R4X3VwZGF0ZV9iaXRzKG1pcGlfdHgsIE1JUElUWF9EU0lf QkdfQ09OLAogCQkJCVJHX0RTSV9WT1VUX01TSyB8CiAJCQkJUkdfRFNJX0JHX0NLRU4gfCBSR19E U0lfQkdfQ09SRV9FTiwKQEAgLTIxMCwyNCArMjE2LDE4IEBAIHN0YXRpYyBpbnQgbXRrX21pcGlf dHhfcGxsX3ByZXBhcmUoc3RydWN0IGNsa19odyAqaHcpCiAKIAl1c2xlZXBfcmFuZ2UoMzAsIDEw MCk7CiAKLQltdGtfbWlwaV90eF91cGRhdGVfYml0cyhtaXBpX3R4LCBNSVBJVFhfRFNJX1RPUF9D T04sCi0JCQkJUkdfRFNJX0xOVF9JTVBfQ0FMX0NPREUgfCBSR19EU0lfTE5UX0hTX0JJQVNfRU4s Ci0JCQkJKDggPDwgNCkgfCBSR19EU0lfTE5UX0hTX0JJQVNfRU4pOwotCi0JbXRrX21pcGlfdHhf c2V0X2JpdHMobWlwaV90eCwgTUlQSVRYX0RTSV9DT04sCi0JCQkgICAgIFJHX0RTSV9DS0dfTERP T1VUX0VOIHwgUkdfRFNJX0xET0NPUkVfRU4pOworCW10a19taXBpX3R4X3VwZGF0ZV9iaXRzKG1p cGlfdHgsIE1JUElUWF9EU0lfQ09OLAorCQkJCVJHX0RTSV9DS0dfTERPT1VUX0VOIHwgUkdfRFNJ X0xET0NPUkVfRU4sCisJCQkJUkdfRFNJX0NLR19MRE9PVVRfRU4gfCBSR19EU0lfTERPQ09SRV9F Tik7CiAKIAltdGtfbWlwaV90eF91cGRhdGVfYml0cyhtaXBpX3R4LCBNSVBJVFhfRFNJX1BMTF9Q V1IsCiAJCQkJUkdfRFNJX01QUExMX1NETV9QV1JfT04gfAogCQkJCVJHX0RTSV9NUFBMTF9TRE1f SVNPX0VOLAogCQkJCVJHX0RTSV9NUFBMTF9TRE1fUFdSX09OKTsKIAotCW10a19taXBpX3R4X2Ns ZWFyX2JpdHMobWlwaV90eCwgTUlQSVRYX0RTSV9QTExfQ09OMCwKLQkJCSAgICAgICBSR19EU0lf TVBQTExfUExMX0VOKTsKLQogCW10a19taXBpX3R4X3VwZGF0ZV9iaXRzKG1pcGlfdHgsIE1JUElU WF9EU0lfUExMX0NPTjAsCi0JCQkJUkdfRFNJX01QUExMX1RYRElWMCB8IFJHX0RTSV9NUFBMTF9U WERJVjEgfAotCQkJCVJHX0RTSV9NUFBMTF9QUkVESVYsCisJCQkJUkdfRFNJX01QUExMX1BSRURJ ViB8IFJHX0RTSV9NUFBMTF9UWERJVjAgfAorCQkJCVJHX0RTSV9NUFBMTF9UWERJVjEgfCBSR19E U0lfTVBQTExfUE9TRElWLAogCQkJCSh0eGRpdjAgPDwgMykgfCAodHhkaXYxIDw8IDUpKTsKIAog CS8qCkBAIC0yNDIsMTAgKzI0MiwxMiBAQCBzdGF0aWMgaW50IG10a19taXBpX3R4X3BsbF9wcmVw YXJlKHN0cnVjdCBjbGtfaHcgKmh3KQogCQkgICAgICAyNjAwMDAwMCk7CiAJd3JpdGVsKHBjdywg bWlwaV90eC0+cmVncyArIE1JUElUWF9EU0lfUExMX0NPTjIpOwogCi0JbXRrX21pcGlfdHhfc2V0 X2JpdHMobWlwaV90eCwgTUlQSVRYX0RTSV9QTExfQ09OMSwKLQkJCSAgICAgUkdfRFNJX01QUExM X1NETV9GUkFfRU4pOworCW10a19taXBpX3R4X3VwZGF0ZV9iaXRzKG1pcGlfdHgsIE1JUElUWF9E U0lfUExMX0NPTjEsCisJCQkJUkdfRFNJX01QUExMX1NETV9GUkFfRU4sCisJCQkJUkdfRFNJX01Q UExMX1NETV9GUkFfRU4pOwogCi0JbXRrX21pcGlfdHhfc2V0X2JpdHMobWlwaV90eCwgTUlQSVRY X0RTSV9QTExfQ09OMCwgUkdfRFNJX01QUExMX1BMTF9FTik7CisJbXRrX21pcGlfdHhfdXBkYXRl X2JpdHMobWlwaV90eCwgTUlQSVRYX0RTSV9QTExfQ09OMCwKKwkJCQlSR19EU0lfTVBQTExfUExM X0VOLCBSR19EU0lfTVBQTExfUExMX0VOKTsKIAogCXVzbGVlcF9yYW5nZSgyMCwgMTAwKTsKIAot LSAKMS45LjEKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f CmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpo dHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: yt.shen@mediatek.com (YT Shen) Date: Fri, 2 Sep 2016 19:24:43 +0800 Subject: [PATCH v7 8/9] drm/mediatek: update DSI sub driver flow In-Reply-To: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> Message-ID: <1472815484-43821-9-git-send-email-yt.shen@mediatek.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This patch update enable/disable flow of DSI module and MIPI TX module Signed-off-by: shaoming chen Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_dsi.c | 102 +++++++++++++++++++++++++++------ drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 32 ++++++----- 2 files changed, 101 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 1103ff4..f807621 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -95,6 +95,8 @@ #define DSI_RACK 0x84 #define RACK BIT(0) +#define DSI_MEM_CONTI 0x90 + #define DSI_PHY_LCCON 0x104 #define LC_HS_TX_EN BIT(0) #define LC_ULPM_EN BIT(1) @@ -127,6 +129,10 @@ #define CLK_HS_POST (0xff << 8) #define CLK_HS_EXIT (0xff << 16) +#define DSI_VM_CMD_CON 0x130 +#define VM_CMD_EN BIT(0) +#define TS_VFP_EN BIT(5) + #define DSI_CMDQ0 0x180 #define CONFIG (0xff << 0) #define SHORT_PACKET 0 @@ -251,7 +257,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) * mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi. * we set mipi_ratio is 1.05. */ - dsi->data_rate = dsi->vm.pixelclock * 3 * 21 / (1 * 1000 * 10); + dsi->data_rate = dsi->vm.pixelclock * 12 * 21; + dsi->data_rate /= (dsi->lanes * 1000 * 10); + dev_info(dev, "set mipitx's data rate: %dMHz\n", dsi->data_rate); ret = clk_set_rate(dsi->hs_clk, dsi->data_rate * 1000000); if (ret < 0) { @@ -273,10 +281,6 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) goto err_disable_engine_clk; } - mtk_dsi_enable(dsi); - mtk_dsi_reset_engine(dsi); - mtk_dsi_phy_timconfig(dsi); - return 0; err_disable_engine_clk: @@ -291,7 +295,7 @@ err_refcount: static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi) { mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); - mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); + mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, LC_ULPM_EN); } static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) @@ -304,7 +308,7 @@ static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi) { mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0); - mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); + mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, LD0_ULPM_EN); } static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi) @@ -340,11 +344,21 @@ static void mtk_dsi_set_mode(struct mtk_dsi *dsi) if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) vid_mode = BURST_MODE; + else + vid_mode = SYNC_EVENT_MODE; } writel(vid_mode, dsi->regs + DSI_MODE_CTRL); } +static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) +{ + writel(0x3c, dsi->regs + DSI_MEM_CONTI); + + mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN); + mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); +} + static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) { struct videomode *vm = &dsi->vm; @@ -401,6 +415,9 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) break; } + tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; + tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); } @@ -479,6 +496,16 @@ static void mtk_dsi_start(struct mtk_dsi *dsi) writel(1, dsi->regs + DSI_START); } +static void mtk_dsi_stop(struct mtk_dsi *dsi) +{ + writel(0, dsi->regs + DSI_START); +} + +static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi) +{ + writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL); +} + static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi) { u32 inten = DSI_INT_ALL_BITS; @@ -521,6 +548,25 @@ static irqreturn_t mtk_dsi_irq(int irq, void *dev_id) return IRQ_HANDLED; } +static void mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi) +{ + s32 ret = 0; + unsigned long timeout = msecs_to_jiffies(500); + + mtk_dsi_irq_data_clear(dsi, VM_DONE_INT_FLAG); + mtk_dsi_set_cmd_mode(dsi); + + ret = wait_event_interruptible_timeout(_dsi_irq_wait_queue, + dsi->irq_data & VM_DONE_INT_FLAG, + timeout); + if (ret == 0) { + dev_info(dsi->dev, "dsi wait engine idle timeout\n"); + + mtk_dsi_enable(dsi); + mtk_dsi_reset_engine(dsi); + } +} + static void mtk_dsi_poweroff(struct mtk_dsi *dsi) { if (WARN_ON(dsi->refcount == 0)) @@ -529,6 +575,17 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) if (--dsi->refcount != 0) return; + mtk_dsi_switch_to_cmd_mode(dsi); + + if (dsi->panel) { + if (drm_panel_unprepare(dsi->panel)) { + DRM_ERROR("failed to unprepare the panel\n"); + return; + } + } + + mtk_dsi_reset_engine(dsi); + mtk_dsi_lane0_ulp_mode_enter(dsi); mtk_dsi_clk_ulp_mode_enter(dsi); @@ -547,29 +604,37 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi) if (dsi->enabled) return; - if (dsi->panel) { - if (drm_panel_prepare(dsi->panel)) { - DRM_ERROR("failed to setup the panel\n"); - return; - } - } - ret = mtk_dsi_poweron(dsi); if (ret < 0) { DRM_ERROR("failed to power on dsi\n"); return; } + usleep_range(20000, 21000); + mtk_dsi_rxtx_control(dsi); + mtk_dsi_phy_timconfig(dsi); + mtk_dsi_ps_control_vact(dsi); + mtk_dsi_set_vm_cmd(dsi); + mtk_dsi_config_vdo_timing(dsi); + mtk_dsi_set_interrupt_enable(dsi); + mtk_dsi_enable(dsi); mtk_dsi_clk_ulp_mode_leave(dsi); mtk_dsi_lane0_ulp_mode_leave(dsi); mtk_dsi_clk_hs_mode(dsi, 0); - mtk_dsi_set_mode(dsi); - mtk_dsi_ps_control_vact(dsi); - mtk_dsi_config_vdo_timing(dsi); - mtk_dsi_set_interrupt_enable(dsi); + if (dsi->panel) { + if (drm_panel_prepare(dsi->panel)) { + DRM_ERROR("failed to prepare the panel\n"); + return; + } + + if (drm_panel_enable(dsi->panel)) { + DRM_ERROR("failed to enable the panel\n"); + return; + } + } mtk_dsi_set_mode(dsi); mtk_dsi_clk_hs_mode(dsi, 1); @@ -591,6 +656,7 @@ static void mtk_output_dsi_disable(struct mtk_dsi *dsi) } } + mtk_dsi_stop(dsi); mtk_dsi_poweroff(dsi); dsi->enabled = false; diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index 108d31a..34e95c6 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -177,7 +177,9 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate); - if (mipi_tx->data_rate >= 500000000) { + if (mipi_tx->data_rate > 1250000000) { + return -EINVAL; + } else if (mipi_tx->data_rate >= 500000000) { txdiv = 1; txdiv0 = 0; txdiv1 = 0; @@ -201,6 +203,10 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) return -EINVAL; } + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON, + RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN, + (8 << 4) | RG_DSI_LNT_HS_BIAS_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON, RG_DSI_VOUT_MSK | RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN, @@ -210,24 +216,18 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) usleep_range(30, 100); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON, - RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN, - (8 << 4) | RG_DSI_LNT_HS_BIAS_EN); - - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON, - RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_CON, + RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN, + RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR, RG_DSI_MPPLL_SDM_PWR_ON | RG_DSI_MPPLL_SDM_ISO_EN, RG_DSI_MPPLL_SDM_PWR_ON); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, - RG_DSI_MPPLL_PLL_EN); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0, - RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 | - RG_DSI_MPPLL_PREDIV, + RG_DSI_MPPLL_PREDIV | RG_DSI_MPPLL_TXDIV0 | + RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_POSDIV, (txdiv0 << 3) | (txdiv1 << 5)); /* @@ -242,10 +242,12 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) 26000000); writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1, - RG_DSI_MPPLL_SDM_FRA_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON1, + RG_DSI_MPPLL_SDM_FRA_EN, + RG_DSI_MPPLL_SDM_FRA_EN); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0, + RG_DSI_MPPLL_PLL_EN, RG_DSI_MPPLL_PLL_EN); usleep_range(20, 100); -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932094AbcIBL0Z (ORCPT ); Fri, 2 Sep 2016 07:26:25 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:52897 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753871AbcIBL0V (ORCPT ); Fri, 2 Sep 2016 07:26:21 -0400 From: YT Shen To: , Philipp Zabel CC: David Airlie , Matthias Brugger , YT Shen , Daniel Kurtz , Mao Huang , CK Hu , Bibby Hsieh , Daniel Vetter , Thierry Reding , Jie Qiu , Maxime Ripard , Chris Wilson , shaoming chen , Jitao Shi , Boris Brezillon , Dan Carpenter , , , , , Sascha Hauer , , Subject: [PATCH v7 8/9] drm/mediatek: update DSI sub driver flow Date: Fri, 2 Sep 2016 19:24:43 +0800 Message-ID: <1472815484-43821-9-git-send-email-yt.shen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch update enable/disable flow of DSI module and MIPI TX module Signed-off-by: shaoming chen Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_dsi.c | 102 +++++++++++++++++++++++++++------ drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 32 ++++++----- 2 files changed, 101 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 1103ff4..f807621 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -95,6 +95,8 @@ #define DSI_RACK 0x84 #define RACK BIT(0) +#define DSI_MEM_CONTI 0x90 + #define DSI_PHY_LCCON 0x104 #define LC_HS_TX_EN BIT(0) #define LC_ULPM_EN BIT(1) @@ -127,6 +129,10 @@ #define CLK_HS_POST (0xff << 8) #define CLK_HS_EXIT (0xff << 16) +#define DSI_VM_CMD_CON 0x130 +#define VM_CMD_EN BIT(0) +#define TS_VFP_EN BIT(5) + #define DSI_CMDQ0 0x180 #define CONFIG (0xff << 0) #define SHORT_PACKET 0 @@ -251,7 +257,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) * mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi. * we set mipi_ratio is 1.05. */ - dsi->data_rate = dsi->vm.pixelclock * 3 * 21 / (1 * 1000 * 10); + dsi->data_rate = dsi->vm.pixelclock * 12 * 21; + dsi->data_rate /= (dsi->lanes * 1000 * 10); + dev_info(dev, "set mipitx's data rate: %dMHz\n", dsi->data_rate); ret = clk_set_rate(dsi->hs_clk, dsi->data_rate * 1000000); if (ret < 0) { @@ -273,10 +281,6 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) goto err_disable_engine_clk; } - mtk_dsi_enable(dsi); - mtk_dsi_reset_engine(dsi); - mtk_dsi_phy_timconfig(dsi); - return 0; err_disable_engine_clk: @@ -291,7 +295,7 @@ err_refcount: static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi) { mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); - mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); + mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, LC_ULPM_EN); } static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) @@ -304,7 +308,7 @@ static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi) { mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0); - mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); + mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, LD0_ULPM_EN); } static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi) @@ -340,11 +344,21 @@ static void mtk_dsi_set_mode(struct mtk_dsi *dsi) if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) vid_mode = BURST_MODE; + else + vid_mode = SYNC_EVENT_MODE; } writel(vid_mode, dsi->regs + DSI_MODE_CTRL); } +static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) +{ + writel(0x3c, dsi->regs + DSI_MEM_CONTI); + + mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN); + mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); +} + static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) { struct videomode *vm = &dsi->vm; @@ -401,6 +415,9 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) break; } + tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; + tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); } @@ -479,6 +496,16 @@ static void mtk_dsi_start(struct mtk_dsi *dsi) writel(1, dsi->regs + DSI_START); } +static void mtk_dsi_stop(struct mtk_dsi *dsi) +{ + writel(0, dsi->regs + DSI_START); +} + +static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi) +{ + writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL); +} + static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi) { u32 inten = DSI_INT_ALL_BITS; @@ -521,6 +548,25 @@ static irqreturn_t mtk_dsi_irq(int irq, void *dev_id) return IRQ_HANDLED; } +static void mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi) +{ + s32 ret = 0; + unsigned long timeout = msecs_to_jiffies(500); + + mtk_dsi_irq_data_clear(dsi, VM_DONE_INT_FLAG); + mtk_dsi_set_cmd_mode(dsi); + + ret = wait_event_interruptible_timeout(_dsi_irq_wait_queue, + dsi->irq_data & VM_DONE_INT_FLAG, + timeout); + if (ret == 0) { + dev_info(dsi->dev, "dsi wait engine idle timeout\n"); + + mtk_dsi_enable(dsi); + mtk_dsi_reset_engine(dsi); + } +} + static void mtk_dsi_poweroff(struct mtk_dsi *dsi) { if (WARN_ON(dsi->refcount == 0)) @@ -529,6 +575,17 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) if (--dsi->refcount != 0) return; + mtk_dsi_switch_to_cmd_mode(dsi); + + if (dsi->panel) { + if (drm_panel_unprepare(dsi->panel)) { + DRM_ERROR("failed to unprepare the panel\n"); + return; + } + } + + mtk_dsi_reset_engine(dsi); + mtk_dsi_lane0_ulp_mode_enter(dsi); mtk_dsi_clk_ulp_mode_enter(dsi); @@ -547,29 +604,37 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi) if (dsi->enabled) return; - if (dsi->panel) { - if (drm_panel_prepare(dsi->panel)) { - DRM_ERROR("failed to setup the panel\n"); - return; - } - } - ret = mtk_dsi_poweron(dsi); if (ret < 0) { DRM_ERROR("failed to power on dsi\n"); return; } + usleep_range(20000, 21000); + mtk_dsi_rxtx_control(dsi); + mtk_dsi_phy_timconfig(dsi); + mtk_dsi_ps_control_vact(dsi); + mtk_dsi_set_vm_cmd(dsi); + mtk_dsi_config_vdo_timing(dsi); + mtk_dsi_set_interrupt_enable(dsi); + mtk_dsi_enable(dsi); mtk_dsi_clk_ulp_mode_leave(dsi); mtk_dsi_lane0_ulp_mode_leave(dsi); mtk_dsi_clk_hs_mode(dsi, 0); - mtk_dsi_set_mode(dsi); - mtk_dsi_ps_control_vact(dsi); - mtk_dsi_config_vdo_timing(dsi); - mtk_dsi_set_interrupt_enable(dsi); + if (dsi->panel) { + if (drm_panel_prepare(dsi->panel)) { + DRM_ERROR("failed to prepare the panel\n"); + return; + } + + if (drm_panel_enable(dsi->panel)) { + DRM_ERROR("failed to enable the panel\n"); + return; + } + } mtk_dsi_set_mode(dsi); mtk_dsi_clk_hs_mode(dsi, 1); @@ -591,6 +656,7 @@ static void mtk_output_dsi_disable(struct mtk_dsi *dsi) } } + mtk_dsi_stop(dsi); mtk_dsi_poweroff(dsi); dsi->enabled = false; diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index 108d31a..34e95c6 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -177,7 +177,9 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate); - if (mipi_tx->data_rate >= 500000000) { + if (mipi_tx->data_rate > 1250000000) { + return -EINVAL; + } else if (mipi_tx->data_rate >= 500000000) { txdiv = 1; txdiv0 = 0; txdiv1 = 0; @@ -201,6 +203,10 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) return -EINVAL; } + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON, + RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN, + (8 << 4) | RG_DSI_LNT_HS_BIAS_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON, RG_DSI_VOUT_MSK | RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN, @@ -210,24 +216,18 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) usleep_range(30, 100); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON, - RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN, - (8 << 4) | RG_DSI_LNT_HS_BIAS_EN); - - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON, - RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_CON, + RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN, + RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR, RG_DSI_MPPLL_SDM_PWR_ON | RG_DSI_MPPLL_SDM_ISO_EN, RG_DSI_MPPLL_SDM_PWR_ON); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, - RG_DSI_MPPLL_PLL_EN); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0, - RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 | - RG_DSI_MPPLL_PREDIV, + RG_DSI_MPPLL_PREDIV | RG_DSI_MPPLL_TXDIV0 | + RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_POSDIV, (txdiv0 << 3) | (txdiv1 << 5)); /* @@ -242,10 +242,12 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) 26000000); writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1, - RG_DSI_MPPLL_SDM_FRA_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON1, + RG_DSI_MPPLL_SDM_FRA_EN, + RG_DSI_MPPLL_SDM_FRA_EN); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0, + RG_DSI_MPPLL_PLL_EN, RG_DSI_MPPLL_PLL_EN); usleep_range(20, 100); -- 1.9.1