From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37979) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1biK40-0007ri-RV for qemu-devel@nongnu.org; Fri, 09 Sep 2016 07:33:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1biK3x-0007oY-HU for qemu-devel@nongnu.org; Fri, 09 Sep 2016 07:33:44 -0400 Message-ID: <1473420805.8689.171.camel@kernel.crashing.org> From: Benjamin Herrenschmidt Date: Fri, 09 Sep 2016 21:33:25 +1000 In-Reply-To: <1473417926-14263-2-git-send-email-nikunj@linux.vnet.ibm.com> References: <1473417926-14263-1-git-send-email-nikunj@linux.vnet.ibm.com> <1473417926-14263-2-git-send-email-nikunj@linux.vnet.ibm.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH RFC v1 2/3] target-ppc: add flag in chech_tlb_flush() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania , qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Cc: alex.bennee@linaro.org, qemu-devel@nongnu.org, rth@twiddle.net On Fri, 2016-09-09 at 16:15 +0530, Nikunj A Dadhania wrote: > The flag will be used to indicate whether broadcast tlb flush is > needed > or not. >=20 > Signed-off-by: Nikunj A Dadhania > --- > =C2=A0hw/ppc/spapr_hcall.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A04 = ++-- > =C2=A0target-ppc/excp_helper.c |=C2=A0=C2=A04 ++-- > =C2=A0target-ppc/helper.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2= =A02 +- > =C2=A0target-ppc/helper_regs.h |=C2=A0=C2=A04 ++-- > =C2=A0target-ppc/mmu_helper.c=C2=A0=C2=A0|=C2=A0=C2=A04 ++-- > =C2=A0target-ppc/translate.c=C2=A0=C2=A0=C2=A0| 13 +++++++------ > =C2=A06 files changed, 16 insertions(+), 15 deletions(-) >=20 > diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c > index 73af112..ef12ea0 100644 > --- a/hw/ppc/spapr_hcall.c > +++ b/hw/ppc/spapr_hcall.c > @@ -201,7 +201,7 @@ static target_ulong h_remove(PowerPCCPU *cpu, > sPAPRMachineState *spapr, > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0switch (ret) { > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case REMOVE_SUCCESS: > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env); > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env, 1= ); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0return H_SUCCESS; > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case REMOVE_NOT_FOUND: > @@ -282,7 +282,7 @@ static target_ulong h_bulk_remove(PowerPCCPU > *cpu, sPAPRMachineState *spapr, > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > =C2=A0 exit: > -=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env); > +=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env, 1); > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0return rc; > =C2=A0} > diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c > index 04ed4da..09947e4 100644 > --- a/target-ppc/excp_helper.c > +++ b/target-ppc/excp_helper.c > @@ -711,7 +711,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, > int excp_model, int excp) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* Any interrupt is context synchronizing= , check if TCG TLB > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* needs a delayed flush on ppc64 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/ > -=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env); > +=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env, 1); No that one is local > =C2=A0} > =C2=A0 > =C2=A0void ppc_cpu_do_interrupt(CPUState *cs) > @@ -973,7 +973,7 @@ static inline void do_rfi(CPUPPCState *env, > target_ulong nip, target_ulong msr) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0cs->interrupt_request |=3D CPU_INTERRUPT_= EXITTB; > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* Context synchronizing: check if TCG TL= B needs flush */ > -=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env); > +=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env, 1); > =C2=A0} Same =C2=A0 > =C2=A0void helper_rfi(CPUPPCState *env) > diff --git a/target-ppc/helper.h b/target-ppc/helper.h > index dcf3f95..a86e184 100644 > --- a/target-ppc/helper.h > +++ b/target-ppc/helper.h > @@ -18,7 +18,7 @@ DEF_HELPER_1(rfid, void, env) > =C2=A0DEF_HELPER_1(hrfid, void, env) > =C2=A0DEF_HELPER_2(store_lpcr, void, env, tl) > =C2=A0#endif > -DEF_HELPER_1(check_tlb_flush, void, env) > +DEF_HELPER_2(check_tlb_flush, void, env, i32) > =C2=A0#endif > =C2=A0 > =C2=A0DEF_HELPER_3(lmw, void, env, tl, i32) > diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h > index 4457a30..fe20870 100644 > --- a/target-ppc/helper_regs.h > +++ b/target-ppc/helper_regs.h > @@ -154,7 +154,7 @@ static inline int hreg_store_msr(CPUPPCState > *env, target_ulong value, > =C2=A0} > =C2=A0 > =C2=A0#if !defined(CONFIG_USER_ONLY) > -static inline void check_tlb_flush(CPUPPCState *env) > +static inline void check_tlb_flush(CPUPPCState *env, uint32_t > global) > =C2=A0{ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0CPUState *cs =3D CPU(ppc_env_get_cpu(env)= ); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if ((env->tlb_need_flush & TLB_NEED_LOCAL= _FLUSH) =3D=3D > TLB_NEED_LOCAL_FLUSH) { > @@ -163,7 +163,7 @@ static inline void check_tlb_flush(CPUPPCState > *env) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > =C2=A0} > =C2=A0#else > -static inline void check_tlb_flush(CPUPPCState *env) { } > +static inline void check_tlb_flush(CPUPPCState *env, uint32_t > global) { } > =C2=A0#endif > =C2=A0 > =C2=A0#endif /* HELPER_REGS_H */ > diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c > index 2498888..59dea8f 100644 > --- a/target-ppc/mmu_helper.c > +++ b/target-ppc/mmu_helper.c > @@ -2867,9 +2867,9 @@ void helper_booke206_tlbflush(CPUPPCState *env, > target_ulong type) > =C2=A0} > =C2=A0 > =C2=A0 > -void helper_check_tlb_flush(CPUPPCState *env) > +void helper_check_tlb_flush(CPUPPCState *env, unsigned int global) > =C2=A0{ > -=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env); > +=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env, global); > =C2=A0} > =C2=A0 > =C2=A0/****************************************************************= *** > **********/ > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 618334a..5f12c41 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -3064,7 +3064,7 @@ static void gen_eieio(DisasContext *ctx) > =C2=A0} > =C2=A0 > =C2=A0#if !defined(CONFIG_USER_ONLY) > -static inline void gen_check_tlb_flush(DisasContext *ctx) > +static inline void gen_check_tlb_flush(DisasContext *ctx, uint32_t > global) > =C2=A0{ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0TCGv_i32 t; > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0TCGLabel *l; > @@ -3076,12 +3076,13 @@ static inline void > gen_check_tlb_flush(DisasContext *ctx) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0t =3D tcg_temp_new_i32(); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPP= CState, > tlb_need_flush)); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l)= ; > -=C2=A0=C2=A0=C2=A0=C2=A0gen_helper_check_tlb_flush(cpu_env); > +=C2=A0=C2=A0=C2=A0=C2=A0tcg_gen_movi_i32(t, global); > +=C2=A0=C2=A0=C2=A0=C2=A0gen_helper_check_tlb_flush(cpu_env, t); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0gen_set_label(l); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0tcg_temp_free_i32(t); > =C2=A0} > =C2=A0#else > -static inline void gen_check_tlb_flush(DisasContext *ctx) { } > +static inline void gen_check_tlb_flush(DisasContext *ctx, uint32_t > global) { } > =C2=A0#endif > =C2=A0 > =C2=A0/* isync */ > @@ -3092,7 +3093,7 @@ static void gen_isync(DisasContext *ctx) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* kernel mode however so check MSR_= PR > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (!ctx->pr) { > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0gen_check_tlb_flush(ct= x); > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0gen_check_tlb_flush(ct= x, 0); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0gen_stop_exception(ctx); > =C2=A0} > @@ -3257,7 +3258,7 @@ static void gen_sync(DisasContext *ctx) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* check MSR_PR as well. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (((l =3D=3D 2) || !(ctx->insns_flags &= PPC_64B)) && !ctx->pr) { > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0gen_check_tlb_flush(ct= x); > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0gen_check_tlb_flush(ct= x, 1); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > =C2=A0} > =C2=A0 > @@ -4467,7 +4468,7 @@ static void gen_tlbsync(DisasContext *ctx) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* embedded however needs to deal wi= th tlbsync. We don't try to > be > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* fancy and swallow the overhead of= checking for both. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/ > -=C2=A0=C2=A0=C2=A0=C2=A0gen_check_tlb_flush(ctx); > +=C2=A0=C2=A0=C2=A0=C2=A0gen_check_tlb_flush(ctx, 1); > =C2=A0#endif /* defined(CONFIG_USER_ONLY) */ > =C2=A0} You may want to make that one a nop on BookS since it will do both tlbsync and ptesync. BookE only does tlbsync. Ben.