From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56965) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bjKNc-0005lw-C2 for qemu-devel@nongnu.org; Mon, 12 Sep 2016 02:06:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bjKNY-0000sO-5h for qemu-devel@nongnu.org; Mon, 12 Sep 2016 02:06:07 -0400 Message-ID: <1473660343.8689.239.camel@kernel.crashing.org> From: Benjamin Herrenschmidt Date: Mon, 12 Sep 2016 16:05:43 +1000 In-Reply-To: <1473659314-11813-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1473659314-11813-1-git-send-email-nikunj@linux.vnet.ibm.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v3 0/3] ppc: Broadcast tlb flush should have global effect List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania , qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Cc: alex.bennee@linaro.org, qemu-devel@nongnu.org, rth@twiddle.net On Mon, 2016-09-12 at 11:18 +0530, Nikunj A Dadhania wrote: > PowerPC targets should do tlb invalidation on other cpus on=C2=A0 > instructions that expect a global effect. >=20 > * ptesync for BookS > * tlbsync primarily for BookE > =C2=A0 (for BookS make it a nop, as it always come along with ptesync) > * tlbivax for other ppc tragets > * H_REMOVE, H_BULK_REMOVE and H_PROTECT hcalls in case of pseries The above is confusing. The instructions that have global effects are tlbie (BookS) and tlbivax (BookE) plus the H_CALLs since they contain a tlbie on a real hypervisor. The ptesync and tlbsync instructions are barriers use to synchronize with the global invalidations. That means that we don't need to ensure the global invalidations have completed until we hit those barriers. We typically use them as a way to "batch" the invalidations in TCG. > The implementation provides a single point that can be used in MTTCG > for=C2=A0 > doing async-flushes. >=20 > The patchset introduces bit-flags in CPUPPCState::tlb_need_flush: >=20 > =C2=A0 TLB_NEED_LOCAL_FLUSH (0x1) - Flush local tlb > =C2=A0 TLB_NEED_GLOBAL_FLUSH (0x2) - Flush tlb on other cpus. >=20 > Nikunj A Dadhania (3): > =C2=A0 target-ppc: add TLB_NEED_LOCAL_FLUSH flag > =C2=A0 target-ppc: add flag in chech_tlb_flush() > =C2=A0 target-ppc: tlbie should have global effect >=20 > =C2=A0hw/ppc/spapr_hcall.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A06 = ++++-- > =C2=A0target-ppc/cpu.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0|=C2=A0=C2=A02 ++ > =C2=A0target-ppc/excp_helper.c |=C2=A0=C2=A04 ++-- > =C2=A0target-ppc/helper.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2= =A02 +- > =C2=A0target-ppc/helper_regs.h | 25 +++++++++++++++++++++---- > =C2=A0target-ppc/mmu-hash64.c=C2=A0=C2=A0|=C2=A0=C2=A06 +++--- > =C2=A0target-ppc/mmu_helper.c=C2=A0=C2=A0| 20 ++++++++++++-------- > =C2=A0target-ppc/translate.c=C2=A0=C2=A0=C2=A0| 26 ++++++++++++++++----= ------ > =C2=A08 files changed, 61 insertions(+), 30 deletions(-) >=20