From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43269) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bk1Cf-0002B9-3o for qemu-devel@nongnu.org; Tue, 13 Sep 2016 23:49:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bk1Ca-0002hV-0J for qemu-devel@nongnu.org; Tue, 13 Sep 2016 23:49:40 -0400 Message-ID: <1473824961.8689.324.camel@kernel.crashing.org> From: Benjamin Herrenschmidt Date: Wed, 14 Sep 2016 13:49:21 +1000 In-Reply-To: <20160914030941.GE15077@voom.fritz.box> References: <1473659314-11813-1-git-send-email-nikunj@linux.vnet.ibm.com> <1473659314-11813-3-git-send-email-nikunj@linux.vnet.ibm.com> <20160914030941.GE15077@voom.fritz.box> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v3 2/3] target-ppc: add flag in chech_tlb_flush() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson , Nikunj A Dadhania Cc: qemu-ppc@nongnu.org, alex.bennee@linaro.org, qemu-devel@nongnu.org, rth@twiddle.net On Wed, 2016-09-14 at 13:09 +1000, David Gibson wrote: > On Mon, Sep 12, 2016 at 11:18:33AM +0530, Nikunj A Dadhania wrote: > >=20 > > The flag will be used to indicate whether broadcast tlb flush is > > needed > > or not. > >=20 > > Moreover, BookS does both ptesync and tlbsync, so make that a nop > > for > > the server and tlbsync would generate a check flush for BookE >=20 > This commit message needs a bunch more detail.=C2=A0=C2=A0The flag indi= cates > whether a broadcast tlb flush is neede where exactly?=C2=A0=C2=A0How do= es the > information in the parameter differ from the information in the > existing flags which check_tlb_flush() checks? The flag to check_tlb_flush() indicates that any pending broadcast needs to be performed/completed. IE. it's set to 1 as a result of an instruction (or an H_CALL) defined to synchronize broadcast tlbie's > >=20 > >=20 > > Signed-off-by: Nikunj A Dadhania > > --- > > =C2=A0hw/ppc/spapr_hcall.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A0= 4 ++-- > > =C2=A0target-ppc/excp_helper.c |=C2=A0=C2=A04 ++-- > > =C2=A0target-ppc/helper.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2= =A02 +- > > =C2=A0target-ppc/helper_regs.h |=C2=A0=C2=A04 ++-- > > =C2=A0target-ppc/mmu_helper.c=C2=A0=C2=A0|=C2=A0=C2=A04 ++-- > > =C2=A0target-ppc/translate.c=C2=A0=C2=A0=C2=A0| 20 ++++++++++--------= -- > > =C2=A06 files changed, 19 insertions(+), 19 deletions(-) > >=20 > > diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c > > index 73af112..ef12ea0 100644 > > --- a/hw/ppc/spapr_hcall.c > > +++ b/hw/ppc/spapr_hcall.c > > @@ -201,7 +201,7 @@ static target_ulong h_remove(PowerPCCPU *cpu, > > sPAPRMachineState *spapr, > > =C2=A0 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0switch (ret) { > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case REMOVE_SUCCESS: > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env)= ; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env,= 1); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0return H_SUCCES= S; > > =C2=A0 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case REMOVE_NOT_FOUND: > > @@ -282,7 +282,7 @@ static target_ulong h_bulk_remove(PowerPCCPU > > *cpu, sPAPRMachineState *spapr, > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > > =C2=A0 exit: > > -=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env); > > +=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env, 1); > > =C2=A0 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0return rc; > > =C2=A0} > > diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c > > index 04ed4da..3b78126 100644 > > --- a/target-ppc/excp_helper.c > > +++ b/target-ppc/excp_helper.c > > @@ -711,7 +711,7 @@ static inline void powerpc_excp(PowerPCCPU > > *cpu, int excp_model, int excp) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* Any interrupt is context synchronizi= ng, check if TCG TLB > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* needs a delayed flush on ppc64 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/ > > -=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env); > > +=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env, 0); > > =C2=A0} > > =C2=A0 > > =C2=A0void ppc_cpu_do_interrupt(CPUState *cs) > > @@ -973,7 +973,7 @@ static inline void do_rfi(CPUPPCState *env, > > target_ulong nip, target_ulong msr) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0cs->interrupt_request |=3D CPU_INTERRUP= T_EXITTB; > > =C2=A0 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* Context synchronizing: check if TCG = TLB needs flush */ > > -=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env); > > +=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env, 0); > > =C2=A0} > > =C2=A0 > > =C2=A0void helper_rfi(CPUPPCState *env) > > diff --git a/target-ppc/helper.h b/target-ppc/helper.h > > index e75d070..5ececf1 100644 > > --- a/target-ppc/helper.h > > +++ b/target-ppc/helper.h > > @@ -18,7 +18,7 @@ DEF_HELPER_1(rfid, void, env) > > =C2=A0DEF_HELPER_1(hrfid, void, env) > > =C2=A0DEF_HELPER_2(store_lpcr, void, env, tl) > > =C2=A0#endif > > -DEF_HELPER_1(check_tlb_flush, void, env) > > +DEF_HELPER_2(check_tlb_flush, void, env, i32) > > =C2=A0#endif > > =C2=A0 > > =C2=A0DEF_HELPER_3(lmw, void, env, tl, i32) > > diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h > > index 69204a5..bcf65ce 100644 > > --- a/target-ppc/helper_regs.h > > +++ b/target-ppc/helper_regs.h > > @@ -154,7 +154,7 @@ static inline int hreg_store_msr(CPUPPCState > > *env, target_ulong value, > > =C2=A0} > > =C2=A0 > > =C2=A0#if !defined(CONFIG_USER_ONLY) > > -static inline void check_tlb_flush(CPUPPCState *env) > > +static inline void check_tlb_flush(CPUPPCState *env, uint32_t > > global) > > =C2=A0{ > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0CPUState *cs =3D CPU(ppc_env_get_cpu(en= v)); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (env->tlb_need_flush & TLB_NEED_LOCA= L_FLUSH) { > > @@ -163,7 +163,7 @@ static inline void check_tlb_flush(CPUPPCState > > *env) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > > =C2=A0} > > =C2=A0#else > > -static inline void check_tlb_flush(CPUPPCState *env) { } > > +static inline void check_tlb_flush(CPUPPCState *env, uint32_t > > global) { } > > =C2=A0#endif > > =C2=A0 > > =C2=A0#endif /* HELPER_REGS_H */ > > diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c > > index d59d2f8..bf9f329 100644 > > --- a/target-ppc/mmu_helper.c > > +++ b/target-ppc/mmu_helper.c > > @@ -2867,9 +2867,9 @@ void helper_booke206_tlbflush(CPUPPCState > > *env, target_ulong type) > > =C2=A0} > > =C2=A0 > > =C2=A0 > > -void helper_check_tlb_flush(CPUPPCState *env) > > +void helper_check_tlb_flush(CPUPPCState *env, unsigned int global) > > =C2=A0{ > > -=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env); > > +=C2=A0=C2=A0=C2=A0=C2=A0check_tlb_flush(env, global); > > =C2=A0} > > =C2=A0 > > =C2=A0/**************************************************************= *** > > ************/ > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > > index a27f455..5026804 100644 > > --- a/target-ppc/translate.c > > +++ b/target-ppc/translate.c > > @@ -3066,7 +3066,7 @@ static void gen_eieio(DisasContext *ctx) > > =C2=A0} > > =C2=A0 > > =C2=A0#if !defined(CONFIG_USER_ONLY) > > -static inline void gen_check_tlb_flush(DisasContext *ctx) > > +static inline void gen_check_tlb_flush(DisasContext *ctx, uint32_t > > global) > > =C2=A0{ > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0TCGv_i32 t; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0TCGLabel *l; > > @@ -3078,12 +3078,13 @@ static inline void > > gen_check_tlb_flush(DisasContext *ctx) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0t =3D tcg_temp_new_i32(); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0tcg_gen_ld_i32(t, cpu_env, offsetof(CPU= PPCState, > > tlb_need_flush)); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, = l); > > -=C2=A0=C2=A0=C2=A0=C2=A0gen_helper_check_tlb_flush(cpu_env); > > +=C2=A0=C2=A0=C2=A0=C2=A0tcg_gen_movi_i32(t, global); > > +=C2=A0=C2=A0=C2=A0=C2=A0gen_helper_check_tlb_flush(cpu_env, t); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0gen_set_label(l); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0tcg_temp_free_i32(t); > > =C2=A0} > > =C2=A0#else > > -static inline void gen_check_tlb_flush(DisasContext *ctx) { } > > +static inline void gen_check_tlb_flush(DisasContext *ctx, uint32_t > > global) { } > > =C2=A0#endif > > =C2=A0 > > =C2=A0/* isync */ > > @@ -3094,7 +3095,7 @@ static void gen_isync(DisasContext *ctx) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* kernel mode however so check MS= R_PR > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/ > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (!ctx->pr) { > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0gen_check_tlb_flush(= ctx); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0gen_check_tlb_flush(= ctx, 0); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0gen_stop_exception(ctx); > > =C2=A0} > > @@ -3259,7 +3260,7 @@ static void gen_sync(DisasContext *ctx) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* check MSR_PR as well. > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/ > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (((l =3D=3D 2) || !(ctx->insns_flags= & PPC_64B)) && !ctx->pr) { > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0gen_check_tlb_flush(= ctx); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0gen_check_tlb_flush(= ctx, 1); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > > =C2=A0} > > =C2=A0 > > @@ -4468,11 +4469,10 @@ static void gen_tlbsync(DisasContext *ctx) > > =C2=A0#else > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0CHK_HV; > > =C2=A0 > > -=C2=A0=C2=A0=C2=A0=C2=A0/* tlbsync is a nop for server, ptesync hand= les delayed tlb > > flush, > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* embedded however needs to deal with = tlbsync. We don't try > > to be > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* fancy and swallow the overhead of ch= ecking for both. > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/ > > -=C2=A0=C2=A0=C2=A0=C2=A0gen_check_tlb_flush(ctx); > > +=C2=A0=C2=A0=C2=A0=C2=A0/* BookS does both ptesync and tlbsync make = tlbsync a nop for > > server */ > > +=C2=A0=C2=A0=C2=A0=C2=A0if (ctx->insns_flags & PPC_BOOKE) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0gen_check_tlb_flush(= ctx, 1); > > +=C2=A0=C2=A0=C2=A0=C2=A0} > > =C2=A0#endif /* defined(CONFIG_USER_ONLY) */ > > =C2=A0} > > =C2=A0 >=20