From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Jeffery Subject: Re: [PATCH v2 4/6] pinctrl: aspeed: Read and write bits in LPCHC and GFX controllers Date: Fri, 04 Nov 2016 14:29:52 +1030 Message-ID: <1478231992.27396.79.camel@aj.id.au> References: <1478097481-14895-1-git-send-email-andrew@aj.id.au> <1478097481-14895-5-git-send-email-andrew@aj.id.au> Mime-Version: 1.0 Content-Type: multipart/signed; micalg="pgp-sha512"; protocol="application/pgp-signature"; boundary="=-+TMxMvOqGiI+odZ5dhyi" Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Joel Stanley Cc: Lee Jones , Linus Walleij , Mark Rutland , Rob Herring , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org List-Id: linux-gpio@vger.kernel.org --=-+TMxMvOqGiI+odZ5dhyi Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: base64 T24gRnJpLCAyMDE2LTExLTA0IGF0IDA5OjU0ICsxMDMwLCBKb2VsIFN0YW5sZXkgd3JvdGU6Cj4g T24gVGh1LCBOb3YgMywgMjAxNiBhdCAxOjA3IEFNLCBBbmRyZXcgSmVmZmVyeSA8YW5kcmV3QGFq LmlkLmF1PiB3cm90ZToKPiA+IAo+ID4gVGhlIFN5c3RlbSBDb250cm9sIFVuaXQgSVAgYmxvY2sg aW4gdGhlIEFzcGVlZCBTb0NzIGlzIHR5cGljYWxseSB3aGVyZQo+ID4gdGhlIHBpbm11eCBjb25m aWd1cmF0aW9uIGlzIGZvdW5kLCBidXQgbm90IGFsd2F5cy4gQSBudW1iZXIgb2YgcGlucwo+ID4g ZGVwZW5kIG9uIHN0YXRlIGluIG9uZSBvZiBMUEMgSG9zdCBDb250cm9sIChMUENIQykgb3IgU29D IERpc3BsYXkKPiA+IENvbnRyb2xsZXIgKEdGWCkgSVAgYmxvY2tzLCBzbyB0aGUgQXNwZWVkIHBp bm11eCBkcml2ZXJzIHNob3VsZCBoYXZlIHRoZQo+ID4gbWVhbnMgdG8gYWRqdXN0IHRoZXNlIGFz IG5lY2Vzc2FyeS4KPiA+IAo+ID4gV2UgdXNlIHN5c2NvbiB0byBjYXN0IGEgcmVnbWFwIG92ZXIg dGhlIEdGWCBhbmQgTFBDSENSIGJsb2Nrcywgd2hpY2ggaXMKPiA+IHVzZWQgYXMgYW4gYXJiaXRy YXRpb24gbGF5ZXIgYmV0d2VlbiB0aGUgcmVsZXZhbnQgZHJpdmVyIGFuZCB0aGUgcGluY3RybAo+ ID4gc3Vic3lzdGVtLiBUaGUgcmVnbWFwcyBhcmUgdGhlbiBleHBvc2VkIHRvIHRoZSBTb0Mtc3Bl Y2lmaWMgcGluY3RybAo+ID4gZHJpdmVycyBieSBwaGFuZGxlcyBpbiB0aGUgZGV2aWNldHJlZSwg YW5kIGFyZSBzZWxlY3RlZCBkdXJpbmcgYSBtdXgKPiA+IHJlcXVlc3QgYnkgcXVlcnlpbmcgYSBu ZXcgJ2lwJyBtZW1iZXIgaW4gc3RydWN0IGFzcGVlZF9zaWdfZGVzYy4KPiA+IAo+ID4gU2lnbmVk LW9mZi1ieTogQW5kcmV3IEplZmZlcnkgPGFuZHJld0Bhai5pZC5hdT4KPiBJIGxpa2UgdGhpcyBh IGxvdCBtb3JlIHRoYW4gdGhlIGZpcnN0IGdvLiBHb29kIHdvcmsuCj4gCj4gU29tZSBtaW5vciBj b21tZW50cyBiZWxvdy4KPiAKPiA+IAo+ID4gLS0tCj4gPiBTaW5jZSB2MToKPiA+IAo+ID4gVGhl IGNoYW5nZSBpcyBub3cgcHJvYWN0aXZlOiBpbnN0ZWFkIG9mIHJlcG9ydGluZyB0aGF0IHdlIG5l ZWQgdG8gZmxpcCBiaXRzIGluCj4gPiBjb250cm9sbGVycyB3ZSBjYW4ndCBhY2Nlc3MsIHRoZSBw YXRjaCBwcm92aWRlcyBhY2Nlc3MgdmlhIHJlZ21hcHMgZm9yIHRoZQo+ID4gcmVsZXZhbnQgY29u dHJvbGxlcnMuIFRoZSBpbXBsZW1lbnRhdGlvbiBhbHNvIHNwbGl0cyBvdXQgdGhlIElQIGJsb2Nr IElEIGludG8KPiA+IGl0cyBvd24gdmFyaWFibGUgcmF0aGVyIHRoYW4gcGFja2luZyB0aGUgdmFs dWUgaW50byB0aGUgdXBwZXIgYml0cyBvZiB0aGUgcmVnCj4gPiBtZW1iZXIgb2Ygc3RydWN0IGFz cGVlZF9zaWdfZGVzYy4gVGhpcyBkcml2ZXMgc29tZSBjaHVybiBpbiB0aGUgZGlmZiwgYnV0IEkn dmUKPiA+IHRyaWVkIHRvIG1pbmltaXNlIGl0Lgo+ID4gCj4gPiDCoC4uLi9kZXZpY2V0cmVlL2Jp bmRpbmdzL3BpbmN0cmwvcGluY3RybC1hc3BlZWQudHh0IHwgNTAgKysrKysrKysrKysrKy0tLQo+ ID4gwqBkcml2ZXJzL3BpbmN0cmwvYXNwZWVkL3BpbmN0cmwtYXNwZWVkLWc0LmPCoMKgwqDCoMKg wqDCoMKgwqB8IDE4ICsrKy0tLQo+ID4gwqBkcml2ZXJzL3BpbmN0cmwvYXNwZWVkL3BpbmN0cmwt YXNwZWVkLWc1LmPCoMKgwqDCoMKgwqDCoMKgwqB8IDM5ICsrKysrKysrKystLS0KPiA+IMKgZHJp dmVycy9waW5jdHJsL2FzcGVlZC9waW5jdHJsLWFzcGVlZC5jwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgfCA2NiArKysrKysrKysrKysrLS0tLS0tLS0tCj4gPiDCoGRyaXZlcnMvcGluY3RybC9hc3Bl ZWQvcGluY3RybC1hc3BlZWQuaMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoHwgMzIgKysrKysrKyst LS0KPiA+IMKgNSBmaWxlcyBjaGFuZ2VkLCAxNDQgaW5zZXJ0aW9ucygrKSwgNjEgZGVsZXRpb25z KC0pCj4gPiAKPiA+IGRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGlu Z3MvcGluY3RybC9waW5jdHJsLWFzcGVlZC50eHQgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUv YmluZGluZ3MvcGluY3RybC9waW5jdHJsLWFzcGVlZC50eHQKPiA+IGluZGV4IDJhZDE4YzRlYTU1 Yy4uMTE1YjBjY2U2YzFjIDEwMDY0NAo+ID4gLS0tIGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVl L2JpbmRpbmdzL3BpbmN0cmwvcGluY3RybC1hc3BlZWQudHh0Cj4gPiArKysgYi9Eb2N1bWVudGF0 aW9uL2RldmljZXRyZWUvYmluZGluZ3MvcGluY3RybC9waW5jdHJsLWFzcGVlZC50eHQKPiA+IEBA IC00LDEyICs0LDE5IEBAIEFzcGVlZCBQaW4gQ29udHJvbGxlcnMKPiA+IMKgVGhlIEFzcGVlZCBT b0NzIHZhcnkgaW4gZnVuY3Rpb25hbGl0eSBpbnNpZGUgYSBnZW5lcmF0aW9uIGJ1dCBoYXZlIGEg Y29tbW9uIG11eAo+ID4gwqBkZXZpY2UgcmVnaXN0ZXIgbGF5b3V0Lgo+ID4gCj4gPiAtUmVxdWly ZWQgcHJvcGVydGllczoKPiA+IC0tIGNvbXBhdGlibGUgOiBTaG91bGQgYmUgYW55IG9uZSBvZiB0 aGUgZm9sbG93aW5nOgo+ID4gLcKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCJhc3BlZWQs YXN0MjQwMC1waW5jdHJsIgo+ID4gLcKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCJhc3Bl ZWQsZzQtcGluY3RybCIKPiA+IC3CoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAiYXNwZWVk LGFzdDI1MDAtcGluY3RybCIKPiA+IC3CoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAiYXNw ZWVkLGc1LXBpbmN0cmwiCj4gPiArUmVxdWlyZWQgcHJvcGVydGllcyBmb3IgZzQ6Cj4gPiArLSBj b21wYXRpYmxlIDrCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoFNob3VsZCBiZSBhbnkgb25lIG9mIHRoZSBmb2xsb3dpbmc6Cj4gPiArwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAiYXNwZWVk LGFzdDI0MDAtcGluY3RybCIKPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCJhc3BlZWQsZzQtcGluY3RybCIKPiA+ICsKPiA+ ICtSZXF1aXJlZCBwcm9wZXJ0aWVzIGZvciBnNToKPiA+ICstIGNvbXBhdGlibGUgOsKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgU2hvdWxkIGJlIGFueSBv bmUgb2YgdGhlIGZvbGxvd2luZzoKPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCJhc3BlZWQsYXN0MjUwMC1waW5jdHJsIgo+ ID4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgImFzcGVlZCxnNS1waW5jdHJsIgo+ID4gKwo+ID4gKy0gYXNwZWVkLGV4dGVybmFs LW5vZGVzOsKgwqDCoMKgwqDCoMKgQSBjZWxsIG9mIHBoYW5kbGVzIHRvIGV4dGVybmFsIGNvbnRy b2xsZXIgbm9kZXM6Cj4gPiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAwOiBjb21wYXRpYmxlIHdpdGggImFzcGVlZCxhc3QyNTAw LWdmeCIsICJzeXNjb24iCj4gPiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAxOiBjb21wYXRpYmxlIHdpdGggImFzcGVlZCxhc3Qy NTAwLWxwY2hjIiwgInN5c2NvbiIKPiA+IAo+ID4gwqBUaGUgcGluIGNvbnRyb2xsZXIgbm9kZSBz aG91bGQgYmUgYSBjaGlsZCBvZiBhIHN5c2NvbiBub2RlIHdpdGggdGhlIHJlcXVpcmVkCj4gPiDC oHByb3BlcnR5Ogo+ID4gQEAgLTQ3LDcgKzU0LDcgQEAgUkdNSUkxIFJHTUlJMiBSTUlJMSBSTUlJ MiBTRDEgU1BJMSBTUEkxREVCVUcgU1BJMVBBU1NUSFJVIFRJTUVSNCBUSU1FUjUgVElNRVI2Cj4g PiDCoFRJTUVSNyBUSU1FUjggVkdBQklPU1JPTQo+ID4gCj4gPiAKPiA+IC1FeGFtcGxlczoKPiA+ ICtnNCBFeGFtcGxlOgo+ID4gCj4gPiDCoHN5c2Nvbjogc2N1QDFlNmUyMDAwIHsKPiA+IMKgwqDC oMKgwqDCoMKgwqBjb21wYXRpYmxlID0gInN5c2NvbiIsICJzaW1wbGUtbWZkIjsKPiA+IEBAIC02 Myw1ICs3MCwzNCBAQCBzeXNjb246IHNjdUAxZTZlMjAwMCB7Cj4gPiDCoMKgwqDCoMKgwqDCoMKg fTsKPiA+IMKgfTsKPiA+IAo+ID4gK2c1IEV4YW1wbGU6Cj4gPiArCj4gPiArYXBiIHsKPiA+ICvC oMKgwqDCoMKgwqDCoGdmeDogZGlzcGxheUAxZTZlNjAwMCB7Cj4gPiArwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgY29tcGF0aWJsZSA9ICJhc3BlZWQsYXN0MjUwMC1nZngiLCAic3lzY29u IjsKPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqByZWcgPSA8MHgxZTZlNjAwMCAw eDEwMDA+Owo+ID4gK8KgwqDCoMKgwqDCoMKgfTsKPiA+ICsKPiA+ICvCoMKgwqDCoMKgwqDCoGxw Y2hjOiBscGNoY0AxZTc4OTBhMCB7Cj4gPiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg Y29tcGF0aWJsZSA9ICJhc3BlZWQsYXN0MjUwMC1scGNoYyIsICJzeXNjb24iOwo+ID4gK8KgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoHJlZyA9IDwweDFlNzg5MGEwIDB4YzQ+Owo+ID4gK8Kg wqDCoMKgwqDCoMKgfTsKPiA+ICsKPiA+ICvCoMKgwqDCoMKgwqDCoHN5c2Nvbjogc2N1QDFlNmUy MDAwIHsKPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBjb21wYXRpYmxlID0gInN5 c2NvbiIsICJzaW1wbGUtbWZkIjsKPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBy ZWcgPSA8MHgxZTZlMjAwMCAweDFhOD47Cj4gPiArCj4gPiArwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgcGluY3RybDogcGluY3RybCB7Cj4gPiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoGNvbXBhdGlibGUgPSAiYXNwZWVkLGc1LXBpbmN0cmwiOwo+ ID4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBhc3BlZWQs ZXh0ZXJuYWwtbm9kZXMgPSA8JmdmeCwgJmxwY2hjPjsKPiA+ICsKPiA+ICvCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgcGluY3RybF9pMmMzX2RlZmF1bHQ6IGky YzNfZGVmYXVsdCB7Cj4gPiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBmdW5jdGlvbiA9ICJJMkMzIjsKPiA+ICvCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoGdyb3Vw cyA9ICJJMkMzIjsKPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgfTsKPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqB9Owo+ID4gK8KgwqDC oMKgwqDCoMKgfTsKPiA+ICt9Owo+ID4gKwo+ID4gwqBQbGVhc2UgcmVmZXIgdG8gcGluY3RybC1i aW5kaW5ncy50eHQgaW4gdGhpcyBkaXJlY3RvcnkgZm9yIGRldGFpbHMgb2YgdGhlCj4gPiDCoGNv bW1vbiBwaW5jdHJsIGJpbmRpbmdzIHVzZWQgYnkgY2xpZW50IGRldmljZXMuCj4gPiBkaWZmIC0t Z2l0IGEvZHJpdmVycy9waW5jdHJsL2FzcGVlZC9waW5jdHJsLWFzcGVlZC1nNC5jIGIvZHJpdmVy cy9waW5jdHJsL2FzcGVlZC9waW5jdHJsLWFzcGVlZC1nNC5jCj4gPiBpbmRleCBhMjFiMDcxZmYy OTAuLjU1OGJkMTAyNDE2YyAxMDA2NDQKPiA+IC0tLSBhL2RyaXZlcnMvcGluY3RybC9hc3BlZWQv cGluY3RybC1hc3BlZWQtZzQuYwo+ID4gKysrIGIvZHJpdmVycy9waW5jdHJsL2FzcGVlZC9waW5j dHJsLWFzcGVlZC1nNC5jCj4gPiBAQCAtMjkyLDcgKzI5Miw3IEBAIFNTU0ZfUElOX0RFQ0woVTE4 LCBHUElPRzcsIEZMV1AsIFNJR19ERVNDX1NFVChTQ1U4NCwgNykpOwo+ID4gwqAjZGVmaW5lIFVB UlQ2X0RFU0PCoMKgwqDCoMKgU0lHX0RFU0NfU0VUKFNDVTkwLCA3KQo+ID4gwqAjZGVmaW5lIFJP TTE2X0RFU0PCoMKgwqDCoMKgU0lHX0RFU0NfU0VUKFNDVTkwLCA2KQo+ID4gwqAjZGVmaW5lIEZM QVNIX1dJREXCoMKgwqDCoMKgU0lHX0RFU0NfU0VUKEhXX1NUUkFQMSwgNCkKPiA+IC0jZGVmaW5l IEJPT1RfU1JDX05PUsKgwqDCoHsgSFdfU1RSQVAxLCBHRU5NQVNLKDEsIDApLCAwLCAwIH0KPiA+ ICsjZGVmaW5lIEJPT1RfU1JDX05PUsKgwqDCoHsgQVNQRUVEX0lQX1NDVSwgSFdfU1RSQVAxLCBH RU5NQVNLKDEsIDApLCAwLCAwIH0KPiA+IAo+ID4gwqAjZGVmaW5lIEE4IDU2Cj4gPiDCoFNJR19F WFBSX0RFQ0woUk9NRDgsIFJPTTE2LCBST00xNl9ERVNDKTsKPiA+IEBAIC00MTgsOSArNDE4LDkg QEAgRlVOQ19HUk9VUF9ERUNMKEkyQzgsIEc1LCBGMyk7Cj4gPiDCoCNkZWZpbmUgVTEgODgKPiA+ IMKgU1NTRl9QSU5fREVDTChVMSwgR1BJT0wwLCBOQ1RTMSwgU0lHX0RFU0NfU0VUKFNDVTg0LCAx NikpOwo+ID4gCj4gPiAtI2RlZmluZSBWUEkxOF9ERVNDwqDCoMKgwqDCoHsgU0NVOTAsIEdFTk1B U0soNSwgNCksIDEsIDAgfQo+ID4gLSNkZWZpbmUgVlBJMjRfREVTQ8KgwqDCoMKgwqB7IFNDVTkw LCBHRU5NQVNLKDUsIDQpLCAyLCAwIH0KPiA+IC0jZGVmaW5lIFZQSTMwX0RFU0PCoMKgwqDCoMKg eyBTQ1U5MCwgR0VOTUFTSyg1LCA0KSwgMywgMCB9Cj4gPiArI2RlZmluZSBWUEkxOF9ERVNDwqDC oMKgwqDCoHsgQVNQRUVEX0lQX1NDVSwgU0NVOTAsIEdFTk1BU0soNSwgNCksIDEsIDAgfQo+ID4g KyNkZWZpbmUgVlBJMjRfREVTQ8KgwqDCoMKgwqB7IEFTUEVFRF9JUF9TQ1UsIFNDVTkwLCBHRU5N QVNLKDUsIDQpLCAyLCAwIH0KPiA+ICsjZGVmaW5lIFZQSTMwX0RFU0PCoMKgwqDCoMKgeyBBU1BF RURfSVBfU0NVLCBTQ1U5MCwgR0VOTUFTSyg1LCA0KSwgMywgMCB9Cj4gPiAKPiA+IMKgI2RlZmlu ZSBUNSA4OQo+ID4gwqAjZGVmaW5lIFQ1X0RFU0PCoMKgwqDCoMKgwqDCoMKgwqBTSUdfREVTQ19T RVQoU0NVODQsIDE3KQo+ID4gQEAgLTY0MSwxMSArNjQxLDExIEBAIFNTU0ZfUElOX0RFQ0woWTIy LCBHUElPUjIsIFJPTUNTMywgU0lHX0RFU0NfU0VUKFNDVTg4LCAyNikpOwo+ID4gwqAjZGVmaW5l IFUxOSAxMzkKPiA+IMKgU1NTRl9QSU5fREVDTChVMTksIEdQSU9SMywgUk9NQ1M0LCBTSUdfREVT Q19TRVQoU0NVODgsIDI3KSk7Cj4gPiAKPiA+IC0jZGVmaW5lIFZQT09GRjBfREVTQ8KgwqDCoHsg U0NVOTQsIEdFTk1BU0soMSwgMCksIDAsIDAgfQo+ID4gLSNkZWZpbmUgVlBPMTJfREVTQ8KgwqDC oMKgwqB7IFNDVTk0LCBHRU5NQVNLKDEsIDApLCAxLCAwIH0KPiA+IC0jZGVmaW5lIFZQTzI0X0RF U0PCoMKgwqDCoMKgeyBTQ1U5NCwgR0VOTUFTSygxLCAwKSwgMiwgMCB9Cj4gPiAtI2RlZmluZSBW UE9PRkYxX0RFU0PCoMKgwqB7IFNDVTk0LCBHRU5NQVNLKDEsIDApLCAzLCAwIH0KPiA+IC0jZGVm aW5lIFZQT19PRkZfMTLCoMKgwqDCoMKgwqB7IFNDVTk0LCAweDIsIDAsIDAgfQo+ID4gKyNkZWZp bmUgVlBPT0ZGMF9ERVNDwqDCoMKgeyBBU1BFRURfSVBfU0NVLCBTQ1U5NCwgR0VOTUFTSygxLCAw KSwgMCwgMCB9Cj4gPiArI2RlZmluZSBWUE8xMl9ERVNDwqDCoMKgwqDCoHsgQVNQRUVEX0lQX1ND VSwgU0NVOTQsIEdFTk1BU0soMSwgMCksIDEsIDAgfQo+ID4gKyNkZWZpbmUgVlBPMjRfREVTQ8Kg wqDCoMKgwqB7IEFTUEVFRF9JUF9TQ1UsIFNDVTk0LCBHRU5NQVNLKDEsIDApLCAyLCAwIH0KPiA+ ICsjZGVmaW5lIFZQT09GRjFfREVTQ8KgwqDCoHsgQVNQRUVEX0lQX1NDVSwgU0NVOTQsIEdFTk1B U0soMSwgMCksIDMsIDAgfQo+ID4gKyNkZWZpbmUgVlBPX09GRl8xMsKgwqDCoMKgwqDCoHsgQVNQ RUVEX0lQX1NDVSwgU0NVOTQsIDB4MiwgMCwgMCB9Cj4gPiDCoCNkZWZpbmUgVlBPXzI0X09GRsKg wqDCoMKgwqDCoFNJR19ERVNDX1NFVChTQ1U5NCwgMSkKPiA+IAo+ID4gwqAjZGVmaW5lIFYyMSAx NDAKPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BpbmN0cmwvYXNwZWVkL3BpbmN0cmwtYXNwZWVk LWc1LmMgYi9kcml2ZXJzL3BpbmN0cmwvYXNwZWVkL3BpbmN0cmwtYXNwZWVkLWc1LmMKPiA+IGlu ZGV4IDg3YjQ2MzkwYjY5NS4uOTljNGZhOWJmODYxIDEwMDY0NAo+ID4gLS0tIGEvZHJpdmVycy9w aW5jdHJsL2FzcGVlZC9waW5jdHJsLWFzcGVlZC1nNS5jCj4gPiArKysgYi9kcml2ZXJzL3BpbmN0 cmwvYXNwZWVkL3BpbmN0cmwtYXNwZWVkLWc1LmMKPiA+IEBAIC0xMCw2ICsxMCw3IEBACj4gPiDC oCNpbmNsdWRlIAo+ID4gwqAjaW5jbHVkZSAKPiA+IMKgI2luY2x1ZGUgCj4gPiArI2luY2x1ZGUg Cj4gPiDCoCNpbmNsdWRlIAo+ID4gwqAjaW5jbHVkZSAKPiA+IMKgI2luY2x1ZGUgCj4gPiBAQCAt MjYsOCArMjcsOCBAQAo+ID4gCj4gPiDCoCNkZWZpbmUgQVNQRUVEX0c1X05SX1BJTlMgMjI4Cj4g PiAKPiA+IC0jZGVmaW5lIENPTkQxwqDCoMKgwqDCoMKgwqDCoMKgwqB7IFNDVTkwLCBCSVQoNiks IDAsIDAgfQo+ID4gLSNkZWZpbmUgQ09ORDLCoMKgwqDCoMKgwqDCoMKgwqDCoHsgU0NVOTQsIEdF Tk1BU0soMSwgMCksIDAsIDAgfQo+ID4gKyNkZWZpbmUgQ09ORDHCoMKgwqDCoMKgwqDCoMKgwqDC oHsgQVNQRUVEX0lQX1NDVSwgU0NVOTAsIEJJVCg2KSwgMCwgMCB9Cj4gPiArI2RlZmluZSBDT05E MsKgwqDCoMKgwqDCoMKgwqDCoMKgeyBBU1BFRURfSVBfU0NVLCBTQ1U5NCwgR0VOTUFTSygxLCAw KSwgMCwgMCB9Cj4gPiAKPiA+IMKgI2RlZmluZSBCMTQgMAo+ID4gwqBTU1NGX1BJTl9ERUNMKEIx NCwgR1BJT0EwLCBNQUMxTElOSywgU0lHX0RFU0NfU0VUKFNDVTgwLCAwKSk7Cj4gPiBAQCAtMTg2 LDkgKzE4NywxMiBAQCBNU19QSU5fREVDTChDMjAsIEdQSU9FMSwgTkRDRDMsIEdQSUUwT1VUKTsK PiA+IAo+ID4gwqBGVU5DX0dST1VQX0RFQ0woR1BJRTAsIEIyMCwgQzIwKTsKPiA+IAo+ID4gLSNk ZWZpbmUgU1BJMV9ERVNDwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoHsgSFdfU1RSQVAxLCBH RU5NQVNLKDEzLCAxMiksIDEsIDAgfQo+ID4gLSNkZWZpbmUgU1BJMURFQlVHX0RFU0PCoMKgwqDC oMKgwqDCoMKgwqB7IEhXX1NUUkFQMSwgR0VOTUFTSygxMywgMTIpLCAyLCAwIH0KPiA+IC0jZGVm aW5lIFNQSTFQQVNTVEhSVV9ERVNDwqDCoMKgwqDCoMKgeyBIV19TVFJBUDEsIEdFTk1BU0soMTMs IDEyKSwgMywgMCB9Cj4gPiArI2RlZmluZSBTUEkxX0RFU0MgXAo+ID4gK8KgwqDCoMKgwqDCoMKg eyBBU1BFRURfSVBfU0NVLCBIV19TVFJBUDEsIEdFTk1BU0soMTMsIDEyKSwgMSwgMCB9Cj4gPiAr I2RlZmluZSBTUEkxREVCVUdfREVTQyBcCj4gPiArwqDCoMKgwqDCoMKgwqB7IEFTUEVFRF9JUF9T Q1UsIEhXX1NUUkFQMSwgR0VOTUFTSygxMywgMTIpLCAyLCAwIH0KPiA+ICsjZGVmaW5lIFNQSTFQ QVNTVEhSVV9ERVNDIFwKPiA+ICvCoMKgwqDCoMKgwqDCoHsgQVNQRUVEX0lQX1NDVSwgSFdfU1RS QVAxLCBHRU5NQVNLKDEzLCAxMiksIDMsIDAgfQo+ID4gCj4gPiDCoCNkZWZpbmUgQzE4IDY0Cj4g PiDCoFNJR19FWFBSX0RFQ0woU1lTQ1MsIFNQSTFERUJVRywgQ09ORDEsIFNQSTFERUJVR19ERVND KTsKPiA+IEBAIC0zMjUsMTAgKzMyOSwxMSBAQCBTU19QSU5fREVDTChSMSwgR1BJT0s3LCBTREE4 KTsKPiA+IAo+ID4gwqBGVU5DX0dST1VQX0RFQ0woSTJDOCwgUDIsIFIxKTsKPiA+IAo+ID4gLSNk ZWZpbmUgVlBJT0ZGMF9ERVNDwqDCoMKgwqB7IFNDVTkwLCBHRU5NQVNLKDUsIDQpLCAwLCAwIH0K PiA+IC0jZGVmaW5lIFZQSU9GRjFfREVTQ8KgwqDCoMKgeyBTQ1U5MCwgR0VOTUFTSyg1LCA0KSwg MSwgMCB9Cj4gPiAtI2RlZmluZSBWUEkyNF9ERVNDwqDCoMKgwqDCoMKgeyBTQ1U5MCwgR0VOTUFT Syg1LCA0KSwgMiwgMCB9Cj4gPiAtI2RlZmluZSBWUElSU1ZEX0RFU0PCoMKgwqDCoHsgU0NVOTAs IEdFTk1BU0soNSwgNCksIDMsIDAgfQo+ID4gKyNkZWZpbmUgVlBJT0ZGMF9ERVNDwqDCoMKgwqB7 IEFTUEVFRF9JUF9TQ1UsIFNDVTkwLCBHRU5NQVNLKDUsIDQpLCAwLCAwIH0KPiA+ICsjZGVmaW5l IFZQSU9GRjFfREVTQ8KgwqDCoMKgeyBBU1BFRURfSVBfU0NVLCBTQ1U5MCwgR0VOTUFTSyg1LCA0 KSwgMSwgMCB9Cj4gPiArI2RlZmluZSBWUEkyNF9ERVNDwqDCoMKgwqDCoMKgeyBBU1BFRURfSVBf U0NVLCBTQ1U5MCwgR0VOTUFTSyg1LCA0KSwgMiwgMCB9Cj4gPiArI2RlZmluZSBWUElSU1ZEX0RF U0PCoMKgwqDCoHsgQVNQRUVEX0lQX1NDVSwgU0NVOTAsIEdFTk1BU0soNSwgNCksIDMsIDAgfQo+ ID4gKwo+ID4gCj4gPiDCoCNkZWZpbmUgVjIgMTA0Cj4gPiDCoCNkZWZpbmUgVjJfREVTQ8KgwqDC oMKgwqDCoMKgwqDCoFNJR19ERVNDX1NFVChTQ1U4OCwgMCkKPiA+IEBAIC04NDgsMTAgKzg1Mywy NiBAQCBzdGF0aWMgc3RydWN0IHBpbmN0cmxfZGVzYyBhc3BlZWRfZzVfcGluY3RybF9kZXNjID0g ewo+ID4gwqBzdGF0aWMgaW50IGFzcGVlZF9nNV9waW5jdHJsX3Byb2JlKHN0cnVjdCBwbGF0Zm9y bV9kZXZpY2UgKnBkZXYpCj4gPiDCoHsKPiA+IMKgwqDCoMKgwqDCoMKgwqBpbnQgaTsKPiA+ICvC oMKgwqDCoMKgwqDCoHN0cnVjdCByZWdtYXAgKiptYXA7Cj4gPiArwqDCoMKgwqDCoMKgwqBzdHJ1 Y3QgZGV2aWNlX25vZGUgKm5vZGU7Cj4gPiAKPiA+IMKgwqDCoMKgwqDCoMKgwqBmb3IgKGkgPSAw OyBpIDwgQVJSQVlfU0laRShhc3BlZWRfZzVfcGlucyk7IGkrKykKPiA+IMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgYXNwZWVkX2c1X3BpbnNbaV0ubnVtYmVyID0gaTsKPiA+IAo+ID4g K8KgwqDCoMKgwqDCoMKgbWFwID0gJmFzcGVlZF9nNV9waW5jdHJsX2RhdGEubWFwc1tBU1BFRURf SVBfR0ZYXTsKPiA+ICvCoMKgwqDCoMKgwqDCoG5vZGUgPSBvZl9wYXJzZV9waGFuZGxlKHBkZXYt PmRldi5vZl9ub2RlLCAiYXNwZWVkLGV4dGVybmFsLW5vZGVzIiwgMCk7Cj4gPiArwqDCoMKgwqDC oMKgwqAqbWFwID0gc3lzY29uX25vZGVfdG9fcmVnbWFwKG5vZGUpOwo+IEkgdGhpbmsgeW91IGNh biB1c2Ugc3lzY29uX3JlZ21hcF9sb29rdXBfYnlfcGhhbmRsZSB0byByZXBsYWNlIGJvdGggb2YK PiB0aGVzZSBsaW5lcy4KCkdvb2QgY2FsbCwgd2lsbCBkby4KCj4gCj4gPiAKPiA+ICvCoMKgwqDC oMKgwqDCoG9mX25vZGVfcHV0KG5vZGUpOwo+ID4gK8KgwqDCoMKgwqDCoMKgaWYgKElTX0VSUigq bWFwKSkKPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqByZXR1cm4gUFRSX0VSUigq bWFwKTsKPiBEbyB3ZSB3YW50IHRvIGZhaWwsIG9yIHdhcm4gYW5kIGNvbnRpbnVlPwoKV2Ugd291 bGQgbmVlZCB0byBhZGQgZnVydGhlciBjaGVja3MgdG8gZGVmZW5kIGFnYWluc3QgbnVsbCBkZXJl ZmVyZW5jZXMKaWYgd2Ugd2VyZSB0byBjb250aW51ZS4gSSB0aGluayB0aGUgYnJva2VuIGRldmlj ZXRyZWUgc2hvdWxkIGJlIGZpeGVkLgoKPiAKPiBUaGUgc2VxdWVuY2UgaXMgYSBiaXQgbWVzc3ku IEhvdyBhYm91dDoKPiAKPiBzdHJ1Y3QgcmVnbWFwICptYXA7Cj4gCj4gbWFwID0gc3lzY29uX3Jl Z21hcF9sb29rdXBfYnlfcGhhbmRsZShwZGV2LT5kZXYub2Zfbm9kZSwKPiAiYXNwZWVkLGV4dGVy bmFsLW5vZGVzIik7Cj4gaWYgKElTX0VSUihtYXApKQo+IMKgwqDCoHJldHVybiBQVFJfRVJSKG1h cCk7Cj4gCj4gYXNwZWVkX2c1X3BpbmN0cmxfZGF0YS5tYXBzW0FTUEVFRF9JUF9HRlhdID0gbWFw OwoKVGhhdCBsb29rcyBuZWF0ZXIsIEkgd2lsbCBzd2l0Y2guCgo+IAo+IAo+ID4gCj4gPiArCj4g PiArwqDCoMKgwqDCoMKgwqBtYXAgPSAmYXNwZWVkX2c1X3BpbmN0cmxfZGF0YS5tYXBzW0FTUEVF RF9JUF9MUENIQ107Cj4gPiArwqDCoMKgwqDCoMKgwqBub2RlID0gb2ZfcGFyc2VfcGhhbmRsZShw ZGV2LT5kZXYub2Zfbm9kZSwgImFzcGVlZCxleHRlcm5hbC1ub2RlcyIsIDEpOwo+ID4gK8KgwqDC oMKgwqDCoMKgKm1hcCA9IHN5c2Nvbl9ub2RlX3RvX3JlZ21hcChub2RlKTsKPiA+ICvCoMKgwqDC oMKgwqDCoG9mX25vZGVfcHV0KG5vZGUpOwo+ID4gK8KgwqDCoMKgwqDCoMKgaWYgKElTX0VSUigq bWFwKSkKPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqByZXR1cm4gUFRSX0VSUigq bWFwKTsKPiA+ICsKPiBTYW1lIGNvbW1lbnRzIGFzIGFib3ZlLgoKQWNrLgoKPiAKPiA+IAo+ID4g wqDCoMKgwqDCoMKgwqDCoHJldHVybiBhc3BlZWRfcGluY3RybF9wcm9iZShwZGV2LCAmYXNwZWVk X2c1X3BpbmN0cmxfZGVzYywKPiA+IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoCZhc3BlZWRfZzVfcGluY3RybF9kYXRhKTsKPiA+IMKgfQo+ID4gZGlmZiAt LWdpdCBhL2RyaXZlcnMvcGluY3RybC9hc3BlZWQvcGluY3RybC1hc3BlZWQuYyBiL2RyaXZlcnMv cGluY3RybC9hc3BlZWQvcGluY3RybC1hc3BlZWQuYwo+ID4gaW5kZXggNDlhZWJhOTEyNTMxLi4y MzU4NmFhYzdhNWEgMTAwNjQ0Cj4gPiAtLS0gYS9kcml2ZXJzL3BpbmN0cmwvYXNwZWVkL3BpbmN0 cmwtYXNwZWVkLmMKPiA+ICsrKyBiL2RyaXZlcnMvcGluY3RybC9hc3BlZWQvcGluY3RybC1hc3Bl ZWQuYwo+ID4gQEAgLTE0LDYgKzE0LDEyIEBACj4gPiDCoCNpbmNsdWRlICIuLi9jb3JlLmgiCj4g PiDCoCNpbmNsdWRlICJwaW5jdHJsLWFzcGVlZC5oIgo+ID4gCj4gPiArc3RhdGljIGNvbnN0IGNo YXIgKmNvbnN0IGFzcGVlZF9waW5tdXhfaXBzW10gPSB7Cj4gPiArwqDCoMKgwqDCoMKgwqBbQVNQ RUVEX0lQX1NDVV0gPSAiU0NVIiwKPiA+ICvCoMKgwqDCoMKgwqDCoFtBU1BFRURfSVBfR0ZYXSA9 ICJHRlgiLAo+ID4gK8KgwqDCoMKgwqDCoMKgW0FTUEVFRF9JUF9MUENIQ10gPSAiTEhDUiIsCj4g V2UndmUgZ290IGJvdGggTFBDSEMgYW5kIExIQ1IgaGVyZS4gQXMgSSBzYWlkIHdoZW4gY29tbWVu dGluZyBvbiB0aGUKPiByZWdtYXAgYmluZGluZ3MsIEkgbGlrZSBMSEMoUikgYmV0dGVyLgo+IAo+ ID4gCj4gPiArfTsKPiA+ICsKPiA+IMKgaW50IGFzcGVlZF9waW5jdHJsX2dldF9ncm91cHNfY291 bnQoc3RydWN0IHBpbmN0cmxfZGV2ICpwY3RsZGV2KQo+ID4gwqB7Cj4gPiDCoMKgwqDCoMKgwqDC oMKgc3RydWN0IGFzcGVlZF9waW5jdHJsX2RhdGEgKnBkYXRhID0gcGluY3RybF9kZXZfZ2V0X2Ry dmRhdGEocGN0bGRldik7Cj4gPiBAQCAtNzgsNyArODQsOCBAQCBpbnQgYXNwZWVkX3Bpbm11eF9n ZXRfZm5fZ3JvdXBzKHN0cnVjdCBwaW5jdHJsX2RldiAqcGN0bGRldiwKPiA+IMKgc3RhdGljIGlu bGluZSB2b2lkIGFzcGVlZF9zaWdfZGVzY19wcmludF92YWwoCj4gPiDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoGNvbnN0IHN0cnVjdCBhc3BlZWRfc2lnX2Rlc2MgKmRlc2MsIGJvb2wg ZW5hYmxlLCB1MzIgcnYpCj4gV2hhdCdzIGEgcnY/IFBlcmhhcHMgInJlZyIgb3IgInZhbHVlIj8K PiAKPiA+IAo+ID4gwqB7Cj4gPiAtwqDCoMKgwqDCoMKgwqBwcl9kZWJ1ZygiU0NVJXhbMHglMDh4 XT0weCV4LCBnb3QgMHgleCBmcm9tIDB4JTA4eFxuIiwgZGVzYy0+cmVnLAo+ID4gK8KgwqDCoMKg wqDCoMKgcHJfZGVidWcoIldhbnQgJXMlWFsweCUwOFhdPTB4JVgsIGdvdCAweCVYIGZyb20gMHgl MDhYXG4iLAo+ID4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqBhc3BlZWRfcGlubXV4X2lwc1tkZXNjLT5pcF0sIGRlc2MtPnJlZywKPiA+IMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoGRlc2MtPm1hc2ssIGVuYWJsZSA/ IGRlc2MtPmVuYWJsZSA6IGRlc2MtPmRpc2FibGUsCj4gPiDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAocnYgJiBkZXNjLT5tYXNrKSA+PiBfX2ZmcyhkZXNj LT5tYXNrKSwgcnYpOwo+ID4gwqB9Cj4gPiBAQCAtODgsNyArOTUsNyBAQCBzdGF0aWMgaW5saW5l IHZvaWQgYXNwZWVkX3NpZ19kZXNjX3ByaW50X3ZhbCgKPiA+IMKgICoKPiA+IMKgICogQGRlc2M6 IFRoZSBzaWduYWwgZGVzY3JpcHRvciBvZiBpbnRlcmVzdAo+ID4gwqAgKiBAZW5hYmxlZDogVHJ1 ZSB0byBxdWVyeSB0aGUgZW5hYmxlZCBzdGF0ZSwgZmFsc2UgdG8gcXVlcnkgZGlzYWJsZWQgc3Rh dGUKPiA+IC0gKiBAcmVnbWFwOiBUaGUgU0NVIHJlZ21hcCBpbnN0YW5jZQo+ID4gKyAqIEByZWdt YXA6IFRoZSBJUCBibG9jaydzIHJlZ21hcCBpbnN0YW5jZQo+ID4gwqAgKgo+ID4gwqAgKiBAcmV0 dXJuIFRydWUgaWYgdGhlIGRlc2NyaXB0b3IncyBiaXRmaWVsZCBpcyBjb25maWd1cmVkIHRvIHRo ZSBzdGF0ZQo+ID4gwqAgKiBzZWxlY3RlZCBieSBAZW5hYmxlZCwgZmFsc2Ugb3RoZXJ3aXNlCj4g PiBAQCAtMTE5LDcgKzEyNiw3IEBAIHN0YXRpYyBib29sIGFzcGVlZF9zaWdfZGVzY19ldmFsKGNv bnN0IHN0cnVjdCBhc3BlZWRfc2lnX2Rlc2MgKmRlc2MsCj4gPiDCoCAqCj4gPiDCoCAqIEBleHBy OiBBbiBleHByZXNzaW9uIGNvbnRyb2xsaW5nIHRoZSBzaWduYWwgZm9yIGEgbXV4IGZ1bmN0aW9u IG9uIGEgcGluCj4gPiDCoCAqIEBlbmFibGVkOiBUcnVlIHRvIHF1ZXJ5IHRoZSBlbmFibGVkIHN0 YXRlLCBmYWxzZSB0byBxdWVyeSBkaXNhYmxlZCBzdGF0ZQo+ID4gLSAqIEByZWdtYXA6IFRoZSBT Q1UgcmVnbWFwIGluc3RhbmNlCj4gPiArICogQG1hcHM6IFRoZSBsaXN0IG9mIHJlZ21hcCBpbnN0 YW5jZXMKPiA+IMKgICoKPiA+IMKgICogQHJldHVybiBUcnVlIGlmIHRoZSBleHByZXNzaW9uIGNv bXBvc2VkIGJ5IEBlbmFibGVkIGV2YWx1YXRlcyB0cnVlLCBmYWxzZQo+ID4gwqAgKiBvdGhlcndp c2UKPiA+IEBAIC0xMzYsMTUgKzE0MywxNiBAQCBzdGF0aWMgYm9vbCBhc3BlZWRfc2lnX2Rlc2Nf ZXZhbChjb25zdCBzdHJ1Y3QgYXNwZWVkX3NpZ19kZXNjICpkZXNjLAo+ID4gwqAgKiBlaXRoZXIg Y29uZGl0aW9uIGFzIHJlcXVpcmVkLgo+ID4gwqAgKi8KPiA+IMKgc3RhdGljIGJvb2wgYXNwZWVk X3NpZ19leHByX2V2YWwoY29uc3Qgc3RydWN0IGFzcGVlZF9zaWdfZXhwciAqZXhwciwKPiA+IC3C oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgYm9vbCBlbmFibGVkLCBzdHJ1Y3QgcmVnbWFwICptYXApCj4gPiArwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoGJvb2wg ZW5hYmxlZCwgc3RydWN0IHJlZ21hcCAqIGNvbnN0ICptYXBzKQo+ID4gwqB7Cj4gPiDCoMKgwqDC oMKgwqDCoMKgaW50IGk7Cj4gPiAKPiA+IMKgwqDCoMKgwqDCoMKgwqBmb3IgKGkgPSAwOyBpIDwg ZXhwci0+bmRlc2NzOyBpKyspIHsKPiA+IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg Y29uc3Qgc3RydWN0IGFzcGVlZF9zaWdfZGVzYyAqZGVzYyA9ICZleHByLT5kZXNjc1tpXTsKPiA+ IAo+ID4gLcKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoGlmICghYXNwZWVkX3NpZ19kZXNj X2V2YWwoZGVzYywgZW5hYmxlZCwgbWFwKSkKPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqBpZiAoIWFzcGVlZF9zaWdfZGVzY19ldmFsKGRlc2MsIGVuYWJsZWQsIG1hcHNbZGVzYy0+ aXBdKSkKPiA+IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oHJldHVybiBmYWxzZTsKPiA+ICsKPiA+IMKgwqDCoMKgwqDCoMKgwqB9Cj4gPiAKPiA+IMKgwqDC oMKgwqDCoMKgwqByZXR1cm4gdHJ1ZTsKPiA+IEBAIC0xNTgsMTIgKzE2NiwxMiBAQCBzdGF0aWMg Ym9vbCBhc3BlZWRfc2lnX2V4cHJfZXZhbChjb25zdCBzdHJ1Y3QgYXNwZWVkX3NpZ19leHByICpl eHByLAo+ID4gwqAgKsKgwqDCoMKgwqDCoMKgwqBjb25maWd1cmVkCj4gPiDCoCAqIEBlbmFibGU6 IHRydWUgdG8gZW5hYmxlIGFuIGZ1bmN0aW9uJ3Mgc2lnbmFsIHRocm91Z2ggYSBwaW4ncyBzaWdu YWwKPiA+IMKgICrCoMKgwqDCoMKgwqDCoMKgwqDCoGV4cHJlc3Npb24sIGZhbHNlIHRvIGRpc2Fi bGUgdGhlIGZ1bmN0aW9uJ3Mgc2lnbmFsCj4gPiAtICogQG1hcDogVGhlIFNDVSdzIHJlZ21hcCBp bnN0YW5jZSBmb3IgcGlubXV4IHJlZ2lzdGVyIGFjY2Vzcy4KPiA+ICsgKiBAbWFwczogVGhlIGxp c3Qgb2YgcmVnbWFwIGluc3RhbmNlcyBmb3IgcGlubXV4IHJlZ2lzdGVyIGFjY2Vzcy4KPiA+IMKg ICoKPiA+IMKgICogQHJldHVybiB0cnVlIGlmIHRoZSBleHByZXNzaW9uIGlzIGNvbmZpZ3VyZWQg YXMgcmVxdWVzdGVkLCBmYWxzZSBvdGhlcndpc2UKPiA+IMKgICovCj4gPiDCoHN0YXRpYyBib29s IGFzcGVlZF9zaWdfZXhwcl9zZXQoY29uc3Qgc3RydWN0IGFzcGVlZF9zaWdfZXhwciAqZXhwciwK PiA+IC3CoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoGJvb2wgZW5hYmxlLCBzdHJ1Y3QgcmVnbWFwICptYXApCj4gPiArwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBib29s IGVuYWJsZSwgc3RydWN0IHJlZ21hcCAqIGNvbnN0ICptYXBzKQo+ID4gwqB7Cj4gPiDCoMKgwqDC oMKgwqDCoMKgaW50IGk7Cj4gPiAKPiA+IEBAIC0xNzEsNiArMTc5LDcgQEAgc3RhdGljIGJvb2wg YXNwZWVkX3NpZ19leHByX3NldChjb25zdCBzdHJ1Y3QgYXNwZWVkX3NpZ19leHByICpleHByLAo+ ID4gwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBib29sIHJldDsKPiA+IMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgY29uc3Qgc3RydWN0IGFzcGVlZF9zaWdfZGVzYyAqZGVz YyA9ICZleHByLT5kZXNjc1tpXTsKPiA+IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg dTMyIHBhdHRlcm4gPSBlbmFibGUgPyBkZXNjLT5lbmFibGUgOiBkZXNjLT5kaXNhYmxlOwo+ID4g K8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoHUzMiB2YWwgPSAocGF0dGVybiA8PCBfX2Zm cyhkZXNjLT5tYXNrKSk7Cj4gPiAKPiA+IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg LyoKPiA+IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAqIFN0cmFwIHJlZ2lzdGVy cyBhcmUgY29uZmlndXJlZCBpbiBoYXJkd2FyZSBvciBieSBlYXJseS1ib290Cj4gPiBAQCAtMTc5 LDQ4ICsxODgsNDkgQEAgc3RhdGljIGJvb2wgYXNwZWVkX3NpZ19leHByX3NldChjb25zdCBzdHJ1 Y3QgYXNwZWVkX3NpZ19leHByICpleHByLAo+ID4gwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoCogZGVjb25maWd1cmVkIGFuZCBpcyB0aGUgcmVhc29uIHdlIHJlLWV2YWx1YXRlIGFm dGVyIHdyaXRpbmcKPiA+IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAqIGFsbCBk ZXNjcmlwdG9yIGJpdHMuCj4gPiDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgKi8K PiA+IC3CoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBpZiAoZGVzYy0+cmVnID09IEhXX1NU UkFQMSB8fCBkZXNjLT5yZWcgPT0gSFdfU1RSQVAyKQo+ID4gK8KgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoGlmICgoZGVzYy0+cmVnID09IEhXX1NUUkFQMSB8fCBkZXNjLT5yZWcgPT0gSFdf U1RSQVAyKSAmJgo+ID4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgZGVzYy0+aXAgPT0gQVNQRUVEX0lQX1NDVSkKPiA+IMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoGNvbnRpbnVlOwo+ID4g Cj4gPiAtwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgcmV0ID0gcmVnbWFwX3VwZGF0ZV9i aXRzKG1hcCwgZGVzYy0+cmVnLCBkZXNjLT5tYXNrLAo+ID4gLcKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgcGF0dGVybiA8PCBfX2Zm cyhkZXNjLT5tYXNrKSkgPT0gMDsKPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBy ZXQgPSByZWdtYXBfdXBkYXRlX2JpdHMobWFwc1tkZXNjLT5pcF0sIGRlc2MtPnJlZywKPiA+ICvC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoGRlc2MtPm1hc2ssIHZhbCkgPT0gMDsKPiA+IAo+ID4gwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBpZiAoIXJldCkKPiA+IMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoHJldHVybiByZXQ7Cj4gPiDCoMKgwqDC oMKgwqDCoMKgfQo+ID4gCj4gPiAtwqDCoMKgwqDCoMKgwqByZXR1cm4gYXNwZWVkX3NpZ19leHBy X2V2YWwoZXhwciwgZW5hYmxlLCBtYXApOwo+ID4gK8KgwqDCoMKgwqDCoMKgcmV0dXJuIGFzcGVl ZF9zaWdfZXhwcl9ldmFsKGV4cHIsIGVuYWJsZSwgbWFwcyk7Cj4gPiDCoH0KPiA+IAo+ID4gwqBz dGF0aWMgYm9vbCBhc3BlZWRfc2lnX2V4cHJfZW5hYmxlKGNvbnN0IHN0cnVjdCBhc3BlZWRfc2ln X2V4cHIgKmV4cHIsCj4gPiAtwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBzdHJ1Y3QgcmVnbWFwICptYXApCj4gPiArwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqBzdHJ1Y3QgcmVnbWFwICogY29uc3QgKm1hcHMpCj4gPiDCoHsKPiA+IC3CoMKgwqDC oMKgwqDCoGlmIChhc3BlZWRfc2lnX2V4cHJfZXZhbChleHByLCB0cnVlLCBtYXApKQo+ID4gK8Kg wqDCoMKgwqDCoMKgaWYgKGFzcGVlZF9zaWdfZXhwcl9ldmFsKGV4cHIsIHRydWUsIG1hcHMpKQo+ ID4gwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqByZXR1cm4gdHJ1ZTsKPiA+IAo+ID4g LcKgwqDCoMKgwqDCoMKgcmV0dXJuIGFzcGVlZF9zaWdfZXhwcl9zZXQoZXhwciwgdHJ1ZSwgbWFw KTsKPiA+ICvCoMKgwqDCoMKgwqDCoHJldHVybiBhc3BlZWRfc2lnX2V4cHJfc2V0KGV4cHIsIHRy dWUsIG1hcHMpOwo+ID4gwqB9Cj4gPiAKPiA+IMKgc3RhdGljIGJvb2wgYXNwZWVkX3NpZ19leHBy X2Rpc2FibGUoY29uc3Qgc3RydWN0IGFzcGVlZF9zaWdfZXhwciAqZXhwciwKPiA+IC3CoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgc3RydWN0IHJlZ21hcCAqbWFwKQo+ID4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBzdHJ1Y3QgcmVnbWFw ICogY29uc3QgKm1hcHMpCj4gPiDCoHsKPiA+IC3CoMKgwqDCoMKgwqDCoGlmICghYXNwZWVkX3Np Z19leHByX2V2YWwoZXhwciwgdHJ1ZSwgbWFwKSkKPiA+ICvCoMKgwqDCoMKgwqDCoGlmICghYXNw ZWVkX3NpZ19leHByX2V2YWwoZXhwciwgdHJ1ZSwgbWFwcykpCj4gPiDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoHJldHVybiB0cnVlOwo+ID4gCj4gPiAtwqDCoMKgwqDCoMKgwqByZXR1 cm4gYXNwZWVkX3NpZ19leHByX3NldChleHByLCBmYWxzZSwgbWFwKTsKPiA+ICvCoMKgwqDCoMKg wqDCoHJldHVybiBhc3BlZWRfc2lnX2V4cHJfc2V0KGV4cHIsIGZhbHNlLCBtYXBzKTsKPiA+IMKg fQo+ID4gCj4gPiDCoC8qKgo+ID4gwqAgKiBEaXNhYmxlIGEgc2lnbmFsIG9uIGEgcGluIGJ5IGRp c2FibGluZyBhbGwgcHJvdmlkZWQgc2lnbmFsIGV4cHJlc3Npb25zLgo+ID4gwqAgKgo+ID4gwqAg KiBAZXhwcnM6IFRoZSBsaXN0IG9mIHNpZ25hbCBleHByZXNzaW9ucyAoZnJvbSBhIHByaW9yaXR5 IGxldmVsIG9uIGEgcGluKQo+ID4gLSAqIEBtYXA6IFRoZSBTQ1UncyByZWdtYXAgaW5zdGFuY2Ug Zm9yIHBpbm11eCByZWdpc3RlciBhY2Nlc3MuCj4gPiArICogQG1hcHM6IFRoZSBsaXN0IG9mIHJl Z21hcCBpbnN0YW5jZXMgZm9yIHBpbm11eCByZWdpc3RlciBhY2Nlc3MuCj4gPiDCoCAqCj4gPiDC oCAqIEByZXR1cm4gdHJ1ZSBpZiBhbGwgZXhwcmVzc2lvbnMgaW4gdGhlIGxpc3QgYXJlIHN1Y2Nl c3NmdWxseSBkaXNhYmxlZCwgZmFsc2UKPiA+IMKgICogb3RoZXJ3aXNlCj4gPiDCoCAqLwo+ID4g wqBzdGF0aWMgYm9vbCBhc3BlZWRfZGlzYWJsZV9zaWcoY29uc3Qgc3RydWN0IGFzcGVlZF9zaWdf ZXhwciAqKmV4cHJzLAo+ID4gLcKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoHN0cnVjdCByZWdtYXAgKm1hcCkKPiA+ICvCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBzdHJ1Y3Qg cmVnbWFwICogY29uc3QgKm1hcHMpCj4gPiDCoHsKPiA+IMKgwqDCoMKgwqDCoMKgwqBib29sIGRp c2FibGVkID0gdHJ1ZTsKPiA+IAo+ID4gQEAgLTIzMCw3ICsyNDAsNyBAQCBzdGF0aWMgYm9vbCBh c3BlZWRfZGlzYWJsZV9zaWcoY29uc3Qgc3RydWN0IGFzcGVlZF9zaWdfZXhwciAqKmV4cHJzLAo+ ID4gwqDCoMKgwqDCoMKgwqDCoHdoaWxlICgqZXhwcnMpIHsKPiA+IMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgYm9vbCByZXQ7Cj4gPiAKPiA+IC3CoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqByZXQgPSBhc3BlZWRfc2lnX2V4cHJfZGlzYWJsZSgqZXhwcnMsIG1hcCk7Cj4gPiAr wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgcmV0ID0gYXNwZWVkX3NpZ19leHByX2Rpc2Fi bGUoKmV4cHJzLCBtYXBzKTsKPiA+IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgZGlz YWJsZWQgPSBkaXNhYmxlZCAmJiByZXQ7Cj4gPiAKPiA+IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgZXhwcnMrKzsKPiA+IEBAIC0zNDMsNiArMzUzLDggQEAgaW50IGFzcGVlZF9waW5t dXhfc2V0X211eChzdHJ1Y3QgcGluY3RybF9kZXYgKnBjdGxkZXYsIHVuc2lnbmVkIGludCBmdW5j dGlvbiwKPiA+IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgY29uc3Qgc3RydWN0IGFz cGVlZF9zaWdfZXhwciAqKmZ1bmNzOwo+ID4gwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqBjb25zdCBzdHJ1Y3QgYXNwZWVkX3NpZ19leHByICoqKnByaW9zOwo+ID4gCj4gPiArwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgcHJfZGVidWcoIk11eGluZyBwaW4gJWQgZm9yICVzXG4i LCBwaW4sIHBmdW5jLT5uYW1lKTsKPiA+ICsKPiA+IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgaWYgKCFwZGVzYykKPiA+IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoHJldHVybiAtRUlOVkFMOwo+ID4gCj4gPiBAQCAtMzU4LDcgKzM3MCw3IEBA IGludCBhc3BlZWRfcGlubXV4X3NldF9tdXgoc3RydWN0IHBpbmN0cmxfZGV2ICpwY3RsZGV2LCB1 bnNpZ25lZCBpbnQgZnVuY3Rpb24sCj4gPiDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqBpZiAoZXhwcikKPiA+IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBicmVhazsKPiA+IAo+ID4gLcKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBpZiAoIWFzcGVlZF9k aXNhYmxlX3NpZyhmdW5jcywgcGRhdGEtPm1hcCkpCj4gPiArwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoGlmICghYXNwZWVkX2Rpc2FibGVfc2lnKGZ1bmNzLCBw ZGF0YS0+bWFwcykpCj4gPiDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgcmV0dXJuIC1FUEVSTTsKPiA+IAo+ID4gwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgcHJpb3MrKzsKPiA+IEBAIC0z NzcsNyArMzg5LDcgQEAgaW50IGFzcGVlZF9waW5tdXhfc2V0X211eChzdHJ1Y3QgcGluY3RybF9k ZXYgKnBjdGxkZXYsIHVuc2lnbmVkIGludCBmdW5jdGlvbiwKPiA+IMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoHJldHVybiAtRU5YSU87Cj4gPiDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoH0KPiA+IAo+ID4gLcKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoGlmICghYXNwZWVkX3NpZ19leHByX2VuYWJsZShleHByLCBwZGF0YS0+bWFwKSkK PiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBpZiAoIWFzcGVlZF9zaWdfZXhwcl9l bmFibGUoZXhwciwgcGRhdGEtPm1hcHMpKQo+ID4gwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgcmV0dXJuIC1FUEVSTTsKPiA+IMKgwqDCoMKgwqDCoMKgwqB9 Cj4gPiAKPiA+IEBAIC00MzIsNyArNDQ0LDcgQEAgaW50IGFzcGVlZF9ncGlvX3JlcXVlc3RfZW5h YmxlKHN0cnVjdCBwaW5jdHJsX2RldiAqcGN0bGRldiwKPiA+IMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgaWYgKGFzcGVlZF9ncGlvX2luX2V4cHJzKGZ1bmNzKSkKPiA+IMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoGJyZWFrOwo+ID4gCj4gPiAt wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgaWYgKCFhc3BlZWRfZGlzYWJsZV9zaWcoZnVu Y3MsIHBkYXRhLT5tYXApKQo+ID4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoGlmICgh YXNwZWVkX2Rpc2FibGVfc2lnKGZ1bmNzLCBwZGF0YS0+bWFwcykpCj4gPiDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqByZXR1cm4gLUVQRVJNOwo+ID4gCj4g PiDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoHByaW9zKys7Cj4gPiBAQCAtNDYyLDcg KzQ3NCw3IEBAIGludCBhc3BlZWRfZ3Bpb19yZXF1ZXN0X2VuYWJsZShzdHJ1Y3QgcGluY3RybF9k ZXYgKnBjdGxkZXYsCj4gPiDCoMKgwqDCoMKgwqDCoMKgwqAqIElmIEdQSU8gaXMgbm90IHRoZSBs b3dlc3QgcHJpb3JpdHkgc2lnbmFsIHR5cGUsIGFzc3VtZSB0aGVyZSBpcyBvbmx5Cj4gPiDCoMKg wqDCoMKgwqDCoMKgwqAqIG9uZSBleHByZXNzaW9uIGRlZmluZWQgdG8gZW5hYmxlIHRoZSBHUElP IGZ1bmN0aW9uCj4gPiDCoMKgwqDCoMKgwqDCoMKgwqAqLwo+ID4gLcKgwqDCoMKgwqDCoMKgaWYg KCFhc3BlZWRfc2lnX2V4cHJfZW5hYmxlKGV4cHIsIHBkYXRhLT5tYXApKQo+ID4gK8KgwqDCoMKg wqDCoMKgaWYgKCFhc3BlZWRfc2lnX2V4cHJfZW5hYmxlKGV4cHIsIHBkYXRhLT5tYXBzKSkKPiA+ IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgcmV0dXJuIC1FUEVSTTsKPiA+IAo+ID4g wqDCoMKgwqDCoMKgwqDCoHJldHVybiAwOwo+ID4gQEAgLTQ4MSwxMCArNDkzLDEwIEBAIGludCBh c3BlZWRfcGluY3RybF9wcm9iZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2LAo+ID4gwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqByZXR1cm4gLUVOT0RFVjsKPiA+IMKgwqDCoMKg wqDCoMKgwqB9Cj4gPiAKPiA+IC3CoMKgwqDCoMKgwqDCoHBkYXRhLT5tYXAgPSBzeXNjb25fbm9k ZV90b19yZWdtYXAocGFyZW50LT5vZl9ub2RlKTsKPiA+IC3CoMKgwqDCoMKgwqDCoGlmIChJU19F UlIocGRhdGEtPm1hcCkpIHsKPiA+ICvCoMKgwqDCoMKgwqDCoHBkYXRhLT5tYXBzW0FTUEVFRF9J UF9TQ1VdID0gc3lzY29uX25vZGVfdG9fcmVnbWFwKHBhcmVudC0+b2Zfbm9kZSk7Cj4gPiArwqDC oMKgwqDCoMKgwqBpZiAoSVNfRVJSKHBkYXRhLT5tYXBzW0FTUEVFRF9JUF9TQ1VdKSkgewo+ID4g wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBkZXZfZXJyKCZwZGV2LT5kZXYsICJObyBy ZWdtYXAgZm9yIHN5c2NvbiBwaW5jb250cm9sbGVyIHBhcmVudFxuIik7Cj4gPiAtwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgcmV0dXJuIFBUUl9FUlIocGRhdGEtPm1hcCk7Cj4gPiArwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgcmV0dXJuIFBUUl9FUlIocGRhdGEtPm1hcHNbQVNQ RUVEX0lQX1NDVV0pOwo+ID4gwqDCoMKgwqDCoMKgwqDCoH0KPiA+IAo+ID4gwqDCoMKgwqDCoMKg wqDCoHBjdGwgPSBwaW5jdHJsX3JlZ2lzdGVyKHBkZXNjLCAmcGRldi0+ZGV2LCBwZGF0YSk7Cj4g PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9waW5jdHJsL2FzcGVlZC9waW5jdHJsLWFzcGVlZC5oIGIv ZHJpdmVycy9waW5jdHJsL2FzcGVlZC9waW5jdHJsLWFzcGVlZC5oCj4gPiBpbmRleCAzZTcyZWY4 YzU0YmYuLjcyNzcyOGI4NmMwNyAxMDA2NDQKPiA+IC0tLSBhL2RyaXZlcnMvcGluY3RybC9hc3Bl ZWQvcGluY3RybC1hc3BlZWQuaAo+ID4gKysrIGIvZHJpdmVycy9waW5jdHJsL2FzcGVlZC9waW5j dHJsLWFzcGVlZC5oCj4gPiBAQCAtMjMyLDYgKzIzMiwxMSBAQAo+ID4gwqAgKiBncm91cC4KPiA+ IMKgICovCj4gPiAKPiA+ICsjZGVmaW5lIEFTUEVFRF9JUF9TQ1XCoMKgMAo+ID4gKyNkZWZpbmUg QVNQRUVEX0lQX0dGWMKgwqAxCj4gPiArI2RlZmluZSBBU1BFRURfSVBfTFBDSEPCoMKgwqDCoMKg wqDCoMKgMgo+ID4gKyNkZWZpbmUgQVNQRUVEX05SX1BJTk1VWF9JUFPCoMKgwqAzCj4gPiArCj4g PiDCoC8qCj4gPiDCoCAqIFRoZSAiTXVsdGktZnVuY3Rpb24gUGlucyBNYXBwaW5nIGFuZCBDb250 cm9sIiB0YWJsZSBpbiB0aGUgU29DIGRhdGFzaGVldAo+ID4gwqAgKiByZWZlcmVuY2VzIHJlZ2lz dGVycyBieSB0aGUgZGV2aWNlL29mZnNldCBtbmVtb25pYy4gVGhlIHJlZ2lzdGVyIG1hY3Jvcwo+ ID4gQEAgLTI2MSw3ICsyNjYsOSBAQAo+ID4gwqDCoMKgKiBBIHNpZ25hbCBkZXNjcmlwdG9yLCB3 aGljaCBkZXNjcmliZXMgdGhlIHJlZ2lzdGVyLCBiaXRzIGFuZCB0aGUKPiA+IMKgwqDCoCogZW5h YmxlL2Rpc2FibGUgdmFsdWVzIHRoYXQgc2hvdWxkIGJlIGNvbXBhcmVkIG9yIHdyaXR0ZW4uCj4g PiDCoMKgwqAqCj4gPiAtwqDCoCogQHJlZzogVGhlIHJlZ2lzdGVyIG9mZnNldCBmcm9tIGJhc2Ug aW4gYnl0ZXMKPiA+ICvCoMKgKiBAaXA6IFRoZSBJUCBibG9jayBpZGVudGlmaWVyLCB1c2VkIGFz IGFuIGluZGV4IGludG8gdGhlIHJlZ21hcCBhcnJheSBpbgo+ID4gK8KgwqAqwqDCoMKgwqDCoMKg c3RydWN0IGFzcGVlZF9waW5jdHJsX2RhdGEKPiA+ICvCoMKgKiBAcmVnOiBUaGUgcmVnaXN0ZXIg b2Zmc2V0IHdpdGggcmVzcGVjdCB0byB0aGUgYmFzZSBhZGRyZXNzIG9mIHRoZSBJUCBibG9jawo+ ID4gwqDCoMKgKiBAbWFzazogVGhlIG1hc2sgdG8gYXBwbHkgdG8gdGhlIHJlZ2lzdGVyLiBUaGUg bG93ZXN0IHNldCBiaXQgb2YgdGhlIG1hc2sgaXMKPiA+IMKgwqDCoCrCoMKgwqDCoMKgwqDCoMKg dXNlZCB0byBkZXJpdmUgdGhlIHNoaWZ0IHZhbHVlLgo+ID4gwqDCoMKgKiBAZW5hYmxlOiBUaGUg dmFsdWUgdGhhdCBlbmFibGVzIHRoZSBmdW5jdGlvbi4gVmFsdWUgc2hvdWxkIGJlIGluIHRoZSBM U0JzLAo+ID4gQEAgLTI3MCw2ICsyNzcsNyBAQAo+ID4gwqDCoMKgKsKgwqDCoMKgwqDCoMKgwqDC oMKgwqBMU0JzLCBub3QgYXQgdGhlIHBvc2l0aW9uIG9mIHRoZSBtYXNrLgo+ID4gwqDCoMKgKi8K PiA+IMKgc3RydWN0IGFzcGVlZF9zaWdfZGVzYyB7Cj4gPiArwqDCoMKgwqDCoMKgwqB1bnNpZ25l ZCBpbnQgaXA7Cj4gPiDCoMKgwqDCoMKgwqDCoMKgdW5zaWduZWQgaW50IHJlZzsKPiA+IMKgwqDC oMKgwqDCoMKgwqB1MzIgbWFzazsKPiA+IMKgwqDCoMKgwqDCoMKgwqB1MzIgZW5hYmxlOwo+ID4g QEAgLTMxMywyNCArMzIxLDMwIEBAIHN0cnVjdCBhc3BlZWRfcGluX2Rlc2Mgewo+ID4gCj4gPiDC oC8qIE1hY3JvIGhlbGwgKi8KPiA+IAo+ID4gKyNkZWZpbmUgU0lHX0RFU0NfSVBfQklUKGlwLCBy ZWcsIGlkeCwgdmFsKSBcCj4gPiArwqDCoMKgwqDCoMKgwqB7IGlwLCByZWcsIEJJVF9NQVNLKGlk eCksIHZhbCwgKCgodmFsKSArIDEpICYgMSkgfQo+ID4gKwo+ID4gwqAvKioKPiA+IC0gKiBTaG9y dC1oYW5kIG1hY3JvIGZvciBkZXNjcmliaW5nIGEgY29uZmlndXJhdGlvbiBlbmFibGVkIGJ5IHRo ZSBzdGF0ZSBvZiBvbmUKPiA+IC0gKiBiaXQuIFRoZSBkaXNhYmxlIHZhbHVlIGlzIGRlcml2ZWQu Cj4gPiArICogU2hvcnQtaGFuZCBtYWNybyBmb3IgZGVzY3JpYmluZyBhbiBTQ1UgZGVzY3JpcHRv ciBlbmFibGVkIGJ5IHRoZSBzdGF0ZSBvZgo+ID4gKyAqIG9uZSBiaXQuIFRoZSBkaXNhYmxlIHZh bHVlIGlzIGRlcml2ZWQuCj4gPiDCoCAqCj4gPiDCoCAqIEByZWc6IFRoZSBzaWduYWwncyBhc3Nv Y2lhdGVkIHJlZ2lzdGVyLCBvZmZzZXQgZnJvbSBiYXNlCj4gPiDCoCAqIEBpZHg6IFRoZSBzaWdu YWwncyBiaXQgaW5kZXggaW4gdGhlIHJlZ2lzdGVyCj4gPiDCoCAqIEB2YWw6IFRoZSB2YWx1ZSAo MCBvciAxKSB0aGF0IGVuYWJsZXMgdGhlIGZ1bmN0aW9uCj4gPiDCoCAqLwo+ID4gwqAjZGVmaW5l IFNJR19ERVNDX0JJVChyZWcsIGlkeCwgdmFsKSBcCj4gPiAtwqDCoMKgwqDCoMKgwqB7IHJlZywg QklUX01BU0soaWR4KSwgdmFsLCAoKCh2YWwpICsgMSkgJiAxKSB9Cj4gPiArwqDCoMKgwqDCoMKg wqBTSUdfREVTQ19JUF9CSVQoQVNQRUVEX0lQX1NDVSwgcmVnLCBpZHgsIHZhbCkKPiA+ICsKPiA+ ICsjZGVmaW5lIFNJR19ERVNDX0lQX1NFVChpcCwgcmVnLCBpZHgpIFNJR19ERVNDX0lQX0JJVChp cCwgcmVnLCBpZHgsIDEpCj4gPiAKPiA+IMKgLyoqCj4gPiAtICogQSBmdXJ0aGVyIHNob3J0LWhh bmQgbWFjcm8gZGVzY3JpYmluZyBhIGNvbmZpZ3VyYXRpb24gZW5hYmxlZCB3aXRoIGEgc2V0IGJp dC4KPiA+ICsgKiBBIGZ1cnRoZXIgc2hvcnQtaGFuZCBtYWNybyBleHBhbmRpbmcgdG8gYW4gU0NV IGRlc2NyaXB0b3IgZW5hYmxlZCBieSBhIHNldAo+ID4gKyAqIGJpdC4KPiA+IMKgICoKPiA+IC0g KiBAcmVnOiBUaGUgY29uZmlndXJhdGlvbidzIGFzc29jaWF0ZWQgcmVnaXN0ZXIsIG9mZnNldCBm cm9tIGJhc2UKPiA+IC0gKiBAaWR4OiBUaGUgY29uZmlndXJhdGlvbidzIGJpdCBpbmRleCBpbiB0 aGUgcmVnaXN0ZXIKPiA+ICsgKiBAcmVnOiBUaGUgcmVnaXN0ZXIsIG9mZnNldCBmcm9tIGJhc2UK PiA+ICsgKiBAaWR4OiBUaGUgYml0IGluZGV4IGluIHRoZSByZWdpc3Rlcgo+ID4gwqAgKi8KPiA+ IC0jZGVmaW5lIFNJR19ERVNDX1NFVChyZWcsIGlkeCkgU0lHX0RFU0NfQklUKHJlZywgaWR4LCAx KQo+ID4gKyNkZWZpbmUgU0lHX0RFU0NfU0VUKHJlZywgaWR4KSBTSUdfREVTQ19JUF9CSVQoQVNQ RUVEX0lQX1NDVSwgcmVnLCBpZHgsIDEpCj4gPiAKPiA+IMKgI2RlZmluZSBTSUdfREVTQ19MSVNU X1NZTShzaWcsIGZ1bmMpIHNpZ19kZXNjc18gIyMgc2lnICMjIF8gIyMgZnVuYwo+ID4gwqAjZGVm aW5lIFNJR19ERVNDX0xJU1RfREVDTChzaWcsIGZ1bmMsIC4uLikgXAo+ID4gQEAgLTUwMCw3ICs1 MTQsNyBAQCBzdHJ1Y3QgYXNwZWVkX3Bpbl9kZXNjIHsKPiA+IMKgwqDCoMKgwqDCoMKgwqBNU19Q SU5fREVDTF8ocGluLCBTSUdfRVhQUl9MSVNUX1BUUihncGlvKSkKPiA+IAo+ID4gwqBzdHJ1Y3Qg YXNwZWVkX3BpbmN0cmxfZGF0YSB7Cj4gPiAtwqDCoMKgwqDCoMKgwqBzdHJ1Y3QgcmVnbWFwICpt YXA7Cj4gPiArwqDCoMKgwqDCoMKgwqBzdHJ1Y3QgcmVnbWFwICptYXBzW0FTUEVFRF9OUl9QSU5N VVhfSVBTXTsKPiA+IAo+ID4gwqDCoMKgwqDCoMKgwqDCoGNvbnN0IHN0cnVjdCBwaW5jdHJsX3Bp bl9kZXNjICpwaW5zOwo+ID4gwqDCoMKgwqDCoMKgwqDCoGNvbnN0IHVuc2lnbmVkIGludCBucGlu czsKPiA+IC0tCj4gPiAyLjcuNAo+ID4g --=-+TMxMvOqGiI+odZ5dhyi Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCgAGBQJYHAe4AAoJEJ0dnzgO5LT5beMP/2r0zc2YTIfcL9SWo8lbACCv YTa4ThQxYzD/0BdGSJlVpCFoHjsKanehg2mbMailGuHlgJqF7IboeMvfMol5/iW6 /sXrD+K+M0DnXLmIEbBwRcr196Y7Q3+rEkJ+XUVo26B8jmdnT6VdKjxEzrnV6H5B jeAGv3suurLb06k6N9r/yK1zB88V6n8DNUf0fk2YjVJccCvygxSZrnAjJyd6QNMH secUkK2iZcLleJlJfn/KksZrntZmY/qX+bINflsCcxJIdR+pdXNaNNh38BxHEhrc FfmZKzLmH3qv5wQk7TGfBxJn9O1qHVm4t9ChSaru4nEmHlnGCZjUOyO4FpmkcstK y2LW2xyCXXcaF9DfzEa09QsLqIe8VSM59qCuc/1UFToJN9d0JLwyEZbyXorL/j2Z VoLY/vJ/xC81Ir4ltkAqgb2Hs/2dQdLsgLHtabIKiCJt2aA27jbhuipkh7GyMSgc 2V/b4LTdKAsahQnL6NrAoTUNsh3n5UPOmdpsl844Ll40n3tM6xp8WYiBt8Aqj5aL FSjkkt6HlnsYOcyZTwsl8FrvAbE8tCxTO4NrJb480zx8PiKgLJH/wq26WNZyUCo5 c/fRwqfeW35u/qfw2Y7TKhqHKwpQirjjjArXfF2zTWY7Y+KxMtvH6pmYC8FiNOBX KmW3+zjy9vGcSyYXuhy1 =Dcm/ -----END PGP SIGNATURE----- --=-+TMxMvOqGiI+odZ5dhyi-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: andrew@aj.id.au (Andrew Jeffery) Date: Fri, 04 Nov 2016 14:29:52 +1030 Subject: [PATCH v2 4/6] pinctrl: aspeed: Read and write bits in LPCHC and GFX controllers In-Reply-To: References: <1478097481-14895-1-git-send-email-andrew@aj.id.au> <1478097481-14895-5-git-send-email-andrew@aj.id.au> Message-ID: <1478231992.27396.79.camel@aj.id.au> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, 2016-11-04 at 09:54 +1030, Joel Stanley wrote: > On Thu, Nov 3, 2016 at 1:07 AM, Andrew Jeffery wrote: > > > > The System Control Unit IP block in the Aspeed SoCs is typically where > > the pinmux configuration is found, but not always. A number of pins > > depend on state in one of LPC Host Control (LPCHC) or SoC Display > > Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the > > means to adjust these as necessary. > > > > We use syscon to cast a regmap over the GFX and LPCHCR blocks, which is > > used as an arbitration layer between the relevant driver and the pinctrl > > subsystem. The regmaps are then exposed to the SoC-specific pinctrl > > drivers by phandles in the devicetree, and are selected during a mux > > request by querying a new 'ip' member in struct aspeed_sig_desc. > > > > Signed-off-by: Andrew Jeffery > I like this a lot more than the first go. Good work. > > Some minor comments below. > > > > > --- > > Since v1: > > > > The change is now proactive: instead of reporting that we need to flip bits in > > controllers we can't access, the patch provides access via regmaps for the > > relevant controllers. The implementation also splits out the IP block ID into > > its own variable rather than packing the value into the upper bits of the reg > > member of struct aspeed_sig_desc. This drives some churn in the diff, but I've > > tried to minimise it. > > > > ?.../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 50 +++++++++++++--- > > ?drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c?????????| 18 +++--- > > ?drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c?????????| 39 ++++++++++--- > > ?drivers/pinctrl/aspeed/pinctrl-aspeed.c????????????| 66 +++++++++++++--------- > > ?drivers/pinctrl/aspeed/pinctrl-aspeed.h????????????| 32 ++++++++--- > > ?5 files changed, 144 insertions(+), 61 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt > > index 2ad18c4ea55c..115b0cce6c1c 100644 > > --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt > > +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt > > @@ -4,12 +4,19 @@ Aspeed Pin Controllers > > ?The Aspeed SoCs vary in functionality inside a generation but have a common mux > > ?device register layout. > > > > -Required properties: > > -- compatible : Should be any one of the following: > > -???????????????"aspeed,ast2400-pinctrl" > > -???????????????"aspeed,g4-pinctrl" > > -???????????????"aspeed,ast2500-pinctrl" > > -???????????????"aspeed,g5-pinctrl" > > +Required properties for g4: > > +- compatible :?????????????????????????Should be any one of the following: > > +???????????????????????????????"aspeed,ast2400-pinctrl" > > +???????????????????????????????"aspeed,g4-pinctrl" > > + > > +Required properties for g5: > > +- compatible :?????????????????????????Should be any one of the following: > > +???????????????????????????????"aspeed,ast2500-pinctrl" > > +???????????????????????????????"aspeed,g5-pinctrl" > > + > > +- aspeed,external-nodes:???????A cell of phandles to external controller nodes: > > +???????????????????????????????0: compatible with "aspeed,ast2500-gfx", "syscon" > > +???????????????????????????????1: compatible with "aspeed,ast2500-lpchc", "syscon" > > > > ?The pin controller node should be a child of a syscon node with the required > > ?property: > > @@ -47,7 +54,7 @@ RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6 > > ?TIMER7 TIMER8 VGABIOSROM > > > > > > -Examples: > > +g4 Example: > > > > ?syscon: scu at 1e6e2000 { > > ????????compatible = "syscon", "simple-mfd"; > > @@ -63,5 +70,34 @@ syscon: scu at 1e6e2000 { > > ????????}; > > ?}; > > > > +g5 Example: > > + > > +apb { > > +???????gfx: display at 1e6e6000 { > > +???????????????compatible = "aspeed,ast2500-gfx", "syscon"; > > +???????????????reg = <0x1e6e6000 0x1000>; > > +???????}; > > + > > +???????lpchc: lpchc at 1e7890a0 { > > +???????????????compatible = "aspeed,ast2500-lpchc", "syscon"; > > +???????????????reg = <0x1e7890a0 0xc4>; > > +???????}; > > + > > +???????syscon: scu at 1e6e2000 { > > +???????????????compatible = "syscon", "simple-mfd"; > > +???????????????reg = <0x1e6e2000 0x1a8>; > > + > > +???????????????pinctrl: pinctrl { > > +???????????????????????compatible = "aspeed,g5-pinctrl"; > > +???????????????????????aspeed,external-nodes = <&gfx, &lpchc>; > > + > > +???????????????????????pinctrl_i2c3_default: i2c3_default { > > +???????????????????????????????function = "I2C3"; > > +???????????????????????????????groups = "I2C3"; > > +???????????????????????}; > > +???????????????}; > > +???????}; > > +}; > > + > > ?Please refer to pinctrl-bindings.txt in this directory for details of the > > ?common pinctrl bindings used by client devices. > > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c > > index a21b071ff290..558bd102416c 100644 > > --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c > > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c > > @@ -292,7 +292,7 @@ SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7)); > > ?#define UART6_DESC?????SIG_DESC_SET(SCU90, 7) > > ?#define ROM16_DESC?????SIG_DESC_SET(SCU90, 6) > > ?#define FLASH_WIDE?????SIG_DESC_SET(HW_STRAP1, 4) > > -#define BOOT_SRC_NOR???{ HW_STRAP1, GENMASK(1, 0), 0, 0 } > > +#define BOOT_SRC_NOR???{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 } > > > > ?#define A8 56 > > ?SIG_EXPR_DECL(ROMD8, ROM16, ROM16_DESC); > > @@ -418,9 +418,9 @@ FUNC_GROUP_DECL(I2C8, G5, F3); > > ?#define U1 88 > > ?SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); > > > > -#define VPI18_DESC?????{ SCU90, GENMASK(5, 4), 1, 0 } > > -#define VPI24_DESC?????{ SCU90, GENMASK(5, 4), 2, 0 } > > -#define VPI30_DESC?????{ SCU90, GENMASK(5, 4), 3, 0 } > > +#define VPI18_DESC?????{ ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 } > > +#define VPI24_DESC?????{ ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 } > > +#define VPI30_DESC?????{ ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 } > > > > ?#define T5 89 > > ?#define T5_DESC?????????SIG_DESC_SET(SCU84, 17) > > @@ -641,11 +641,11 @@ SSSF_PIN_DECL(Y22, GPIOR2, ROMCS3, SIG_DESC_SET(SCU88, 26)); > > ?#define U19 139 > > ?SSSF_PIN_DECL(U19, GPIOR3, ROMCS4, SIG_DESC_SET(SCU88, 27)); > > > > -#define VPOOFF0_DESC???{ SCU94, GENMASK(1, 0), 0, 0 } > > -#define VPO12_DESC?????{ SCU94, GENMASK(1, 0), 1, 0 } > > -#define VPO24_DESC?????{ SCU94, GENMASK(1, 0), 2, 0 } > > -#define VPOOFF1_DESC???{ SCU94, GENMASK(1, 0), 3, 0 } > > -#define VPO_OFF_12??????{ SCU94, 0x2, 0, 0 } > > +#define VPOOFF0_DESC???{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } > > +#define VPO12_DESC?????{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 } > > +#define VPO24_DESC?????{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 } > > +#define VPOOFF1_DESC???{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 } > > +#define VPO_OFF_12??????{ ASPEED_IP_SCU, SCU94, 0x2, 0, 0 } > > ?#define VPO_24_OFF??????SIG_DESC_SET(SCU94, 1) > > > > ?#define V21 140 > > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c > > index 87b46390b695..99c4fa9bf861 100644 > > --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c > > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c > > @@ -10,6 +10,7 @@ > > ?#include > > ?#include > > ?#include > > +#include > > ?#include > > ?#include > > ?#include > > @@ -26,8 +27,8 @@ > > > > ?#define ASPEED_G5_NR_PINS 228 > > > > -#define COND1??????????{ SCU90, BIT(6), 0, 0 } > > -#define COND2??????????{ SCU94, GENMASK(1, 0), 0, 0 } > > +#define COND1??????????{ ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 } > > +#define COND2??????????{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } > > > > ?#define B14 0 > > ?SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); > > @@ -186,9 +187,12 @@ MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT); > > > > ?FUNC_GROUP_DECL(GPIE0, B20, C20); > > > > -#define SPI1_DESC??????????????{ HW_STRAP1, GENMASK(13, 12), 1, 0 } > > -#define SPI1DEBUG_DESC?????????{ HW_STRAP1, GENMASK(13, 12), 2, 0 } > > -#define SPI1PASSTHRU_DESC??????{ HW_STRAP1, GENMASK(13, 12), 3, 0 } > > +#define SPI1_DESC \ > > +???????{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 } > > +#define SPI1DEBUG_DESC \ > > +???????{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 } > > +#define SPI1PASSTHRU_DESC \ > > +???????{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 } > > > > ?#define C18 64 > > ?SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC); > > @@ -325,10 +329,11 @@ SS_PIN_DECL(R1, GPIOK7, SDA8); > > > > ?FUNC_GROUP_DECL(I2C8, P2, R1); > > > > -#define VPIOFF0_DESC????{ SCU90, GENMASK(5, 4), 0, 0 } > > -#define VPIOFF1_DESC????{ SCU90, GENMASK(5, 4), 1, 0 } > > -#define VPI24_DESC??????{ SCU90, GENMASK(5, 4), 2, 0 } > > -#define VPIRSVD_DESC????{ SCU90, GENMASK(5, 4), 3, 0 } > > +#define VPIOFF0_DESC????{ ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 } > > +#define VPIOFF1_DESC????{ ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 } > > +#define VPI24_DESC??????{ ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 } > > +#define VPIRSVD_DESC????{ ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 } > > + > > > > ?#define V2 104 > > ?#define V2_DESC?????????SIG_DESC_SET(SCU88, 0) > > @@ -848,10 +853,26 @@ static struct pinctrl_desc aspeed_g5_pinctrl_desc = { > > ?static int aspeed_g5_pinctrl_probe(struct platform_device *pdev) > > ?{ > > ????????int i; > > +???????struct regmap **map; > > +???????struct device_node *node; > > > > ????????for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++) > > ????????????????aspeed_g5_pins[i].number = i; > > > > +???????map = &aspeed_g5_pinctrl_data.maps[ASPEED_IP_GFX]; > > +???????node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 0); > > +???????*map = syscon_node_to_regmap(node); > I think you can use syscon_regmap_lookup_by_phandle to replace both of > these lines. Good call, will do. > > > > > +???????of_node_put(node); > > +???????if (IS_ERR(*map)) > > +???????????????return PTR_ERR(*map); > Do we want to fail, or warn and continue? We would need to add further checks to defend against null dereferences if we were to continue. I think the broken devicetree should be fixed. > > The sequence is a bit messy. How about: > > struct regmap *map; > > map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, > "aspeed,external-nodes"); > if (IS_ERR(map)) > ???return PTR_ERR(map); > > aspeed_g5_pinctrl_data.maps[ASPEED_IP_GFX] = map; That looks neater, I will switch. > > > > > > + > > +???????map = &aspeed_g5_pinctrl_data.maps[ASPEED_IP_LPCHC]; > > +???????node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 1); > > +???????*map = syscon_node_to_regmap(node); > > +???????of_node_put(node); > > +???????if (IS_ERR(*map)) > > +???????????????return PTR_ERR(*map); > > + > Same comments as above. Ack. > > > > > ????????return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc, > > ????????????????????????&aspeed_g5_pinctrl_data); > > ?} > > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c > > index 49aeba912531..23586aac7a5a 100644 > > --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c > > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c > > @@ -14,6 +14,12 @@ > > ?#include "../core.h" > > ?#include "pinctrl-aspeed.h" > > > > +static const char *const aspeed_pinmux_ips[] = { > > +???????[ASPEED_IP_SCU] = "SCU", > > +???????[ASPEED_IP_GFX] = "GFX", > > +???????[ASPEED_IP_LPCHC] = "LHCR", > We've got both LPCHC and LHCR here. As I said when commenting on the > regmap bindings, I like LHC(R) better. > > > > > +}; > > + > > ?int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) > > ?{ > > ????????struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); > > @@ -78,7 +84,8 @@ int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev, > > ?static inline void aspeed_sig_desc_print_val( > > ????????????????const struct aspeed_sig_desc *desc, bool enable, u32 rv) > What's a rv? Perhaps "reg" or "value"? > > > > > ?{ > > -???????pr_debug("SCU%x[0x%08x]=0x%x, got 0x%x from 0x%08x\n", desc->reg, > > +???????pr_debug("Want %s%X[0x%08X]=0x%X, got 0x%X from 0x%08X\n", > > +???????????????????????aspeed_pinmux_ips[desc->ip], desc->reg, > > ????????????????????????desc->mask, enable ? desc->enable : desc->disable, > > ????????????????????????(rv & desc->mask) >> __ffs(desc->mask), rv); > > ?} > > @@ -88,7 +95,7 @@ static inline void aspeed_sig_desc_print_val( > > ? * > > ? * @desc: The signal descriptor of interest > > ? * @enabled: True to query the enabled state, false to query disabled state > > - * @regmap: The SCU regmap instance > > + * @regmap: The IP block's regmap instance > > ? * > > ? * @return True if the descriptor's bitfield is configured to the state > > ? * selected by @enabled, false otherwise > > @@ -119,7 +126,7 @@ static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, > > ? * > > ? * @expr: An expression controlling the signal for a mux function on a pin > > ? * @enabled: True to query the enabled state, false to query disabled state > > - * @regmap: The SCU regmap instance > > + * @maps: The list of regmap instances > > ? * > > ? * @return True if the expression composed by @enabled evaluates true, false > > ? * otherwise > > @@ -136,15 +143,16 @@ static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, > > ? * either condition as required. > > ? */ > > ?static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr, > > -????????????????????????????????bool enabled, struct regmap *map) > > +????????????????????????????????bool enabled, struct regmap * const *maps) > > ?{ > > ????????int i; > > > > ????????for (i = 0; i < expr->ndescs; i++) { > > ????????????????const struct aspeed_sig_desc *desc = &expr->descs[i]; > > > > -???????????????if (!aspeed_sig_desc_eval(desc, enabled, map)) > > +???????????????if (!aspeed_sig_desc_eval(desc, enabled, maps[desc->ip])) > > ????????????????????????return false; > > + > > ????????} > > > > ????????return true; > > @@ -158,12 +166,12 @@ static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr, > > ? *????????configured > > ? * @enable: true to enable an function's signal through a pin's signal > > ? *??????????expression, false to disable the function's signal > > - * @map: The SCU's regmap instance for pinmux register access. > > + * @maps: The list of regmap instances for pinmux register access. > > ? * > > ? * @return true if the expression is configured as requested, false otherwise > > ? */ > > ?static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, > > -???????????????????????????????bool enable, struct regmap *map) > > +???????????????????????????????bool enable, struct regmap * const *maps) > > ?{ > > ????????int i; > > > > @@ -171,6 +179,7 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, > > ????????????????bool ret; > > ????????????????const struct aspeed_sig_desc *desc = &expr->descs[i]; > > ????????????????u32 pattern = enable ? desc->enable : desc->disable; > > +???????????????u32 val = (pattern << __ffs(desc->mask)); > > > > ????????????????/* > > ?????????????????* Strap registers are configured in hardware or by early-boot > > @@ -179,48 +188,49 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, > > ?????????????????* deconfigured and is the reason we re-evaluate after writing > > ?????????????????* all descriptor bits. > > ?????????????????*/ > > -???????????????if (desc->reg == HW_STRAP1 || desc->reg == HW_STRAP2) > > +???????????????if ((desc->reg == HW_STRAP1 || desc->reg == HW_STRAP2) && > > +???????????????????????????????desc->ip == ASPEED_IP_SCU) > > ????????????????????????continue; > > > > -???????????????ret = regmap_update_bits(map, desc->reg, desc->mask, > > -???????????????????????????????pattern << __ffs(desc->mask)) == 0; > > +???????????????ret = regmap_update_bits(maps[desc->ip], desc->reg, > > +????????????????????????????????????????desc->mask, val) == 0; > > > > ????????????????if (!ret) > > ????????????????????????return ret; > > ????????} > > > > -???????return aspeed_sig_expr_eval(expr, enable, map); > > +???????return aspeed_sig_expr_eval(expr, enable, maps); > > ?} > > > > ?static bool aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr, > > -??????????????????????????????????struct regmap *map) > > +??????????????????????????????????struct regmap * const *maps) > > ?{ > > -???????if (aspeed_sig_expr_eval(expr, true, map)) > > +???????if (aspeed_sig_expr_eval(expr, true, maps)) > > ????????????????return true; > > > > -???????return aspeed_sig_expr_set(expr, true, map); > > +???????return aspeed_sig_expr_set(expr, true, maps); > > ?} > > > > ?static bool aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr, > > -???????????????????????????????????struct regmap *map) > > +???????????????????????????????????struct regmap * const *maps) > > ?{ > > -???????if (!aspeed_sig_expr_eval(expr, true, map)) > > +???????if (!aspeed_sig_expr_eval(expr, true, maps)) > > ????????????????return true; > > > > -???????return aspeed_sig_expr_set(expr, false, map); > > +???????return aspeed_sig_expr_set(expr, false, maps); > > ?} > > > > ?/** > > ? * Disable a signal on a pin by disabling all provided signal expressions. > > ? * > > ? * @exprs: The list of signal expressions (from a priority level on a pin) > > - * @map: The SCU's regmap instance for pinmux register access. > > + * @maps: The list of regmap instances for pinmux register access. > > ? * > > ? * @return true if all expressions in the list are successfully disabled, false > > ? * otherwise > > ? */ > > ?static bool aspeed_disable_sig(const struct aspeed_sig_expr **exprs, > > -??????????????????????????????struct regmap *map) > > +??????????????????????????????struct regmap * const *maps) > > ?{ > > ????????bool disabled = true; > > > > @@ -230,7 +240,7 @@ static bool aspeed_disable_sig(const struct aspeed_sig_expr **exprs, > > ????????while (*exprs) { > > ????????????????bool ret; > > > > -???????????????ret = aspeed_sig_expr_disable(*exprs, map); > > +???????????????ret = aspeed_sig_expr_disable(*exprs, maps); > > ????????????????disabled = disabled && ret; > > > > ????????????????exprs++; > > @@ -343,6 +353,8 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, > > ????????????????const struct aspeed_sig_expr **funcs; > > ????????????????const struct aspeed_sig_expr ***prios; > > > > +???????????????pr_debug("Muxing pin %d for %s\n", pin, pfunc->name); > > + > > ????????????????if (!pdesc) > > ????????????????????????return -EINVAL; > > > > @@ -358,7 +370,7 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, > > ????????????????????????if (expr) > > ????????????????????????????????break; > > > > -???????????????????????if (!aspeed_disable_sig(funcs, pdata->map)) > > +???????????????????????if (!aspeed_disable_sig(funcs, pdata->maps)) > > ????????????????????????????????return -EPERM; > > > > ????????????????????????prios++; > > @@ -377,7 +389,7 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, > > ????????????????????????return -ENXIO; > > ????????????????} > > > > -???????????????if (!aspeed_sig_expr_enable(expr, pdata->map)) > > +???????????????if (!aspeed_sig_expr_enable(expr, pdata->maps)) > > ????????????????????????return -EPERM; > > ????????} > > > > @@ -432,7 +444,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, > > ????????????????if (aspeed_gpio_in_exprs(funcs)) > > ????????????????????????break; > > > > -???????????????if (!aspeed_disable_sig(funcs, pdata->map)) > > +???????????????if (!aspeed_disable_sig(funcs, pdata->maps)) > > ????????????????????????return -EPERM; > > > > ????????????????prios++; > > @@ -462,7 +474,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, > > ?????????* If GPIO is not the lowest priority signal type, assume there is only > > ?????????* one expression defined to enable the GPIO function > > ?????????*/ > > -???????if (!aspeed_sig_expr_enable(expr, pdata->map)) > > +???????if (!aspeed_sig_expr_enable(expr, pdata->maps)) > > ????????????????return -EPERM; > > > > ????????return 0; > > @@ -481,10 +493,10 @@ int aspeed_pinctrl_probe(struct platform_device *pdev, > > ????????????????return -ENODEV; > > ????????} > > > > -???????pdata->map = syscon_node_to_regmap(parent->of_node); > > -???????if (IS_ERR(pdata->map)) { > > +???????pdata->maps[ASPEED_IP_SCU] = syscon_node_to_regmap(parent->of_node); > > +???????if (IS_ERR(pdata->maps[ASPEED_IP_SCU])) { > > ????????????????dev_err(&pdev->dev, "No regmap for syscon pincontroller parent\n"); > > -???????????????return PTR_ERR(pdata->map); > > +???????????????return PTR_ERR(pdata->maps[ASPEED_IP_SCU]); > > ????????} > > > > ????????pctl = pinctrl_register(pdesc, &pdev->dev, pdata); > > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h > > index 3e72ef8c54bf..727728b86c07 100644 > > --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h > > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h > > @@ -232,6 +232,11 @@ > > ? * group. > > ? */ > > > > +#define ASPEED_IP_SCU??0 > > +#define ASPEED_IP_GFX??1 > > +#define ASPEED_IP_LPCHC????????2 > > +#define ASPEED_NR_PINMUX_IPS???3 > > + > > ?/* > > ? * The "Multi-function Pins Mapping and Control" table in the SoC datasheet > > ? * references registers by the device/offset mnemonic. The register macros > > @@ -261,7 +266,9 @@ > > ???* A signal descriptor, which describes the register, bits and the > > ???* enable/disable values that should be compared or written. > > ???* > > -??* @reg: The register offset from base in bytes > > +??* @ip: The IP block identifier, used as an index into the regmap array in > > +??*??????struct aspeed_pinctrl_data > > +??* @reg: The register offset with respect to the base address of the IP block > > ???* @mask: The mask to apply to the register. The lowest set bit of the mask is > > ???*????????used to derive the shift value. > > ???* @enable: The value that enables the function. Value should be in the LSBs, > > @@ -270,6 +277,7 @@ > > ???*???????????LSBs, not at the position of the mask. > > ???*/ > > ?struct aspeed_sig_desc { > > +???????unsigned int ip; > > ????????unsigned int reg; > > ????????u32 mask; > > ????????u32 enable; > > @@ -313,24 +321,30 @@ struct aspeed_pin_desc { > > > > ?/* Macro hell */ > > > > +#define SIG_DESC_IP_BIT(ip, reg, idx, val) \ > > +???????{ ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) } > > + > > ?/** > > - * Short-hand macro for describing a configuration enabled by the state of one > > - * bit. The disable value is derived. > > + * Short-hand macro for describing an SCU descriptor enabled by the state of > > + * one bit. The disable value is derived. > > ? * > > ? * @reg: The signal's associated register, offset from base > > ? * @idx: The signal's bit index in the register > > ? * @val: The value (0 or 1) that enables the function > > ? */ > > ?#define SIG_DESC_BIT(reg, idx, val) \ > > -???????{ reg, BIT_MASK(idx), val, (((val) + 1) & 1) } > > +???????SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val) > > + > > +#define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1) > > > > ?/** > > - * A further short-hand macro describing a configuration enabled with a set bit. > > + * A further short-hand macro expanding to an SCU descriptor enabled by a set > > + * bit. > > ? * > > - * @reg: The configuration's associated register, offset from base > > - * @idx: The configuration's bit index in the register > > + * @reg: The register, offset from base > > + * @idx: The bit index in the register > > ? */ > > -#define SIG_DESC_SET(reg, idx) SIG_DESC_BIT(reg, idx, 1) > > +#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1) > > > > ?#define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func > > ?#define SIG_DESC_LIST_DECL(sig, func, ...) \ > > @@ -500,7 +514,7 @@ struct aspeed_pin_desc { > > ????????MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio)) > > > > ?struct aspeed_pinctrl_data { > > -???????struct regmap *map; > > +???????struct regmap *maps[ASPEED_NR_PINMUX_IPS]; > > > > ????????const struct pinctrl_pin_desc *pins; > > ????????const unsigned int npins; > > -- > > 2.7.4 > > -------------- next part -------------- A non-text attachment was scrubbed... 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