From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57867) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c5GHj-0006q5-Ob for qemu-devel@nongnu.org; Fri, 11 Nov 2016 13:10:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c5GHi-0003dU-Pp for qemu-devel@nongnu.org; Fri, 11 Nov 2016 13:10:43 -0500 Received: from mail.kernel.org ([198.145.29.136]:52242) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c5GHi-0003d6-KC for qemu-devel@nongnu.org; Fri, 11 Nov 2016 13:10:42 -0500 Date: Fri, 11 Nov 2016 20:10:38 +0200 From: "Michael S. Tsirkin" Message-ID: <1478887767-31980-12-git-send-email-mst@redhat.com> References: <1478887767-31980-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1478887767-31980-1-git-send-email-mst@redhat.com> Subject: [Qemu-devel] [PULL v2 11/34] intel_iommu: fix several incorrect endianess and bit fields List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Peter Xu , Paolo Bonzini , Richard Henderson , Eduardo Habkost From: Peter Xu Signed-off-by: Peter Xu Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/i386/intel_iommu.h | 9 ++++----- hw/i386/intel_iommu.c | 2 +- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 1989c1e..405c9d1 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -123,7 +123,6 @@ enum { union VTD_IR_TableEntry { struct { #ifdef HOST_WORDS_BIGENDIAN - uint32_t dest_id:32; /* Destination ID */ uint32_t __reserved_1:8; /* Reserved 1 */ uint32_t vector:8; /* Interrupt Vector */ uint32_t irte_mode:1; /* IRTE Mode */ @@ -147,9 +146,9 @@ union VTD_IR_TableEntry { uint32_t irte_mode:1; /* IRTE Mode */ uint32_t vector:8; /* Interrupt Vector */ uint32_t __reserved_1:8; /* Reserved 1 */ - uint32_t dest_id:32; /* Destination ID */ #endif - uint16_t source_id:16; /* Source-ID */ + uint32_t dest_id; /* Destination ID */ + uint16_t source_id; /* Source-ID */ #ifdef HOST_WORDS_BIGENDIAN uint64_t __reserved_2:44; /* Reserved 2 */ uint64_t sid_vtype:2; /* Source-ID Validation Type */ @@ -220,7 +219,7 @@ struct VTD_MSIMessage { uint32_t dest:8; uint32_t __addr_head:12; /* 0xfee */ #endif - uint32_t __addr_hi:32; + uint32_t __addr_hi; } QEMU_PACKED; uint64_t msi_addr; }; @@ -239,7 +238,7 @@ struct VTD_MSIMessage { uint16_t level:1; uint16_t trigger_mode:1; #endif - uint16_t __resved1:16; + uint16_t __resved1; } QEMU_PACKED; uint32_t msi_data; }; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 5a12ae7..20c4d2c 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2180,7 +2180,7 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu, } addr.data = origin->address & VTD_MSI_ADDR_LO_MASK; - if (le16_to_cpu(addr.addr.__head) != 0xfee) { + if (addr.addr.__head != 0xfee) { VTD_DPRINTF(GENERAL, "error: MSI addr low 32 bits invalid: " "0x%"PRIx32, addr.data); return -VTD_FR_IR_REQ_RSVD; -- MST