From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: Re: [PATCH] drm/i915/gen9: fix the WM memory bandwidth WA for Y tiling cases Date: Mon, 14 Nov 2016 18:03:58 -0200 Message-ID: <1479153838.2400.12.camel@intel.com> References: <1478636531-6081-1-git-send-email-paulo.r.zanoni@intel.com> <20161109013809.GG6536@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9BCBA6E505 for ; Mon, 14 Nov 2016 20:04:01 +0000 (UTC) In-Reply-To: <20161109013809.GG6536@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Matt Roper Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org RW0gVGVyLCAyMDE2LTExLTA4IMOgcyAxNzozOCAtMDgwMCwgTWF0dCBSb3BlciBlc2NyZXZldToK PiBPbiBUdWUsIE5vdiAwOCwgMjAxNiBhdCAwNjoyMjoxMVBNIC0wMjAwLCBQYXVsbyBaYW5vbmkg d3JvdGU6Cj4gPiAKPiA+IFRoZSBwcmV2aW91cyBzcGVjIHZlcnNpb24gc2FpZCAiZG91YmxlIFl0 aWxlIHBsYW5lcyBtaW5pbXVtIGxpbmVzIiwKPiA+IGFuZCBJIGludGVycHJldGVkIHRoaXMgYXMg cmVmZXJyaW5nIHRvIHdoYXQgdGhlIHNwZWMgY2FsbHMgIlkgdGlsZQo+ID4gbWluaW11bSIsIGJ1 dCBpbiBmYWN0IGl0IHdhcyByZWZlcnJpbmcgdG8gd2hhdCB0aGUgc3BlYyBjYWxscwo+ID4gIk1p bmltdW0KPiA+IFNjYW5saW5lcyBmb3IgWSB0aWxlIi4gSSBub3RpY2VkIHRoYXQgTWFoZXNoIEt1 bWFyIGhhZCBhIGRpZmZlcmVudAo+ID4gaW50ZXJwcmV0YXRpb24sIHNvIEkgc2VudCBhbmQgZW1h aWwgdG8gdGhlIHNwZWMgYXV0aG9ycyBhbmQgZ290Cj4gPiBjbGFyaWZpY2F0aW9uIG9uIHRoZSBj b3JyZWN0IG1lYW5pbmcuIEFsc28sIEJTcGVjIHdhcyB1cGRhdGVkIGFuZAo+ID4gc2hvdWxkIGJl IGNsZWFyIG5vdy4KPiA+IAo+ID4gRml4ZXM6IGVlM2Q1MzJmY2I2NCAoImRybS9pOTE1L2dlbjk6 IHVuY29uZGl0aW9uYWxseSBhcHBseSB0aGUKPiA+IG1lbW9yeSBiYW5kd2lkdGggV0EiKQo+ID4g Q2M6IHN0YWJsZUB2Z2VyLmtlcm5lbC5vcmcKPiA+IENjOiBNYWhlc2ggS3VtYXIgPG1haGVzaDEu a3VtYXJAaW50ZWwuY29tPgo+ID4gU2lnbmVkLW9mZi1ieTogUGF1bG8gWmFub25pIDxwYXVsby5y Lnphbm9uaUBpbnRlbC5jb20+Cj4gCj4gVGhpcyBzZWVtcyB0byBtYXRjaCBteSByZWFkaW5nIG9m IHRoZSBzcGVjIHVwZGF0ZSBmcm9tIE5vdiA0dGgsIHNvOgo+IAo+IFJldmlld2VkLWJ5OiBNYXR0 IFJvcGVyIDxtYXR0aGV3LmQucm9wZXJAaW50ZWwuY29tPgoKUGF0Y2ggbWVyZ2VkIHRvZGF5LiBU aGFua3MgZm9yIHRoZSByZXZpZXchCgo+IAo+IAo+ID4gCj4gPiAtLS0KPiA+IMKgZHJpdmVycy9n cHUvZHJtL2k5MTUvaW50ZWxfcG0uYyB8IDUgKysrLS0KPiA+IMKgMSBmaWxlIGNoYW5nZWQsIDMg aW5zZXJ0aW9ucygrKSwgMiBkZWxldGlvbnMoLSkKPiA+IAo+ID4gZGlmZiAtLWdpdCBhL2RyaXZl cnMvZ3B1L2RybS9pOTE1L2ludGVsX3BtLmMKPiA+IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50 ZWxfcG0uYwo+ID4gaW5kZXggY2M5ZTBjMC4uNjUzNTI1ZiAxMDA2NDQKPiA+IC0tLSBhL2RyaXZl cnMvZ3B1L2RybS9pOTE1L2ludGVsX3BtLmMKPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1 L2ludGVsX3BtLmMKPiA+IEBAIC0zNjI0LDYgKzM2MjQsOSBAQCBzdGF0aWMgaW50IHNrbF9jb21w dXRlX3BsYW5lX3dtKGNvbnN0IHN0cnVjdAo+ID4gZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYs Cj4gPiDCoAkJeV9taW5fc2NhbmxpbmVzID0gNDsKPiA+IMKgCX0KPiA+IMKgCj4gPiArCWlmIChh cHBseV9tZW1vcnlfYndfd2EpCj4gPiArCQl5X21pbl9zY2FubGluZXMgKj0gMjsKPiA+ICsKPiA+ IMKgCXBsYW5lX2J5dGVzX3Blcl9saW5lID0gd2lkdGggKiBjcHA7Cj4gPiDCoAlpZiAoZmItPm1v ZGlmaWVyWzBdID09IEk5MTVfRk9STUFUX01PRF9ZX1RJTEVEIHx8Cj4gPiDCoAnCoMKgwqDCoGZi LT5tb2RpZmllclswXSA9PSBJOTE1X0ZPUk1BVF9NT0RfWWZfVElMRUQpIHsKPiA+IEBAIC0zNjQ0 LDggKzM2NDcsNiBAQCBzdGF0aWMgaW50IHNrbF9jb21wdXRlX3BsYW5lX3dtKGNvbnN0IHN0cnVj dAo+ID4gZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYsCj4gPiDCoAkJCQnCoHBsYW5lX2Jsb2Nr c19wZXJfbGluZSk7Cj4gPiDCoAo+ID4gwqAJeV90aWxlX21pbmltdW0gPSBwbGFuZV9ibG9ja3Nf cGVyX2xpbmUgKiB5X21pbl9zY2FubGluZXM7Cj4gPiAtCWlmIChhcHBseV9tZW1vcnlfYndfd2Ep Cj4gPiAtCQl5X3RpbGVfbWluaW11bSAqPSAyOwo+ID4gwqAKPiA+IMKgCWlmIChmYi0+bW9kaWZp ZXJbMF0gPT0gSTkxNV9GT1JNQVRfTU9EX1lfVElMRUQgfHwKPiA+IMKgCcKgwqDCoMKgZmItPm1v ZGlmaWVyWzBdID09IEk5MTVfRk9STUFUX01PRF9ZZl9USUxFRCkgewo+ID4gLS3CoAo+ID4gMi43 LjQKPiA+IAo+ID4gX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KPiA+IEludGVsLWdmeCBtYWlsaW5nIGxpc3QKPiA+IEludGVsLWdmeEBsaXN0cy5mcmVlZGVz a3RvcC5vcmcKPiA+IGh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGlu Zm8vaW50ZWwtZ2Z4Cj4gCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fCkludGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9w Lm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVs LWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com ([192.55.52.88]:1077 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935195AbcKNUEC (ORCPT ); Mon, 14 Nov 2016 15:04:02 -0500 Message-ID: <1479153838.2400.12.camel@intel.com> Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9: fix the WM memory bandwidth WA for Y tiling cases From: Paulo Zanoni To: Matt Roper Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org Date: Mon, 14 Nov 2016 18:03:58 -0200 In-Reply-To: <20161109013809.GG6536@intel.com> References: <1478636531-6081-1-git-send-email-paulo.r.zanoni@intel.com> <20161109013809.GG6536@intel.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: Em Ter, 2016-11-08 às 17:38 -0800, Matt Roper escreveu: > On Tue, Nov 08, 2016 at 06:22:11PM -0200, Paulo Zanoni wrote: > > > > The previous spec version said "double Ytile planes minimum lines", > > and I interpreted this as referring to what the spec calls "Y tile > > minimum", but in fact it was referring to what the spec calls > > "Minimum > > Scanlines for Y tile". I noticed that Mahesh Kumar had a different > > interpretation, so I sent and email to the spec authors and got > > clarification on the correct meaning. Also, BSpec was updated and > > should be clear now. > > > > Fixes: ee3d532fcb64 ("drm/i915/gen9: unconditionally apply the > > memory bandwidth WA") > > Cc: stable@vger.kernel.org > > Cc: Mahesh Kumar > > Signed-off-by: Paulo Zanoni > > This seems to match my reading of the spec update from Nov 4th, so: > > Reviewed-by: Matt Roper Patch merged today. Thanks for the review! > > > > > > --- > >  drivers/gpu/drm/i915/intel_pm.c | 5 +++-- > >  1 file changed, 3 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > b/drivers/gpu/drm/i915/intel_pm.c > > index cc9e0c0..653525f 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3624,6 +3624,9 @@ static int skl_compute_plane_wm(const struct > > drm_i915_private *dev_priv, > >   y_min_scanlines = 4; > >   } > >   > > + if (apply_memory_bw_wa) > > + y_min_scanlines *= 2; > > + > >   plane_bytes_per_line = width * cpp; > >   if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || > >       fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) { > > @@ -3644,8 +3647,6 @@ static int skl_compute_plane_wm(const struct > > drm_i915_private *dev_priv, > >    plane_blocks_per_line); > >   > >   y_tile_minimum = plane_blocks_per_line * y_min_scanlines; > > - if (apply_memory_bw_wa) > > - y_tile_minimum *= 2; > >   > >   if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || > >       fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) { > > --  > > 2.7.4 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx >