diff for duplicates of <1479309234.24056.47.camel@linux.intel.com>

diff --git a/a/1.txt b/N1/1.txt
index 6c5f2bc..98e5ca9 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,4 +1,4 @@
-On Wed, 2016-11-16@16:56 +0300, Eugeniy Paltsev wrote:
+On Wed, 2016-11-16 at 16:56 +0300, Eugeniy Paltsev wrote:
 > Several versions of DW DMAC have multi block transfers hardware
 > support. Hardware support of multi block transfers is disabled
 > by default if we use DT to configure DMAC and software emulation
@@ -10,87 +10,92 @@ You forgot to explain the conversion from per device value to per
 channel one.
 
 > 
-> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>
+> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 > ---
-> ?drivers/dma/dw/core.c????????????????| 2 +-
-> ?drivers/dma/dw/platform.c????????????| 5 +++++
-> ?include/linux/platform_data/dma-dw.h | 4 ++--
-> ?3 files changed, 8 insertions(+), 3 deletions(-)
+>  drivers/dma/dw/core.c                | 2 +-
+>  drivers/dma/dw/platform.c            | 5 +++++
+>  include/linux/platform_data/dma-dw.h | 4 ++--
+>  3 files changed, 8 insertions(+), 3 deletions(-)
 > 
 > diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
 > index c2c0a61..e3ff4ea 100644
 > --- a/drivers/dma/dw/core.c
 > +++ b/drivers/dma/dw/core.c
 > @@ -1569,7 +1569,7 @@ int dw_dma_probe(struct dw_dma_chip *chip)
-> ?				(dwc_params >> DWC_PARAMS_MBLK_EN &
+>  				(dwc_params >> DWC_PARAMS_MBLK_EN &
 > 0x1) == 0;
-> ?		} else {
-> ?			dwc->block_size = pdata->block_size;
+>  		} else {
+>  			dwc->block_size = pdata->block_size;
 > -			dwc->nollp = pdata->is_nollp;
 > +			dwc->nollp = pdata->hw_llp[i];
-> ?		}
-> ?	}
-> ?
+>  		}
+>  	}
+>  
 > diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
 > index daeceac..2722e60 100644
 > --- a/drivers/dma/dw/platform.c
 > +++ b/drivers/dma/dw/platform.c
 > @@ -151,6 +151,11 @@ dw_dma_parse_dt(struct platform_device *pdev)
-> ?			pdata->data_width[tmp] = BIT(arr[tmp] &
+>  			pdata->data_width[tmp] = BIT(arr[tmp] &
 > 0x07);
-> ?	}
-> ?
+>  	}
+>  
 > +	if (!of_property_read_u32_array(np, "hw-llp", arr,
 > nr_masters)) {
 > +		for (tmp = 0; tmp < nr_masters; tmp++)
 > +			pdata->hw_llp[tmp] = arr[tmp];
 > +	}
 > +
-> ?	return pdata;
-> ?}
-> ?#else
+>  	return pdata;
+>  }
+>  #else
 > diff --git a/include/linux/platform_data/dma-dw.h
 > b/include/linux/platform_data/dma-dw.h
 > index 5f0e11e..5bc8124 100644
 > --- a/include/linux/platform_data/dma-dw.h
 > +++ b/include/linux/platform_data/dma-dw.h
 > @@ -40,19 +40,18 @@ struct dw_dma_slave {
-> ? * @is_private: The device channels should be marked as private and
+>   * @is_private: The device channels should be marked as private and
 > not for
-> ? *	by the general purpose DMA channel allocator.
-> ? * @is_memcpy: The device channels do support memory-to-memory
+>   *	by the general purpose DMA channel allocator.
+>   * @is_memcpy: The device channels do support memory-to-memory
 > transfers.
 > - * @is_nollp: The device channels does not support multi block
 > transfers.
-> ? * @chan_allocation_order: Allocate channels starting from 0 or 7
-> ? * @chan_priority: Set channel priority increasing from 0 to 7 or 7
+>   * @chan_allocation_order: Allocate channels starting from 0 or 7
+>   * @chan_priority: Set channel priority increasing from 0 to 7 or 7
 > to 0.
-> ? * @block_size: Maximum block size supported by the controller
-> ? * @nr_masters: Number of AHB masters supported by the controller
-> ? * @data_width: Maximum data width supported by hardware per AHB
+>   * @block_size: Maximum block size supported by the controller
+>   * @nr_masters: Number of AHB masters supported by the controller
+>   * @data_width: Maximum data width supported by hardware per AHB
 > master
-> ? *		(in bytes, power of 2)
+>   *		(in bytes, power of 2)
 > + * @hw_llp: Multi block transfers supported by hardware per AHB
 > master.
-> ? */
-> ?struct dw_dma_platform_data {
-> ?	unsigned int	nr_channels;
-> ?	bool		is_private;
-> ?	bool		is_memcpy;
+>   */
+>  struct dw_dma_platform_data {
+>  	unsigned int	nr_channels;
+>  	bool		is_private;
+>  	bool		is_memcpy;
 > -	bool		is_nollp;
-> ?#define CHAN_ALLOCATION_ASCENDING	0	/* zero to seven */
-> ?#define CHAN_ALLOCATION_DESCENDING	1	/* seven to zero
+>  #define CHAN_ALLOCATION_ASCENDING	0	/* zero to seven */
+>  #define CHAN_ALLOCATION_DESCENDING	1	/* seven to zero
 > */
-> ?	unsigned char	chan_allocation_order;
+>  	unsigned char	chan_allocation_order;
 > @@ -62,6 +61,7 @@ struct dw_dma_platform_data {
-> ?	unsigned int	block_size;
-> ?	unsigned char	nr_masters;
-> ?	unsigned char	data_width[DW_DMA_MAX_NR_MASTERS];
+>  	unsigned int	block_size;
+>  	unsigned char	nr_masters;
+>  	unsigned char	data_width[DW_DMA_MAX_NR_MASTERS];
 > +	unsigned char	hw_llp[DW_DMA_MAX_NR_MASTERS];
-> ?};
-> ?
-> ?#endif /* _PLATFORM_DATA_DMA_DW_H */
+>  };
+>  
+>  #endif /* _PLATFORM_DATA_DMA_DW_H */
 
 -- 
-Andy Shevchenko <andriy.shevchenko at linux.intel.com>
+Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 Intel Finland Oy
+
+_______________________________________________
+linux-snps-arc mailing list
+linux-snps-arc@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-snps-arc
diff --git a/a/content_digest b/N1/content_digest
index 1fddcd0..f7108e2 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,12 +1,21 @@
  "ref\01479304615-11360-1-git-send-email-Eugeniy.Paltsev@synopsys.com\0"
  "ref\01479304615-11360-4-git-send-email-Eugeniy.Paltsev@synopsys.com\0"
- "From\0andriy.shevchenko@linux.intel.com (Andy Shevchenko)\0"
- "Subject\0[PATCH 3/4] DW DMAC: add hw-llp property to device tree\0"
+ "From\0Andy Shevchenko <andriy.shevchenko@linux.intel.com>\0"
+ "Subject\0Re: [PATCH 3/4] DW DMAC: add hw-llp property to device tree\0"
  "Date\0Wed, 16 Nov 2016 17:13:54 +0200\0"
- "To\0linux-snps-arc@lists.infradead.org\0"
+ "To\0Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>"
+ " devicetree@vger.kernel.org\0"
+ "Cc\0mark.rutland@arm.com"
+  vinod.koul@intel.com
+  vireshk@kernel.org
+  linux-kernel@vger.kernel.org
+  robh+dt@kernel.org
+  dmaengine@vger.kernel.org
+  dan.j.williams@intel.com
+ " linux-snps-arc@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
- "On Wed, 2016-11-16@16:56 +0300, Eugeniy Paltsev wrote:\n"
+ "On Wed, 2016-11-16 at 16:56 +0300, Eugeniy Paltsev wrote:\n"
  "> Several versions of DW DMAC have multi block transfers hardware\n"
  "> support. Hardware support of multi block transfers is disabled\n"
  "> by default if we use DT to configure DMAC and software emulation\n"
@@ -18,89 +27,94 @@
  "channel one.\n"
  "\n"
  "> \n"
- "> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>\n"
+ "> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\n"
  "> ---\n"
- "> ?drivers/dma/dw/core.c????????????????| 2 +-\n"
- "> ?drivers/dma/dw/platform.c????????????| 5 +++++\n"
- "> ?include/linux/platform_data/dma-dw.h | 4 ++--\n"
- "> ?3 files changed, 8 insertions(+), 3 deletions(-)\n"
+ "> \302\240drivers/dma/dw/core.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 2 +-\n"
+ "> \302\240drivers/dma/dw/platform.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 5 +++++\n"
+ "> \302\240include/linux/platform_data/dma-dw.h | 4 ++--\n"
+ "> \302\2403 files changed, 8 insertions(+), 3 deletions(-)\n"
  "> \n"
  "> diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c\n"
  "> index c2c0a61..e3ff4ea 100644\n"
  "> --- a/drivers/dma/dw/core.c\n"
  "> +++ b/drivers/dma/dw/core.c\n"
  "> @@ -1569,7 +1569,7 @@ int dw_dma_probe(struct dw_dma_chip *chip)\n"
- "> ?\t\t\t\t(dwc_params >> DWC_PARAMS_MBLK_EN &\n"
+ "> \302\240\t\t\t\t(dwc_params >> DWC_PARAMS_MBLK_EN &\n"
  "> 0x1) == 0;\n"
- "> ?\t\t} else {\n"
- "> ?\t\t\tdwc->block_size = pdata->block_size;\n"
+ "> \302\240\t\t} else {\n"
+ "> \302\240\t\t\tdwc->block_size = pdata->block_size;\n"
  "> -\t\t\tdwc->nollp = pdata->is_nollp;\n"
  "> +\t\t\tdwc->nollp = pdata->hw_llp[i];\n"
- "> ?\t\t}\n"
- "> ?\t}\n"
- "> ?\n"
+ "> \302\240\t\t}\n"
+ "> \302\240\t}\n"
+ "> \302\240\n"
  "> diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c\n"
  "> index daeceac..2722e60 100644\n"
  "> --- a/drivers/dma/dw/platform.c\n"
  "> +++ b/drivers/dma/dw/platform.c\n"
  "> @@ -151,6 +151,11 @@ dw_dma_parse_dt(struct platform_device *pdev)\n"
- "> ?\t\t\tpdata->data_width[tmp] = BIT(arr[tmp] &\n"
+ "> \302\240\t\t\tpdata->data_width[tmp] = BIT(arr[tmp] &\n"
  "> 0x07);\n"
- "> ?\t}\n"
- "> ?\n"
+ "> \302\240\t}\n"
+ "> \302\240\n"
  "> +\tif (!of_property_read_u32_array(np, \"hw-llp\", arr,\n"
  "> nr_masters)) {\n"
  "> +\t\tfor (tmp = 0; tmp < nr_masters; tmp++)\n"
  "> +\t\t\tpdata->hw_llp[tmp] = arr[tmp];\n"
  "> +\t}\n"
  "> +\n"
- "> ?\treturn pdata;\n"
- "> ?}\n"
- "> ?#else\n"
+ "> \302\240\treturn pdata;\n"
+ "> \302\240}\n"
+ "> \302\240#else\n"
  "> diff --git a/include/linux/platform_data/dma-dw.h\n"
  "> b/include/linux/platform_data/dma-dw.h\n"
  "> index 5f0e11e..5bc8124 100644\n"
  "> --- a/include/linux/platform_data/dma-dw.h\n"
  "> +++ b/include/linux/platform_data/dma-dw.h\n"
  "> @@ -40,19 +40,18 @@ struct dw_dma_slave {\n"
- "> ? * @is_private: The device channels should be marked as private and\n"
+ "> \302\240 * @is_private: The device channels should be marked as private and\n"
  "> not for\n"
- "> ? *\tby the general purpose DMA channel allocator.\n"
- "> ? * @is_memcpy: The device channels do support memory-to-memory\n"
+ "> \302\240 *\tby the general purpose DMA channel allocator.\n"
+ "> \302\240 * @is_memcpy: The device channels do support memory-to-memory\n"
  "> transfers.\n"
  "> - * @is_nollp: The device channels does not support multi block\n"
  "> transfers.\n"
- "> ? * @chan_allocation_order: Allocate channels starting from 0 or 7\n"
- "> ? * @chan_priority: Set channel priority increasing from 0 to 7 or 7\n"
+ "> \302\240 * @chan_allocation_order: Allocate channels starting from 0 or 7\n"
+ "> \302\240 * @chan_priority: Set channel priority increasing from 0 to 7 or 7\n"
  "> to 0.\n"
- "> ? * @block_size: Maximum block size supported by the controller\n"
- "> ? * @nr_masters: Number of AHB masters supported by the controller\n"
- "> ? * @data_width: Maximum data width supported by hardware per AHB\n"
+ "> \302\240 * @block_size: Maximum block size supported by the controller\n"
+ "> \302\240 * @nr_masters: Number of AHB masters supported by the controller\n"
+ "> \302\240 * @data_width: Maximum data width supported by hardware per AHB\n"
  "> master\n"
- "> ? *\t\t(in bytes, power of 2)\n"
+ "> \302\240 *\t\t(in bytes, power of 2)\n"
  "> + * @hw_llp: Multi block transfers supported by hardware per AHB\n"
  "> master.\n"
- "> ? */\n"
- "> ?struct dw_dma_platform_data {\n"
- "> ?\tunsigned int\tnr_channels;\n"
- "> ?\tbool\t\tis_private;\n"
- "> ?\tbool\t\tis_memcpy;\n"
+ "> \302\240 */\n"
+ "> \302\240struct dw_dma_platform_data {\n"
+ "> \302\240\tunsigned int\tnr_channels;\n"
+ "> \302\240\tbool\t\tis_private;\n"
+ "> \302\240\tbool\t\tis_memcpy;\n"
  "> -\tbool\t\tis_nollp;\n"
- "> ?#define CHAN_ALLOCATION_ASCENDING\t0\t/* zero to seven */\n"
- "> ?#define CHAN_ALLOCATION_DESCENDING\t1\t/* seven to zero\n"
+ "> \302\240#define CHAN_ALLOCATION_ASCENDING\t0\t/* zero to seven */\n"
+ "> \302\240#define CHAN_ALLOCATION_DESCENDING\t1\t/* seven to zero\n"
  "> */\n"
- "> ?\tunsigned char\tchan_allocation_order;\n"
+ "> \302\240\tunsigned char\tchan_allocation_order;\n"
  "> @@ -62,6 +61,7 @@ struct dw_dma_platform_data {\n"
- "> ?\tunsigned int\tblock_size;\n"
- "> ?\tunsigned char\tnr_masters;\n"
- "> ?\tunsigned char\tdata_width[DW_DMA_MAX_NR_MASTERS];\n"
+ "> \302\240\tunsigned int\tblock_size;\n"
+ "> \302\240\tunsigned char\tnr_masters;\n"
+ "> \302\240\tunsigned char\tdata_width[DW_DMA_MAX_NR_MASTERS];\n"
  "> +\tunsigned char\thw_llp[DW_DMA_MAX_NR_MASTERS];\n"
- "> ?};\n"
- "> ?\n"
- "> ?#endif /* _PLATFORM_DATA_DMA_DW_H */\n"
+ "> \302\240};\n"
+ "> \302\240\n"
+ "> \302\240#endif /* _PLATFORM_DATA_DMA_DW_H */\n"
  "\n"
  "-- \n"
- "Andy Shevchenko <andriy.shevchenko at linux.intel.com>\n"
- Intel Finland Oy
+ "Andy Shevchenko <andriy.shevchenko@linux.intel.com>\n"
+ "Intel Finland Oy\n"
+ "\n"
+ "_______________________________________________\n"
+ "linux-snps-arc mailing list\n"
+ "linux-snps-arc@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-snps-arc
 
-12a7942802a28601440932dadea136940a7e319c6d038760f315d5db395000a5
+616d210c299e55fdc9a28ccc669ba3a4241c3d375685d1914b7a3c97cf979a9f
