From mboxrd@z Thu Jan 1 00:00:00 1970 From: andriy.shevchenko@linux.intel.com (Andy Shevchenko) Date: Wed, 16 Nov 2016 17:13:54 +0200 Subject: [PATCH 3/4] DW DMAC: add hw-llp property to device tree In-Reply-To: <1479304615-11360-4-git-send-email-Eugeniy.Paltsev@synopsys.com> References: <1479304615-11360-1-git-send-email-Eugeniy.Paltsev@synopsys.com> <1479304615-11360-4-git-send-email-Eugeniy.Paltsev@synopsys.com> List-ID: Message-ID: <1479309234.24056.47.camel@linux.intel.com> To: linux-snps-arc@lists.infradead.org On Wed, 2016-11-16@16:56 +0300, Eugeniy Paltsev wrote: > Several versions of DW DMAC have multi block transfers hardware > support. Hardware support of multi block transfers is disabled > by default if we use DT to configure DMAC and software emulation > of multi block transfers used instead. > Add hw-llp property, so it is possible to enable hardware > multi block transfers (if present) via DT. You forgot to explain the conversion from per device value to per channel one. > > Signed-off-by: Eugeniy Paltsev > --- > ?drivers/dma/dw/core.c????????????????| 2 +- > ?drivers/dma/dw/platform.c????????????| 5 +++++ > ?include/linux/platform_data/dma-dw.h | 4 ++-- > ?3 files changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c > index c2c0a61..e3ff4ea 100644 > --- a/drivers/dma/dw/core.c > +++ b/drivers/dma/dw/core.c > @@ -1569,7 +1569,7 @@ int dw_dma_probe(struct dw_dma_chip *chip) > ? (dwc_params >> DWC_PARAMS_MBLK_EN & > 0x1) == 0; > ? } else { > ? dwc->block_size = pdata->block_size; > - dwc->nollp = pdata->is_nollp; > + dwc->nollp = pdata->hw_llp[i]; > ? } > ? } > ? > diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c > index daeceac..2722e60 100644 > --- a/drivers/dma/dw/platform.c > +++ b/drivers/dma/dw/platform.c > @@ -151,6 +151,11 @@ dw_dma_parse_dt(struct platform_device *pdev) > ? pdata->data_width[tmp] = BIT(arr[tmp] & > 0x07); > ? } > ? > + if (!of_property_read_u32_array(np, "hw-llp", arr, > nr_masters)) { > + for (tmp = 0; tmp < nr_masters; tmp++) > + pdata->hw_llp[tmp] = arr[tmp]; > + } > + > ? return pdata; > ?} > ?#else > diff --git a/include/linux/platform_data/dma-dw.h > b/include/linux/platform_data/dma-dw.h > index 5f0e11e..5bc8124 100644 > --- a/include/linux/platform_data/dma-dw.h > +++ b/include/linux/platform_data/dma-dw.h > @@ -40,19 +40,18 @@ struct dw_dma_slave { > ? * @is_private: The device channels should be marked as private and > not for > ? * by the general purpose DMA channel allocator. > ? * @is_memcpy: The device channels do support memory-to-memory > transfers. > - * @is_nollp: The device channels does not support multi block > transfers. > ? * @chan_allocation_order: Allocate channels starting from 0 or 7 > ? * @chan_priority: Set channel priority increasing from 0 to 7 or 7 > to 0. > ? * @block_size: Maximum block size supported by the controller > ? * @nr_masters: Number of AHB masters supported by the controller > ? * @data_width: Maximum data width supported by hardware per AHB > master > ? * (in bytes, power of 2) > + * @hw_llp: Multi block transfers supported by hardware per AHB > master. > ? */ > ?struct dw_dma_platform_data { > ? unsigned int nr_channels; > ? bool is_private; > ? bool is_memcpy; > - bool is_nollp; > ?#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ > ?#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero > */ > ? unsigned char chan_allocation_order; > @@ -62,6 +61,7 @@ struct dw_dma_platform_data { > ? unsigned int block_size; > ? unsigned char nr_masters; > ? unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; > + unsigned char hw_llp[DW_DMA_MAX_NR_MASTERS]; > ?}; > ? > ?#endif /* _PLATFORM_DATA_DMA_DW_H */ -- Andy Shevchenko Intel Finland Oy From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Shevchenko Subject: Re: [PATCH 3/4] DW DMAC: add hw-llp property to device tree Date: Wed, 16 Nov 2016 17:13:54 +0200 Message-ID: <1479309234.24056.47.camel@linux.intel.com> References: <1479304615-11360-1-git-send-email-Eugeniy.Paltsev@synopsys.com> <1479304615-11360-4-git-send-email-Eugeniy.Paltsev@synopsys.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1479304615-11360-4-git-send-email-Eugeniy.Paltsev@synopsys.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+gla-linux-snps-arc=m.gmane.org@lists.infradead.org To: Eugeniy Paltsev , devicetree@vger.kernel.org Cc: mark.rutland@arm.com, vinod.koul@intel.com, vireshk@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, dmaengine@vger.kernel.org, dan.j.williams@intel.com, linux-snps-arc@lists.infradead.org List-Id: devicetree@vger.kernel.org T24gV2VkLCAyMDE2LTExLTE2IGF0IDE2OjU2ICswMzAwLCBFdWdlbml5IFBhbHRzZXYgd3JvdGU6 Cj4gU2V2ZXJhbCB2ZXJzaW9ucyBvZiBEVyBETUFDIGhhdmUgbXVsdGkgYmxvY2sgdHJhbnNmZXJz IGhhcmR3YXJlCj4gc3VwcG9ydC4gSGFyZHdhcmUgc3VwcG9ydCBvZiBtdWx0aSBibG9jayB0cmFu c2ZlcnMgaXMgZGlzYWJsZWQKPiBieSBkZWZhdWx0IGlmIHdlIHVzZSBEVCB0byBjb25maWd1cmUg RE1BQyBhbmQgc29mdHdhcmUgZW11bGF0aW9uCj4gb2YgbXVsdGkgYmxvY2sgdHJhbnNmZXJzIHVz ZWQgaW5zdGVhZC4KPiBBZGQgaHctbGxwIHByb3BlcnR5LCBzbyBpdCBpcyBwb3NzaWJsZSB0byBl bmFibGUgaGFyZHdhcmUKPiBtdWx0aSBibG9jayB0cmFuc2ZlcnMgKGlmIHByZXNlbnQpIHZpYSBE VC4KCllvdSBmb3Jnb3QgdG8gZXhwbGFpbiB0aGUgY29udmVyc2lvbiBmcm9tIHBlciBkZXZpY2Ug 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X19fX19fX19fX19fX19fX19fX18KbGludXgtc25wcy1hcmMgbWFpbGluZyBsaXN0CmxpbnV4LXNu cHMtYXJjQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFp bG1hbi9saXN0aW5mby9saW51eC1zbnBzLWFyYw== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933714AbcKPPOJ (ORCPT ); Wed, 16 Nov 2016 10:14:09 -0500 Received: from mga04.intel.com ([192.55.52.120]:32504 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753617AbcKPPOE (ORCPT ); Wed, 16 Nov 2016 10:14:04 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,500,1473145200"; d="scan'208";a="787175399" Message-ID: <1479309234.24056.47.camel@linux.intel.com> Subject: Re: [PATCH 3/4] DW DMAC: add hw-llp property to device tree From: Andy Shevchenko To: Eugeniy Paltsev , devicetree@vger.kernel.org Cc: robh+dt@kernel.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, vireshk@kernel.org, dan.j.williams@intel.com, vinod.koul@intel.com, dmaengine@vger.kernel.org, linux-snps-arc@lists.infradead.org Date: Wed, 16 Nov 2016 17:13:54 +0200 In-Reply-To: <1479304615-11360-4-git-send-email-Eugeniy.Paltsev@synopsys.com> References: <1479304615-11360-1-git-send-email-Eugeniy.Paltsev@synopsys.com> <1479304615-11360-4-git-send-email-Eugeniy.Paltsev@synopsys.com> Organization: Intel Finland Oy Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.2-1 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2016-11-16 at 16:56 +0300, Eugeniy Paltsev wrote: > Several versions of DW DMAC have multi block transfers hardware > support. Hardware support of multi block transfers is disabled > by default if we use DT to configure DMAC and software emulation > of multi block transfers used instead. > Add hw-llp property, so it is possible to enable hardware > multi block transfers (if present) via DT. You forgot to explain the conversion from per device value to per channel one. > > Signed-off-by: Eugeniy Paltsev > --- >  drivers/dma/dw/core.c                | 2 +- >  drivers/dma/dw/platform.c            | 5 +++++ >  include/linux/platform_data/dma-dw.h | 4 ++-- >  3 files changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c > index c2c0a61..e3ff4ea 100644 > --- a/drivers/dma/dw/core.c > +++ b/drivers/dma/dw/core.c > @@ -1569,7 +1569,7 @@ int dw_dma_probe(struct dw_dma_chip *chip) >   (dwc_params >> DWC_PARAMS_MBLK_EN & > 0x1) == 0; >   } else { >   dwc->block_size = pdata->block_size; > - dwc->nollp = pdata->is_nollp; > + dwc->nollp = pdata->hw_llp[i]; >   } >   } >   > diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c > index daeceac..2722e60 100644 > --- a/drivers/dma/dw/platform.c > +++ b/drivers/dma/dw/platform.c > @@ -151,6 +151,11 @@ dw_dma_parse_dt(struct platform_device *pdev) >   pdata->data_width[tmp] = BIT(arr[tmp] & > 0x07); >   } >   > + if (!of_property_read_u32_array(np, "hw-llp", arr, > nr_masters)) { > + for (tmp = 0; tmp < nr_masters; tmp++) > + pdata->hw_llp[tmp] = arr[tmp]; > + } > + >   return pdata; >  } >  #else > diff --git a/include/linux/platform_data/dma-dw.h > b/include/linux/platform_data/dma-dw.h > index 5f0e11e..5bc8124 100644 > --- a/include/linux/platform_data/dma-dw.h > +++ b/include/linux/platform_data/dma-dw.h > @@ -40,19 +40,18 @@ struct dw_dma_slave { >   * @is_private: The device channels should be marked as private and > not for >   * by the general purpose DMA channel allocator. >   * @is_memcpy: The device channels do support memory-to-memory > transfers. > - * @is_nollp: The device channels does not support multi block > transfers. >   * @chan_allocation_order: Allocate channels starting from 0 or 7 >   * @chan_priority: Set channel priority increasing from 0 to 7 or 7 > to 0. >   * @block_size: Maximum block size supported by the controller >   * @nr_masters: Number of AHB masters supported by the controller >   * @data_width: Maximum data width supported by hardware per AHB > master >   * (in bytes, power of 2) > + * @hw_llp: Multi block transfers supported by hardware per AHB > master. >   */ >  struct dw_dma_platform_data { >   unsigned int nr_channels; >   bool is_private; >   bool is_memcpy; > - bool is_nollp; >  #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ >  #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero > */ >   unsigned char chan_allocation_order; > @@ -62,6 +61,7 @@ struct dw_dma_platform_data { >   unsigned int block_size; >   unsigned char nr_masters; >   unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; > + unsigned char hw_llp[DW_DMA_MAX_NR_MASTERS]; >  }; >   >  #endif /* _PLATFORM_DATA_DMA_DW_H */ -- Andy Shevchenko Intel Finland Oy