From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50711) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c7ScT-00074G-45 for qemu-devel@nongnu.org; Thu, 17 Nov 2016 14:45:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c7ScQ-0003QS-1g for qemu-devel@nongnu.org; Thu, 17 Nov 2016 14:45:13 -0500 Received: from gate.crashing.org ([63.228.1.57]:57744) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c7ScP-0003P3-Oq for qemu-devel@nongnu.org; Thu, 17 Nov 2016 14:45:09 -0500 Message-ID: <1479411901.2608.119.camel@kernel.crashing.org> From: Benjamin Herrenschmidt Date: Fri, 18 Nov 2016 06:45:01 +1100 In-Reply-To: <20161117134948.26790-1-ze.vlad@gmail.com> References: <20161117134948.26790-1-ze.vlad@gmail.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] ppc: BOOK3E: nothing should be done when MSR:PR is set List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Vladimir Svoboda , qemu-devel@nongnu.org On Thu, 2016-11-17 at 14:49 +0100, Vladimir Svoboda wrote: > The server architecture (BOOK3S) specifies that any instruction that > sets MSR:PR will also set MSR:EE, IR and DR. > However there is no such behavior specification for the embedded > architecture (BOOK3E). >=20 > Signed-off-by: Vladimir Svoboda Acked-by: Benjamin Herrenschmidt > --- > =C2=A0target-ppc/helper_regs.h | 11 +++++++---- > =C2=A01 file changed, 7 insertions(+), 4 deletions(-) >=20 > diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h > index bb9ce60..6213816 100644 > --- a/target-ppc/helper_regs.h > +++ b/target-ppc/helper_regs.h > @@ -131,11 +131,14 @@ static inline int hreg_store_msr(CPUPPCState > *env, target_ulong value, > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* If PR=3D1 then EE, IR and DR must be 1 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* Note: We only enforce this on 64-bit p= rocessors. It appears > that > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* 32-bit implementations supports PR=3D1= and EE/DR/IR=3D0 and MacOS > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* exploits it. > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* Note: We only enforce this on 64-bit s= erver processors. > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* It appears that: > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* - 32-bit implementations supports PR=3D= 1 and EE/DR/IR=3D0 and > MacOS > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*=C2=A0=C2=A0=C2=A0exploits it. > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* - 64-bit embedded implementations do n= ot need any operation > to be > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*=C2=A0=C2=A0=C2=A0performed when PR is = set. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/ > -=C2=A0=C2=A0=C2=A0=C2=A0if ((env->insns_flags & PPC_64B) && ((value >>= MSR_PR) & 1)) { > +=C2=A0=C2=A0=C2=A0=C2=A0if ((env->insns_flags & PPC_SEGMENT_64B) && ((= value >> MSR_PR) & > 1)) { > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0value |=3D (1 << = MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > =C2=A0#endif