diff for duplicates of <1479491012.22212.35.camel@linux.intel.com> diff --git a/a/1.txt b/N1/1.txt index 2ce9721..d411312 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,4 +1,4 @@ -On Fri, 2016-11-18@19:53 +0300, Eugeniy Paltsev wrote: +On Fri, 2016-11-18 at 19:53 +0300, Eugeniy Paltsev wrote: > Several versions of DW DMAC have multi block transfers hardware > support. Hardware support of multi block transfers is disabled > by default if we use DT to configure DMAC and software emulation @@ -12,13 +12,13 @@ On Fri, 2016-11-18@19:53 +0300, Eugeniy Paltsev wrote: > > Update DT documentation. > -> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> +> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org> > --- -> ?Documentation/devicetree/bindings/dma/snps-dma.txt | 2 ++ -> ?drivers/dma/dw/core.c??????????????????????????????| 2 +- -> ?drivers/dma/dw/platform.c??????????????????????????| 5 +++++ -> ?include/linux/platform_data/dma-dw.h???????????????| 4 ++-- -> ?4 files changed, 10 insertions(+), 3 deletions(-) +> Documentation/devicetree/bindings/dma/snps-dma.txt | 2 ++ +> drivers/dma/dw/core.c | 2 +- +> drivers/dma/dw/platform.c | 5 +++++ +> include/linux/platform_data/dma-dw.h | 4 ++-- +> 4 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt > b/Documentation/devicetree/bindings/dma/snps-dma.txt @@ -26,97 +26,101 @@ On Fri, 2016-11-18@19:53 +0300, Eugeniy Paltsev wrote: > --- a/Documentation/devicetree/bindings/dma/snps-dma.txt > +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt > @@ -27,6 +27,8 @@ Optional properties: -> ???that services interrupts for this device -> ?- is_private: The device channels should be marked as private and not +> that services interrupts for this device +> - is_private: The device channels should be marked as private and not > for by the -> ???general purpose DMA channel allocator. False if not passed. +> general purpose DMA channel allocator. False if not passed. > +- multi-block: Multi block transfers supported by hardware per AHB > master. -> +??0 (default): not supported, 1: supported. +> + 0 (default): not supported, 1: supported. Since default is "not supported" you have to update users accordingly. (Check platform data and existing DTS). -? -> ?Example: -> ? + +> Example: +> > diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c > index c2c0a61..f2a3d06 100644 > --- a/drivers/dma/dw/core.c > +++ b/drivers/dma/dw/core.c > @@ -1569,7 +1569,7 @@ int dw_dma_probe(struct dw_dma_chip *chip) -> ? (dwc_params >> DWC_PARAMS_MBLK_EN & +> (dwc_params >> DWC_PARAMS_MBLK_EN & > 0x1) == 0; -> ? } else { -> ? dwc->block_size = pdata->block_size; +> } else { +> dwc->block_size = pdata->block_size; > - dwc->nollp = pdata->is_nollp; > + dwc->nollp = pdata->multi_block[i]; This inverts the default logic. -> ? } -> ? } -> ? +> } +> } +> > diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c > index aa7a5c1..b262fd3 100644 > --- a/drivers/dma/dw/platform.c > +++ b/drivers/dma/dw/platform.c > @@ -152,6 +152,11 @@ dw_dma_parse_dt(struct platform_device *pdev) -> ? pdata->data_width[tmp] = BIT(arr[tmp] & +> pdata->data_width[tmp] = BIT(arr[tmp] & > 0x07); -> ? } -> ? +> } +> > + if (!of_property_read_u32_array(np, "multi-block", arr, > nr_masters)) { > + for (tmp = 0; tmp < nr_masters; tmp++) > + pdata->multi_block[tmp] = arr[tmp]; > + } > + -> ? return pdata; -> ?} -> ?#else +> return pdata; +> } +> #else > diff --git a/include/linux/platform_data/dma-dw.h > b/include/linux/platform_data/dma-dw.h > index 5f0e11e..0773bb4 100644 > --- a/include/linux/platform_data/dma-dw.h > +++ b/include/linux/platform_data/dma-dw.h > @@ -40,19 +40,18 @@ struct dw_dma_slave { -> ? * @is_private: The device channels should be marked as private and +> * @is_private: The device channels should be marked as private and > not for -> ? * by the general purpose DMA channel allocator. -> ? * @is_memcpy: The device channels do support memory-to-memory +> * by the general purpose DMA channel allocator. +> * @is_memcpy: The device channels do support memory-to-memory > transfers. > - * @is_nollp: The device channels does not support multi block > transfers. -> ? * @chan_allocation_order: Allocate channels starting from 0 or 7 -> ? * @chan_priority: Set channel priority increasing from 0 to 7 or 7 +> * @chan_allocation_order: Allocate channels starting from 0 or 7 +> * @chan_priority: Set channel priority increasing from 0 to 7 or 7 > to 0. -> ? * @block_size: Maximum block size supported by the controller -> ? * @nr_masters: Number of AHB masters supported by the controller -> ? * @data_width: Maximum data width supported by hardware per AHB +> * @block_size: Maximum block size supported by the controller +> * @nr_masters: Number of AHB masters supported by the controller +> * @data_width: Maximum data width supported by hardware per AHB > master -> ? * (in bytes, power of 2) +> * (in bytes, power of 2) > + * @multi_block: Multi block transfers supported by hardware per AHB > master. -> ? */ -> ?struct dw_dma_platform_data { -> ? unsigned int nr_channels; -> ? bool is_private; -> ? bool is_memcpy; +> */ +> struct dw_dma_platform_data { +> unsigned int nr_channels; +> bool is_private; +> bool is_memcpy; > - bool is_nollp; -> ?#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ -> ?#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero +> #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ +> #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero > */ -> ? unsigned char chan_allocation_order; +> unsigned char chan_allocation_order; > @@ -62,6 +61,7 @@ struct dw_dma_platform_data { -> ? unsigned int block_size; -> ? unsigned char nr_masters; -> ? unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; +> unsigned int block_size; +> unsigned char nr_masters; +> unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; > + unsigned char multi_block[DW_DMA_MAX_NR_MASTERS]; -> ?}; -> ? -> ?#endif /* _PLATFORM_DATA_DMA_DW_H */ +> }; +> +> #endif /* _PLATFORM_DATA_DMA_DW_H */ -- -Andy Shevchenko <andriy.shevchenko at linux.intel.com> +Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> Intel Finland Oy +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 1cb27e4..2b8469c 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,12 +1,20 @@ "ref\01479487989-24543-1-git-send-email-Eugeniy.Paltsev@synopsys.com\0" "ref\01479487989-24543-3-git-send-email-Eugeniy.Paltsev@synopsys.com\0" - "From\0andriy.shevchenko@linux.intel.com (Andy Shevchenko)\0" - "Subject\0[PATCH v2 2/2] DW DMAC: add multi-block property to device tree\0" + "ref\01479487989-24543-3-git-send-email-Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org\0" + "From\0Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>\0" + "Subject\0Re: [PATCH v2 2/2] DW DMAC: add multi-block property to device tree\0" "Date\0Fri, 18 Nov 2016 19:43:32 +0200\0" - "To\0linux-snps-arc@lists.infradead.org\0" + "To\0Eugeniy Paltsev <Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>" + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "Cc\0robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" + mark.rutland-5wv7dgnIgG8@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + vinod.koul-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org + dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-snps-arc-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" - "On Fri, 2016-11-18@19:53 +0300, Eugeniy Paltsev wrote:\n" + "On Fri, 2016-11-18 at 19:53 +0300, Eugeniy Paltsev wrote:\n" "> Several versions of DW DMAC have multi block transfers hardware\n" "> support. Hardware support of multi block transfers is disabled\n" "> by default if we use DT to configure DMAC and software emulation\n" @@ -20,13 +28,13 @@ "> \n" "> Update DT documentation.\n" "> \n" - "> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>\n" + "> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>\n" "> ---\n" - "> ?Documentation/devicetree/bindings/dma/snps-dma.txt | 2 ++\n" - "> ?drivers/dma/dw/core.c??????????????????????????????| 2 +-\n" - "> ?drivers/dma/dw/platform.c??????????????????????????| 5 +++++\n" - "> ?include/linux/platform_data/dma-dw.h???????????????| 4 ++--\n" - "> ?4 files changed, 10 insertions(+), 3 deletions(-)\n" + "> \302\240Documentation/devicetree/bindings/dma/snps-dma.txt | 2 ++\n" + "> \302\240drivers/dma/dw/core.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 2 +-\n" + "> \302\240drivers/dma/dw/platform.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 5 +++++\n" + "> \302\240include/linux/platform_data/dma-dw.h\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 4 ++--\n" + "> \302\2404 files changed, 10 insertions(+), 3 deletions(-)\n" "> \n" "> diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt\n" "> b/Documentation/devicetree/bindings/dma/snps-dma.txt\n" @@ -34,99 +42,103 @@ "> --- a/Documentation/devicetree/bindings/dma/snps-dma.txt\n" "> +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt\n" "> @@ -27,6 +27,8 @@ Optional properties:\n" - "> ???that services interrupts for this device\n" - "> ?- is_private: The device channels should be marked as private and not\n" + "> \302\240\302\240\302\240that services interrupts for this device\n" + "> \302\240- is_private: The device channels should be marked as private and not\n" "> for by the\n" - "> ???general purpose DMA channel allocator. False if not passed.\n" + "> \302\240\302\240\302\240general purpose DMA channel allocator. False if not passed.\n" "> +- multi-block: Multi block transfers supported by hardware per AHB\n" "> master.\n" - "> +??0 (default): not supported, 1: supported.\n" + "> +\302\240\302\2400 (default): not supported, 1: supported.\n" "\n" "Since default is \"not supported\" you have to update users accordingly.\n" "(Check platform data and existing DTS).\n" - "?\n" - "> ?Example:\n" - "> ?\n" + "\302\240\n" + "> \302\240Example:\n" + "> \302\240\n" "> diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c\n" "> index c2c0a61..f2a3d06 100644\n" "> --- a/drivers/dma/dw/core.c\n" "> +++ b/drivers/dma/dw/core.c\n" "> @@ -1569,7 +1569,7 @@ int dw_dma_probe(struct dw_dma_chip *chip)\n" - "> ?\t\t\t\t(dwc_params >> DWC_PARAMS_MBLK_EN &\n" + "> \302\240\t\t\t\t(dwc_params >> DWC_PARAMS_MBLK_EN &\n" "> 0x1) == 0;\n" - "> ?\t\t} else {\n" - "> ?\t\t\tdwc->block_size = pdata->block_size;\n" + "> \302\240\t\t} else {\n" + "> \302\240\t\t\tdwc->block_size = pdata->block_size;\n" "\n" "> -\t\t\tdwc->nollp = pdata->is_nollp;\n" "> +\t\t\tdwc->nollp = pdata->multi_block[i];\n" "\n" "This inverts the default logic.\n" "\n" - "> ?\t\t}\n" - "> ?\t}\n" - "> ?\n" + "> \302\240\t\t}\n" + "> \302\240\t}\n" + "> \302\240\n" "> diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c\n" "> index aa7a5c1..b262fd3 100644\n" "> --- a/drivers/dma/dw/platform.c\n" "> +++ b/drivers/dma/dw/platform.c\n" "> @@ -152,6 +152,11 @@ dw_dma_parse_dt(struct platform_device *pdev)\n" - "> ?\t\t\tpdata->data_width[tmp] = BIT(arr[tmp] &\n" + "> \302\240\t\t\tpdata->data_width[tmp] = BIT(arr[tmp] &\n" "> 0x07);\n" - "> ?\t}\n" - "> ?\n" + "> \302\240\t}\n" + "> \302\240\n" "> +\tif (!of_property_read_u32_array(np, \"multi-block\", arr,\n" "> nr_masters)) {\n" "> +\t\tfor (tmp = 0; tmp < nr_masters; tmp++)\n" "> +\t\t\tpdata->multi_block[tmp] = arr[tmp];\n" "> +\t}\n" "> +\n" - "> ?\treturn pdata;\n" - "> ?}\n" - "> ?#else\n" + "> \302\240\treturn pdata;\n" + "> \302\240}\n" + "> \302\240#else\n" "> diff --git a/include/linux/platform_data/dma-dw.h\n" "> b/include/linux/platform_data/dma-dw.h\n" "> index 5f0e11e..0773bb4 100644\n" "> --- a/include/linux/platform_data/dma-dw.h\n" "> +++ b/include/linux/platform_data/dma-dw.h\n" "> @@ -40,19 +40,18 @@ struct dw_dma_slave {\n" - "> ? * @is_private: The device channels should be marked as private and\n" + "> \302\240 * @is_private: The device channels should be marked as private and\n" "> not for\n" - "> ? *\tby the general purpose DMA channel allocator.\n" - "> ? * @is_memcpy: The device channels do support memory-to-memory\n" + "> \302\240 *\tby the general purpose DMA channel allocator.\n" + "> \302\240 * @is_memcpy: The device channels do support memory-to-memory\n" "> transfers.\n" "> - * @is_nollp: The device channels does not support multi block\n" "> transfers.\n" - "> ? * @chan_allocation_order: Allocate channels starting from 0 or 7\n" - "> ? * @chan_priority: Set channel priority increasing from 0 to 7 or 7\n" + "> \302\240 * @chan_allocation_order: Allocate channels starting from 0 or 7\n" + "> \302\240 * @chan_priority: Set channel priority increasing from 0 to 7 or 7\n" "> to 0.\n" - "> ? * @block_size: Maximum block size supported by the controller\n" - "> ? * @nr_masters: Number of AHB masters supported by the controller\n" - "> ? * @data_width: Maximum data width supported by hardware per AHB\n" + "> \302\240 * @block_size: Maximum block size supported by the controller\n" + "> \302\240 * @nr_masters: Number of AHB masters supported by the controller\n" + "> \302\240 * @data_width: Maximum data width supported by hardware per AHB\n" "> master\n" - "> ? *\t\t(in bytes, power of 2)\n" + "> \302\240 *\t\t(in bytes, power of 2)\n" "> + * @multi_block: Multi block transfers supported by hardware per AHB\n" "> master.\n" - "> ? */\n" - "> ?struct dw_dma_platform_data {\n" - "> ?\tunsigned int\tnr_channels;\n" - "> ?\tbool\t\tis_private;\n" - "> ?\tbool\t\tis_memcpy;\n" + "> \302\240 */\n" + "> \302\240struct dw_dma_platform_data {\n" + "> \302\240\tunsigned int\tnr_channels;\n" + "> \302\240\tbool\t\tis_private;\n" + "> \302\240\tbool\t\tis_memcpy;\n" "> -\tbool\t\tis_nollp;\n" - "> ?#define CHAN_ALLOCATION_ASCENDING\t0\t/* zero to seven */\n" - "> ?#define CHAN_ALLOCATION_DESCENDING\t1\t/* seven to zero\n" + "> \302\240#define CHAN_ALLOCATION_ASCENDING\t0\t/* zero to seven */\n" + "> \302\240#define CHAN_ALLOCATION_DESCENDING\t1\t/* seven to zero\n" "> */\n" - "> ?\tunsigned char\tchan_allocation_order;\n" + "> \302\240\tunsigned char\tchan_allocation_order;\n" "> @@ -62,6 +61,7 @@ struct dw_dma_platform_data {\n" - "> ?\tunsigned int\tblock_size;\n" - "> ?\tunsigned char\tnr_masters;\n" - "> ?\tunsigned char\tdata_width[DW_DMA_MAX_NR_MASTERS];\n" + "> \302\240\tunsigned int\tblock_size;\n" + "> \302\240\tunsigned char\tnr_masters;\n" + "> \302\240\tunsigned char\tdata_width[DW_DMA_MAX_NR_MASTERS];\n" "> +\tunsigned char\tmulti_block[DW_DMA_MAX_NR_MASTERS];\n" - "> ?};\n" - "> ?\n" - "> ?#endif /* _PLATFORM_DATA_DMA_DW_H */\n" + "> \302\240};\n" + "> \302\240\n" + "> \302\240#endif /* _PLATFORM_DATA_DMA_DW_H */\n" "\n" "-- \n" - "Andy Shevchenko <andriy.shevchenko at linux.intel.com>\n" - Intel Finland Oy + "Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>\n" + "Intel Finland Oy\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -11afd2b0fc0517ea8e9c92b17449f701a21613952b8d6929f28ef0f454fc6d6e +bf5e992d6373c4ddd2f03d3da498865e6078234a69275437d882eb7bb70ef087
diff --git a/a/1.txt b/N2/1.txt index 2ce9721..bf0b5c6 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,4 +1,4 @@ -On Fri, 2016-11-18@19:53 +0300, Eugeniy Paltsev wrote: +On Fri, 2016-11-18 at 19:53 +0300, Eugeniy Paltsev wrote: > Several versions of DW DMAC have multi block transfers hardware > support. Hardware support of multi block transfers is disabled > by default if we use DT to configure DMAC and software emulation @@ -12,13 +12,13 @@ On Fri, 2016-11-18@19:53 +0300, Eugeniy Paltsev wrote: > > Update DT documentation. > -> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> +> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> > --- -> ?Documentation/devicetree/bindings/dma/snps-dma.txt | 2 ++ -> ?drivers/dma/dw/core.c??????????????????????????????| 2 +- -> ?drivers/dma/dw/platform.c??????????????????????????| 5 +++++ -> ?include/linux/platform_data/dma-dw.h???????????????| 4 ++-- -> ?4 files changed, 10 insertions(+), 3 deletions(-) +> Documentation/devicetree/bindings/dma/snps-dma.txt | 2 ++ +> drivers/dma/dw/core.c | 2 +- +> drivers/dma/dw/platform.c | 5 +++++ +> include/linux/platform_data/dma-dw.h | 4 ++-- +> 4 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt > b/Documentation/devicetree/bindings/dma/snps-dma.txt @@ -26,97 +26,97 @@ On Fri, 2016-11-18@19:53 +0300, Eugeniy Paltsev wrote: > --- a/Documentation/devicetree/bindings/dma/snps-dma.txt > +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt > @@ -27,6 +27,8 @@ Optional properties: -> ???that services interrupts for this device -> ?- is_private: The device channels should be marked as private and not +> that services interrupts for this device +> - is_private: The device channels should be marked as private and not > for by the -> ???general purpose DMA channel allocator. False if not passed. +> general purpose DMA channel allocator. False if not passed. > +- multi-block: Multi block transfers supported by hardware per AHB > master. -> +??0 (default): not supported, 1: supported. +> + 0 (default): not supported, 1: supported. Since default is "not supported" you have to update users accordingly. (Check platform data and existing DTS). -? -> ?Example: -> ? + +> Example: +> > diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c > index c2c0a61..f2a3d06 100644 > --- a/drivers/dma/dw/core.c > +++ b/drivers/dma/dw/core.c > @@ -1569,7 +1569,7 @@ int dw_dma_probe(struct dw_dma_chip *chip) -> ? (dwc_params >> DWC_PARAMS_MBLK_EN & +> (dwc_params >> DWC_PARAMS_MBLK_EN & > 0x1) == 0; -> ? } else { -> ? dwc->block_size = pdata->block_size; +> } else { +> dwc->block_size = pdata->block_size; > - dwc->nollp = pdata->is_nollp; > + dwc->nollp = pdata->multi_block[i]; This inverts the default logic. -> ? } -> ? } -> ? +> } +> } +> > diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c > index aa7a5c1..b262fd3 100644 > --- a/drivers/dma/dw/platform.c > +++ b/drivers/dma/dw/platform.c > @@ -152,6 +152,11 @@ dw_dma_parse_dt(struct platform_device *pdev) -> ? pdata->data_width[tmp] = BIT(arr[tmp] & +> pdata->data_width[tmp] = BIT(arr[tmp] & > 0x07); -> ? } -> ? +> } +> > + if (!of_property_read_u32_array(np, "multi-block", arr, > nr_masters)) { > + for (tmp = 0; tmp < nr_masters; tmp++) > + pdata->multi_block[tmp] = arr[tmp]; > + } > + -> ? return pdata; -> ?} -> ?#else +> return pdata; +> } +> #else > diff --git a/include/linux/platform_data/dma-dw.h > b/include/linux/platform_data/dma-dw.h > index 5f0e11e..0773bb4 100644 > --- a/include/linux/platform_data/dma-dw.h > +++ b/include/linux/platform_data/dma-dw.h > @@ -40,19 +40,18 @@ struct dw_dma_slave { -> ? * @is_private: The device channels should be marked as private and +> * @is_private: The device channels should be marked as private and > not for -> ? * by the general purpose DMA channel allocator. -> ? * @is_memcpy: The device channels do support memory-to-memory +> * by the general purpose DMA channel allocator. +> * @is_memcpy: The device channels do support memory-to-memory > transfers. > - * @is_nollp: The device channels does not support multi block > transfers. -> ? * @chan_allocation_order: Allocate channels starting from 0 or 7 -> ? * @chan_priority: Set channel priority increasing from 0 to 7 or 7 +> * @chan_allocation_order: Allocate channels starting from 0 or 7 +> * @chan_priority: Set channel priority increasing from 0 to 7 or 7 > to 0. -> ? * @block_size: Maximum block size supported by the controller -> ? * @nr_masters: Number of AHB masters supported by the controller -> ? * @data_width: Maximum data width supported by hardware per AHB +> * @block_size: Maximum block size supported by the controller +> * @nr_masters: Number of AHB masters supported by the controller +> * @data_width: Maximum data width supported by hardware per AHB > master -> ? * (in bytes, power of 2) +> * (in bytes, power of 2) > + * @multi_block: Multi block transfers supported by hardware per AHB > master. -> ? */ -> ?struct dw_dma_platform_data { -> ? unsigned int nr_channels; -> ? bool is_private; -> ? bool is_memcpy; +> */ +> struct dw_dma_platform_data { +> unsigned int nr_channels; +> bool is_private; +> bool is_memcpy; > - bool is_nollp; -> ?#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ -> ?#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero +> #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ +> #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero > */ -> ? unsigned char chan_allocation_order; +> unsigned char chan_allocation_order; > @@ -62,6 +61,7 @@ struct dw_dma_platform_data { -> ? unsigned int block_size; -> ? unsigned char nr_masters; -> ? unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; +> unsigned int block_size; +> unsigned char nr_masters; +> unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; > + unsigned char multi_block[DW_DMA_MAX_NR_MASTERS]; -> ?}; -> ? -> ?#endif /* _PLATFORM_DATA_DMA_DW_H */ +> }; +> +> #endif /* _PLATFORM_DATA_DMA_DW_H */ -- -Andy Shevchenko <andriy.shevchenko at linux.intel.com> +Andy Shevchenko <andriy.shevchenko@linux.intel.com> Intel Finland Oy diff --git a/a/content_digest b/N2/content_digest index 1cb27e4..9cca1f7 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,12 +1,19 @@ "ref\01479487989-24543-1-git-send-email-Eugeniy.Paltsev@synopsys.com\0" "ref\01479487989-24543-3-git-send-email-Eugeniy.Paltsev@synopsys.com\0" - "From\0andriy.shevchenko@linux.intel.com (Andy Shevchenko)\0" - "Subject\0[PATCH v2 2/2] DW DMAC: add multi-block property to device tree\0" + "From\0Andy Shevchenko <andriy.shevchenko@linux.intel.com>\0" + "Subject\0Re: [PATCH v2 2/2] DW DMAC: add multi-block property to device tree\0" "Date\0Fri, 18 Nov 2016 19:43:32 +0200\0" - "To\0linux-snps-arc@lists.infradead.org\0" + "To\0Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>" + " devicetree@vger.kernel.org\0" + "Cc\0robh+dt@kernel.org" + mark.rutland@arm.com + linux-kernel@vger.kernel.org + vinod.koul@intel.com + dmaengine@vger.kernel.org + " linux-snps-arc@lists.infradead.org\0" "\00:1\0" "b\0" - "On Fri, 2016-11-18@19:53 +0300, Eugeniy Paltsev wrote:\n" + "On Fri, 2016-11-18 at 19:53 +0300, Eugeniy Paltsev wrote:\n" "> Several versions of DW DMAC have multi block transfers hardware\n" "> support. Hardware support of multi block transfers is disabled\n" "> by default if we use DT to configure DMAC and software emulation\n" @@ -20,13 +27,13 @@ "> \n" "> Update DT documentation.\n" "> \n" - "> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>\n" + "> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\n" "> ---\n" - "> ?Documentation/devicetree/bindings/dma/snps-dma.txt | 2 ++\n" - "> ?drivers/dma/dw/core.c??????????????????????????????| 2 +-\n" - "> ?drivers/dma/dw/platform.c??????????????????????????| 5 +++++\n" - "> ?include/linux/platform_data/dma-dw.h???????????????| 4 ++--\n" - "> ?4 files changed, 10 insertions(+), 3 deletions(-)\n" + "> \302\240Documentation/devicetree/bindings/dma/snps-dma.txt | 2 ++\n" + "> \302\240drivers/dma/dw/core.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 2 +-\n" + "> \302\240drivers/dma/dw/platform.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 5 +++++\n" + "> \302\240include/linux/platform_data/dma-dw.h\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 4 ++--\n" + "> \302\2404 files changed, 10 insertions(+), 3 deletions(-)\n" "> \n" "> diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt\n" "> b/Documentation/devicetree/bindings/dma/snps-dma.txt\n" @@ -34,99 +41,99 @@ "> --- a/Documentation/devicetree/bindings/dma/snps-dma.txt\n" "> +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt\n" "> @@ -27,6 +27,8 @@ Optional properties:\n" - "> ???that services interrupts for this device\n" - "> ?- is_private: The device channels should be marked as private and not\n" + "> \302\240\302\240\302\240that services interrupts for this device\n" + "> \302\240- is_private: The device channels should be marked as private and not\n" "> for by the\n" - "> ???general purpose DMA channel allocator. False if not passed.\n" + "> \302\240\302\240\302\240general purpose DMA channel allocator. False if not passed.\n" "> +- multi-block: Multi block transfers supported by hardware per AHB\n" "> master.\n" - "> +??0 (default): not supported, 1: supported.\n" + "> +\302\240\302\2400 (default): not supported, 1: supported.\n" "\n" "Since default is \"not supported\" you have to update users accordingly.\n" "(Check platform data and existing DTS).\n" - "?\n" - "> ?Example:\n" - "> ?\n" + "\302\240\n" + "> \302\240Example:\n" + "> \302\240\n" "> diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c\n" "> index c2c0a61..f2a3d06 100644\n" "> --- a/drivers/dma/dw/core.c\n" "> +++ b/drivers/dma/dw/core.c\n" "> @@ -1569,7 +1569,7 @@ int dw_dma_probe(struct dw_dma_chip *chip)\n" - "> ?\t\t\t\t(dwc_params >> DWC_PARAMS_MBLK_EN &\n" + "> \302\240\t\t\t\t(dwc_params >> DWC_PARAMS_MBLK_EN &\n" "> 0x1) == 0;\n" - "> ?\t\t} else {\n" - "> ?\t\t\tdwc->block_size = pdata->block_size;\n" + "> \302\240\t\t} else {\n" + "> \302\240\t\t\tdwc->block_size = pdata->block_size;\n" "\n" "> -\t\t\tdwc->nollp = pdata->is_nollp;\n" "> +\t\t\tdwc->nollp = pdata->multi_block[i];\n" "\n" "This inverts the default logic.\n" "\n" - "> ?\t\t}\n" - "> ?\t}\n" - "> ?\n" + "> \302\240\t\t}\n" + "> \302\240\t}\n" + "> \302\240\n" "> diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c\n" "> index aa7a5c1..b262fd3 100644\n" "> --- a/drivers/dma/dw/platform.c\n" "> +++ b/drivers/dma/dw/platform.c\n" "> @@ -152,6 +152,11 @@ dw_dma_parse_dt(struct platform_device *pdev)\n" - "> ?\t\t\tpdata->data_width[tmp] = BIT(arr[tmp] &\n" + "> \302\240\t\t\tpdata->data_width[tmp] = BIT(arr[tmp] &\n" "> 0x07);\n" - "> ?\t}\n" - "> ?\n" + "> \302\240\t}\n" + "> \302\240\n" "> +\tif (!of_property_read_u32_array(np, \"multi-block\", arr,\n" "> nr_masters)) {\n" "> +\t\tfor (tmp = 0; tmp < nr_masters; tmp++)\n" "> +\t\t\tpdata->multi_block[tmp] = arr[tmp];\n" "> +\t}\n" "> +\n" - "> ?\treturn pdata;\n" - "> ?}\n" - "> ?#else\n" + "> \302\240\treturn pdata;\n" + "> \302\240}\n" + "> \302\240#else\n" "> diff --git a/include/linux/platform_data/dma-dw.h\n" "> b/include/linux/platform_data/dma-dw.h\n" "> index 5f0e11e..0773bb4 100644\n" "> --- a/include/linux/platform_data/dma-dw.h\n" "> +++ b/include/linux/platform_data/dma-dw.h\n" "> @@ -40,19 +40,18 @@ struct dw_dma_slave {\n" - "> ? * @is_private: The device channels should be marked as private and\n" + "> \302\240 * @is_private: The device channels should be marked as private and\n" "> not for\n" - "> ? *\tby the general purpose DMA channel allocator.\n" - "> ? * @is_memcpy: The device channels do support memory-to-memory\n" + "> \302\240 *\tby the general purpose DMA channel allocator.\n" + "> \302\240 * @is_memcpy: The device channels do support memory-to-memory\n" "> transfers.\n" "> - * @is_nollp: The device channels does not support multi block\n" "> transfers.\n" - "> ? * @chan_allocation_order: Allocate channels starting from 0 or 7\n" - "> ? * @chan_priority: Set channel priority increasing from 0 to 7 or 7\n" + "> \302\240 * @chan_allocation_order: Allocate channels starting from 0 or 7\n" + "> \302\240 * @chan_priority: Set channel priority increasing from 0 to 7 or 7\n" "> to 0.\n" - "> ? * @block_size: Maximum block size supported by the controller\n" - "> ? * @nr_masters: Number of AHB masters supported by the controller\n" - "> ? * @data_width: Maximum data width supported by hardware per AHB\n" + "> \302\240 * @block_size: Maximum block size supported by the controller\n" + "> \302\240 * @nr_masters: Number of AHB masters supported by the controller\n" + "> \302\240 * @data_width: Maximum data width supported by hardware per AHB\n" "> master\n" - "> ? *\t\t(in bytes, power of 2)\n" + "> \302\240 *\t\t(in bytes, power of 2)\n" "> + * @multi_block: Multi block transfers supported by hardware per AHB\n" "> master.\n" - "> ? */\n" - "> ?struct dw_dma_platform_data {\n" - "> ?\tunsigned int\tnr_channels;\n" - "> ?\tbool\t\tis_private;\n" - "> ?\tbool\t\tis_memcpy;\n" + "> \302\240 */\n" + "> \302\240struct dw_dma_platform_data {\n" + "> \302\240\tunsigned int\tnr_channels;\n" + "> \302\240\tbool\t\tis_private;\n" + "> \302\240\tbool\t\tis_memcpy;\n" "> -\tbool\t\tis_nollp;\n" - "> ?#define CHAN_ALLOCATION_ASCENDING\t0\t/* zero to seven */\n" - "> ?#define CHAN_ALLOCATION_DESCENDING\t1\t/* seven to zero\n" + "> \302\240#define CHAN_ALLOCATION_ASCENDING\t0\t/* zero to seven */\n" + "> \302\240#define CHAN_ALLOCATION_DESCENDING\t1\t/* seven to zero\n" "> */\n" - "> ?\tunsigned char\tchan_allocation_order;\n" + "> \302\240\tunsigned char\tchan_allocation_order;\n" "> @@ -62,6 +61,7 @@ struct dw_dma_platform_data {\n" - "> ?\tunsigned int\tblock_size;\n" - "> ?\tunsigned char\tnr_masters;\n" - "> ?\tunsigned char\tdata_width[DW_DMA_MAX_NR_MASTERS];\n" + "> \302\240\tunsigned int\tblock_size;\n" + "> \302\240\tunsigned char\tnr_masters;\n" + "> \302\240\tunsigned char\tdata_width[DW_DMA_MAX_NR_MASTERS];\n" "> +\tunsigned char\tmulti_block[DW_DMA_MAX_NR_MASTERS];\n" - "> ?};\n" - "> ?\n" - "> ?#endif /* _PLATFORM_DATA_DMA_DW_H */\n" + "> \302\240};\n" + "> \302\240\n" + "> \302\240#endif /* _PLATFORM_DATA_DMA_DW_H */\n" "\n" "-- \n" - "Andy Shevchenko <andriy.shevchenko at linux.intel.com>\n" + "Andy Shevchenko <andriy.shevchenko@linux.intel.com>\n" Intel Finland Oy -11afd2b0fc0517ea8e9c92b17449f701a21613952b8d6929f28ef0f454fc6d6e +434f0fb4acc73b65b3d9d2b77aa6dd145ae6fc436312a6f93c2e401b22c8d2d0
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.