From mboxrd@z Thu Jan 1 00:00:00 1970 From: Brian Starkey Subject: [PATCH 4/6] drm: mali-dp: Add support for writeback on DP550/DP650 Date: Fri, 25 Nov 2016 16:49:02 +0000 Message-ID: <1480092544-1725-5-git-send-email-brian.starkey@arm.com> References: <1480092544-1725-1-git-send-email-brian.starkey@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by gabe.freedesktop.org (Postfix) with ESMTP id 338816E8CA for ; Fri, 25 Nov 2016 16:49:29 +0000 (UTC) In-Reply-To: <1480092544-1725-1-git-send-email-brian.starkey@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Liviu Dudau , laurent.pinchart@ideasonboard.com, linux-media@vger.kernel.org List-Id: dri-devel@lists.freedesktop.org RnJvbTogTGl2aXUgRHVkYXUgPExpdml1LkR1ZGF1QGFybS5jb20+CgpNYWxpLURQIGRpc3BsYXkg cHJvY2Vzc29ycyBhcmUgYWJsZSB0byB3cml0ZSB0aGUgY29tcG9zaXRpb24gcmVzdWx0IHRvIGEK bWVtb3J5IGJ1ZmZlciB2aWEgdGhlIFNFLgoKQWRkIGVudHJ5IHBvaW50cyBpbiB0aGUgSEFMIGZv ciBlbmFibGluZy9kaXNhYmxpbmcgdGhpcyBmZWF0dXJlLCBhbmQKaW1wbGVtZW50IHN1cHBvcnQg Zm9yIGl0IG9uIERQNjUwIGFuZCBEUDU1MC4gRFA1MDAgYWN0cyBkaWZmZXJlbnRseSBhbmQKc28g aXMgb21pdHRlZCBmcm9tIHRoaXMgY2hhbmdlLgoKU2lnbmVkLW9mZi1ieTogTGl2aXUgRHVkYXUg PExpdml1LkR1ZGF1QGFybS5jb20+ClNpZ25lZC1vZmYtYnk6IEJyaWFuIFN0YXJrZXkgPGJyaWFu LnN0YXJrZXlAYXJtLmNvbT4KLS0tCiBkcml2ZXJzL2dwdS9kcm0vYXJtL21hbGlkcF9ody5jICAg fCAgIDUyICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrLS0KIGRyaXZlcnMvZ3B1 L2RybS9hcm0vbWFsaWRwX2h3LmggICB8ICAgMTggKysrKysrKysrKysrKwogZHJpdmVycy9ncHUv ZHJtL2FybS9tYWxpZHBfcmVncy5oIHwgICAxNSArKysrKysrKysrKwogMyBmaWxlcyBjaGFuZ2Vk LCA4MyBpbnNlcnRpb25zKCspLCAyIGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMv Z3B1L2RybS9hcm0vbWFsaWRwX2h3LmMgYi9kcml2ZXJzL2dwdS9kcm0vYXJtL21hbGlkcF9ody5j CmluZGV4IDllYzZkNjkuLmM2OTZlNjcgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9hcm0v bWFsaWRwX2h3LmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL2FybS9tYWxpZHBfaHcuYwpAQCAtMzg0 LDYgKzM4NCw0OCBAQCBzdGF0aWMgaW50IG1hbGlkcDU1MF9yb3RtZW1fcmVxdWlyZWQoc3RydWN0 IG1hbGlkcF9od19kZXZpY2UgKmh3ZGV2LCB1MTYgdywgdTE2CiAJcmV0dXJuIHcgKiBieXRlc19w ZXJfY29sOwogfQogCitzdGF0aWMgaW50IG1hbGlkcDU1MF9lbmFibGVfbWVtd3JpdGUoc3RydWN0 IG1hbGlkcF9od19kZXZpY2UgKmh3ZGV2LAorCQkJCSAgICAgZG1hX2FkZHJfdCAqYWRkcnMsIHMz MiAqcGl0Y2hlcywKKwkJCQkgICAgIGludCBudW1fcGxhbmVzLCB1MTYgdywgdTE2IGgsIHUzMiBm bXRfaWQpCit7CisJdTMyIGJhc2UgPSBNQUxJRFA1NTBfU0VfTUVNV1JJVEVfQkFTRTsKKwl1MzIg ZGVfYmFzZSA9IG1hbGlkcF9nZXRfYmxvY2tfYmFzZShod2RldiwgTUFMSURQX0RFX0JMT0NLKTsK KworCS8qIGVuYWJsZSB0aGUgc2NhbGluZyBlbmdpbmUgYmxvY2sgKi8KKwltYWxpZHBfaHdfc2V0 Yml0cyhod2RldiwgTUFMSURQX1NDQUxFX0VOR0lORV9FTiwgZGVfYmFzZSArIE1BTElEUF9ERV9E SVNQTEFZX0ZVTkMpOworCisJbWFsaWRwX2h3X3dyaXRlKGh3ZGV2LCBmbXRfaWQsIGJhc2UgKyBN QUxJRFBfTVdfRk9STUFUKTsKKwlzd2l0Y2ggKG51bV9wbGFuZXMpIHsKKwljYXNlIDI6CisJCW1h bGlkcF9od193cml0ZShod2RldiwgbG93ZXJfMzJfYml0cyhhZGRyc1sxXSksIGJhc2UgKyBNQUxJ RFBfTVdfUDJfUFRSX0xPVyk7CisJCW1hbGlkcF9od193cml0ZShod2RldiwgdXBwZXJfMzJfYml0 cyhhZGRyc1sxXSksIGJhc2UgKyBNQUxJRFBfTVdfUDJfUFRSX0hJR0gpOworCQltYWxpZHBfaHdf d3JpdGUoaHdkZXYsIHBpdGNoZXNbMV0sIGJhc2UgKyBNQUxJRFBfTVdfUDJfU1RSSURFKTsKKwkJ LyogZmFsbCB0aHJvdWdoICovCisJY2FzZSAxOgorCQltYWxpZHBfaHdfd3JpdGUoaHdkZXYsIGxv d2VyXzMyX2JpdHMoYWRkcnNbMF0pLCBiYXNlICsgTUFMSURQX01XX1AxX1BUUl9MT1cpOworCQlt YWxpZHBfaHdfd3JpdGUoaHdkZXYsIHVwcGVyXzMyX2JpdHMoYWRkcnNbMF0pLCBiYXNlICsgTUFM SURQX01XX1AxX1BUUl9ISUdIKTsKKwkJbWFsaWRwX2h3X3dyaXRlKGh3ZGV2LCBwaXRjaGVzWzBd LCBiYXNlICsgTUFMSURQX01XX1AxX1NUUklERSk7CisJCWJyZWFrOworCWRlZmF1bHQ6CisJCVdB Uk4oMSwgIkludmFsaWQgbnVtYmVyIG9mIHBsYW5lcyIpOworCX0KKworCW1hbGlkcF9od193cml0 ZShod2RldiwgTUFMSURQX0RFX0hfQUNUSVZFKHcpIHwgTUFMSURQX0RFX1ZfQUNUSVZFKGgpLAor CQkJTUFMSURQNTUwX1NFX01FTVdSSVRFX09VVF9TSVpFKTsKKwltYWxpZHBfaHdfc2V0Yml0cyho d2RldiwgTUFMSURQNTUwX1NFX01FTVdSSVRFX09ORVNIT1QgfCBNQUxJRFBfU0VfTUVNV1JJVEVf RU4sCisJCQkgIE1BTElEUDU1MF9TRV9DT05UUk9MKTsKKworCXJldHVybiAwOworfQorCitzdGF0 aWMgdm9pZCBtYWxpZHA1NTBfZGlzYWJsZV9tZW13cml0ZShzdHJ1Y3QgbWFsaWRwX2h3X2Rldmlj ZSAqaHdkZXYpCit7CisJdTMyIGJhc2UgPSBtYWxpZHBfZ2V0X2Jsb2NrX2Jhc2UoaHdkZXYsIE1B TElEUF9ERV9CTE9DSyk7CisJbWFsaWRwX2h3X2NsZWFyYml0cyhod2RldiwgTUFMSURQNTUwX1NF X01FTVdSSVRFX09ORVNIT1QgfCBNQUxJRFBfU0VfTUVNV1JJVEVfRU4sCisJCQkgICAgTUFMSURQ NTUwX1NFX0NPTlRST0wpOworCW1hbGlkcF9od19jbGVhcmJpdHMoaHdkZXYsIE1BTElEUF9TQ0FM RV9FTkdJTkVfRU4sIGJhc2UgKyBNQUxJRFBfREVfRElTUExBWV9GVU5DKTsKK30KKwogc3RhdGlj IGludCBtYWxpZHA2NTBfcXVlcnlfaHcoc3RydWN0IG1hbGlkcF9od19kZXZpY2UgKmh3ZGV2KQog ewogCXUzMiBjb25mID0gbWFsaWRwX2h3X3JlYWQoaHdkZXYsIE1BTElEUDU1MF9DT05GSUdfSUQp OwpAQCAtNDY2LDcgKzUwOCw4IEBAIHN0YXRpYyBpbnQgbWFsaWRwNjUwX3F1ZXJ5X2h3KHN0cnVj dCBtYWxpZHBfaHdfZGV2aWNlICpod2RldikKIAkJCQkJICAgIE1BTElEUDU1MF9TRV9JUlFfQVhJ X0VSUiwKIAkJCX0sCiAJCQkuZGNfaXJxX21hcCA9IHsKLQkJCQkuaXJxX21hc2sgPSBNQUxJRFA1 NTBfRENfSVJRX0NPTkZfVkFMSUQsCisJCQkJLmlycV9tYXNrID0gTUFMSURQNTUwX0RDX0lSUV9D T05GX1ZBTElEIHwKKwkJCQkJICAgIE1BTElEUDU1MF9EQ19JUlFfU0UsCiAJCQkJLnZzeW5jX2ly cSA9IE1BTElEUDU1MF9EQ19JUlFfQ09ORl9WQUxJRCwKIAkJCX0sCiAJCQkucGl4ZWxfZm9ybWF0 cyA9IG1hbGlkcDU1MF9kZV9mb3JtYXRzLApAQCAtNDgwLDYgKzUyMyw4IEBAIHN0YXRpYyBpbnQg bWFsaWRwNjUwX3F1ZXJ5X2h3KHN0cnVjdCBtYWxpZHBfaHdfZGV2aWNlICpod2RldikKIAkJLnNl dF9jb25maWdfdmFsaWQgPSBtYWxpZHA1NTBfc2V0X2NvbmZpZ192YWxpZCwKIAkJLm1vZGVzZXQg PSBtYWxpZHA1NTBfbW9kZXNldCwKIAkJLnJvdG1lbV9yZXF1aXJlZCA9IG1hbGlkcDU1MF9yb3Rt ZW1fcmVxdWlyZWQsCisJCS5lbmFibGVfbWVtd3JpdGUgPSBtYWxpZHA1NTBfZW5hYmxlX21lbXdy aXRlLAorCQkuZGlzYWJsZV9tZW13cml0ZSA9IG1hbGlkcDU1MF9kaXNhYmxlX21lbXdyaXRlLAog CX0sCiAJW01BTElEUF82NTBdID0gewogCQkubWFwID0gewpAQCAtNTAwLDcgKzU0NSw4IEBAIHN0 YXRpYyBpbnQgbWFsaWRwNjUwX3F1ZXJ5X2h3KHN0cnVjdCBtYWxpZHBfaHdfZGV2aWNlICpod2Rl dikKIAkJCQkJICAgIE1BTElEUDU1MF9TRV9JUlFfQVhJX0VSUiwKIAkJCX0sCiAJCQkuZGNfaXJx X21hcCA9IHsKLQkJCQkuaXJxX21hc2sgPSBNQUxJRFA1NTBfRENfSVJRX0NPTkZfVkFMSUQsCisJ CQkJLmlycV9tYXNrID0gTUFMSURQNTUwX0RDX0lSUV9DT05GX1ZBTElEIHwKKwkJCQkJICAgIE1B TElEUDU1MF9EQ19JUlFfU0UsCiAJCQkJLnZzeW5jX2lycSA9IE1BTElEUDU1MF9EQ19JUlFfQ09O Rl9WQUxJRCwKIAkJCX0sCiAJCQkucGl4ZWxfZm9ybWF0cyA9IG1hbGlkcDU1MF9kZV9mb3JtYXRz LApAQCAtNTE0LDYgKzU2MCw4IEBAIHN0YXRpYyBpbnQgbWFsaWRwNjUwX3F1ZXJ5X2h3KHN0cnVj dCBtYWxpZHBfaHdfZGV2aWNlICpod2RldikKIAkJLnNldF9jb25maWdfdmFsaWQgPSBtYWxpZHA1 NTBfc2V0X2NvbmZpZ192YWxpZCwKIAkJLm1vZGVzZXQgPSBtYWxpZHA1NTBfbW9kZXNldCwKIAkJ LnJvdG1lbV9yZXF1aXJlZCA9IG1hbGlkcDU1MF9yb3RtZW1fcmVxdWlyZWQsCisJCS5lbmFibGVf bWVtd3JpdGUgPSBtYWxpZHA1NTBfZW5hYmxlX21lbXdyaXRlLAorCQkuZGlzYWJsZV9tZW13cml0 ZSA9IG1hbGlkcDU1MF9kaXNhYmxlX21lbXdyaXRlLAogCX0sCiB9OwogCmRpZmYgLS1naXQgYS9k cml2ZXJzL2dwdS9kcm0vYXJtL21hbGlkcF9ody5oIGIvZHJpdmVycy9ncHUvZHJtL2FybS9tYWxp ZHBfaHcuaAppbmRleCA0ZjhjODg0Li4wOTExNzFkIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9k cm0vYXJtL21hbGlkcF9ody5oCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9hcm0vbWFsaWRwX2h3LmgK QEAgLTE0Niw2ICsxNDYsMjQgQEAgc3RydWN0IG1hbGlkcF9od19kZXZpY2UgewogCSAqLwogCWlu dCAoKnJvdG1lbV9yZXF1aXJlZCkoc3RydWN0IG1hbGlkcF9od19kZXZpY2UgKmh3ZGV2LCB1MTYg dywgdTE2IGgsIHUzMiBmbXQpOwogCisJLyoqCisJICogRW5hYmxlIHdyaXRpbmcgdG8gbWVtb3J5 IHRoZSBjb250ZW50IG9mIHRoZSBuZXh0IGZyYW1lCisJICogQHBhcmFtIGh3ZGV2IC0gbWFsaWRw X2h3X2RldmljZSBzdHJ1Y3R1cmUgY29udGFpbmluZyB0aGUgSFcgZGVzY3JpcHRpb24KKwkgKiBA cGFyYW0gYWRkcnMgLSBhcnJheSBvZiBhZGRyZXNzZXMgZm9yIGVhY2ggcGxhbmUKKwkgKiBAcGFy YW0gcGl0Y2hlcyAtIGFycmF5IG9mIHBpdGNoZXMgZm9yIGVhY2ggcGxhbmUKKwkgKiBAcGFyYW0g bnVtX3BsYW5lcyAtIG51bWJlciBvZiBwbGFuZXMgdG8gYmUgd3JpdHRlbgorCSAqIEBwYXJhbSB3 IC0gd2lkdGggb2YgdGhlIG91dHB1dCBmcmFtZQorCSAqIEBwYXJhbSBoIC0gaGVpZ2h0IG9mIHRo ZSBvdXRwdXQgZnJhbWUKKwkgKiBAcGFyYW0gZm10X2lkIC0gaW50ZXJuYWwgZm9ybWF0IElEIG9m IG91dHB1dCBidWZmZXIKKwkgKi8KKwlpbnQgKCplbmFibGVfbWVtd3JpdGUpKHN0cnVjdCBtYWxp ZHBfaHdfZGV2aWNlICpod2RldiwgZG1hX2FkZHJfdCAqYWRkcnMsCisJCQkgICAgICAgczMyICpw aXRjaGVzLCBpbnQgbnVtX3BsYW5lcywgdTE2IHcsIHUxNiBoLCB1MzIgZm10X2lkKTsKKworCS8q CisJICogRGlzYWJsZSB0aGUgd3JpdGluZyB0byBtZW1vcnkgb2YgdGhlIG5leHQgZnJhbWUncyBj b250ZW50LgorCSAqLworCXZvaWQgKCpkaXNhYmxlX21lbXdyaXRlKShzdHJ1Y3QgbWFsaWRwX2h3 X2RldmljZSAqaHdkZXYpOworCiAJdTggZmVhdHVyZXM7CiAKIAl1OCBtaW5fbGluZV9zaXplOwpk aWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2FybS9tYWxpZHBfcmVncy5oIGIvZHJpdmVycy9n cHUvZHJtL2FybS9tYWxpZHBfcmVncy5oCmluZGV4IDczZmVjYjMuLmNhYjA4NmMgMTAwNjQ0Ci0t LSBhL2RyaXZlcnMvZ3B1L2RybS9hcm0vbWFsaWRwX3JlZ3MuaAorKysgYi9kcml2ZXJzL2dwdS9k cm0vYXJtL21hbGlkcF9yZWdzLmgKQEAgLTY0LDYgKzY0LDggQEAKIC8qIGJpdCBtYXNrcyB0aGF0 IGFyZSBjb21tb24gYmV0d2VlbiBwcm9kdWN0cyAqLwogI2RlZmluZSAgIE1BTElEUF9DRkdfVkFM SUQJCSgxIDw8IDApCiAjZGVmaW5lICAgTUFMSURQX0RJU1BfRlVOQ19JTEFDRUQJKDEgPDwgOCkK KyNkZWZpbmUgICBNQUxJRFBfU0NBTEVfRU5HSU5FX0VOCSgxIDw8IDE2KQorI2RlZmluZSAgIE1B TElEUF9TRV9NRU1XUklURV9FTgkJKDIgPDwgNSkKIAogLyogcmVnaXN0ZXIgb2Zmc2V0cyBmb3Ig SVJRIG1hbmFnZW1lbnQgKi8KICNkZWZpbmUgTUFMSURQX1JFR19TVEFUVVMJCTB4MDAwMDAKQEAg LTkyLDYgKzk0LDE1IEBACiAjZGVmaW5lIE1BTElEUF9ERV9IX0FDVElWRSh4KQkJKCgoeCkgJiAw eDFmZmYpIDw8IDApCiAjZGVmaW5lIE1BTElEUF9ERV9WX0FDVElWRSh4KQkJKCgoeCkgJiAweDFm ZmYpIDw8IDE2KQogCisvKiByZWdpc3RlciBvZmZzZXRzIHJlbGF0aXZlIHRvIE1BTElEUDV4MF9T RV9NRU1XUklURV9CQVNFICovCisjZGVmaW5lIE1BTElEUF9NV19GT1JNQVQJCTB4MDAwMDAKKyNk ZWZpbmUgTUFMSURQX01XX1AxX1NUUklERQkJMHgwMDAwNAorI2RlZmluZSBNQUxJRFBfTVdfUDJf U1RSSURFCQkweDAwMDA4CisjZGVmaW5lIE1BTElEUF9NV19QMV9QVFJfTE9XCQkweDAwMDBjCisj ZGVmaW5lIE1BTElEUF9NV19QMV9QVFJfSElHSAkJMHgwMDAxMAorI2RlZmluZSBNQUxJRFBfTVdf UDJfUFRSX0xPVwkJMHgwMDAyYworI2RlZmluZSBNQUxJRFBfTVdfUDJfUFRSX0hJR0gJCTB4MDAw MzAKKwogLyogcmVnaXN0ZXIgb2Zmc2V0cyBhbmQgYml0cyBzcGVjaWZpYyB0byBEUDUwMCAqLwog I2RlZmluZSBNQUxJRFA1MDBfRENfQkFTRQkJMHgwMDAwMAogI2RlZmluZSBNQUxJRFA1MDBfRENf Q09OVFJPTAkJMHgwMDAwYwpAQCAtMTQ5LDYgKzE2MCwxMCBAQAogI2RlZmluZSBNQUxJRFA1NTBf REVfTFNfUFRSX0JBU0UJMHgwMDQyYwogI2RlZmluZSBNQUxJRFA1NTBfREVfUEVSRl9CQVNFCQkw eDAwNTAwCiAjZGVmaW5lIE1BTElEUDU1MF9TRV9CQVNFCQkweDA4MDAwCisjZGVmaW5lIE1BTElE UDU1MF9TRV9DT05UUk9MCQkweDA4MDEwCisjZGVmaW5lICAgTUFMSURQNTUwX1NFX01FTVdSSVRF X09ORVNIT1QJKDEgPDwgNykKKyNkZWZpbmUgTUFMSURQNTUwX1NFX01FTVdSSVRFX09VVF9TSVpF CTB4MDgwMzAKKyNkZWZpbmUgTUFMSURQNTUwX1NFX01FTVdSSVRFX0JBU0UJMHgwODEwMAogI2Rl ZmluZSBNQUxJRFA1NTBfRENfQkFTRQkJMHgwYzAwMAogI2RlZmluZSBNQUxJRFA1NTBfRENfQ09O VFJPTAkJMHgwYzAxMAogI2RlZmluZSAgIE1BTElEUDU1MF9EQ19DT05GSUdfUkVRCSgxIDw8IDE2 KQotLSAKMS43LjkuNQoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Au b3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRl dmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from foss.arm.com ([217.140.101.70]:51174 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932599AbcKYQt3 (ORCPT ); Fri, 25 Nov 2016 11:49:29 -0500 From: Brian Starkey To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: linux-media@vger.kernel.org, daniel@ffwll.ch, gustavo@padovan.org, laurent.pinchart@ideasonboard.com, eric@anholt.net, ville.syrjala@linux.intel.com, liviu.dudau@arm.com, Liviu Dudau Subject: [PATCH 4/6] drm: mali-dp: Add support for writeback on DP550/DP650 Date: Fri, 25 Nov 2016 16:49:02 +0000 Message-Id: <1480092544-1725-5-git-send-email-brian.starkey@arm.com> In-Reply-To: <1480092544-1725-1-git-send-email-brian.starkey@arm.com> References: <1480092544-1725-1-git-send-email-brian.starkey@arm.com> Sender: linux-media-owner@vger.kernel.org List-ID: From: Liviu Dudau Mali-DP display processors are able to write the composition result to a memory buffer via the SE. Add entry points in the HAL for enabling/disabling this feature, and implement support for it on DP650 and DP550. DP500 acts differently and so is omitted from this change. Signed-off-by: Liviu Dudau Signed-off-by: Brian Starkey --- drivers/gpu/drm/arm/malidp_hw.c | 52 +++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/arm/malidp_hw.h | 18 +++++++++++++ drivers/gpu/drm/arm/malidp_regs.h | 15 +++++++++++ 3 files changed, 83 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index 9ec6d69..c696e67 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -384,6 +384,48 @@ static int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 return w * bytes_per_col; } +static int malidp550_enable_memwrite(struct malidp_hw_device *hwdev, + dma_addr_t *addrs, s32 *pitches, + int num_planes, u16 w, u16 h, u32 fmt_id) +{ + u32 base = MALIDP550_SE_MEMWRITE_BASE; + u32 de_base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); + + /* enable the scaling engine block */ + malidp_hw_setbits(hwdev, MALIDP_SCALE_ENGINE_EN, de_base + MALIDP_DE_DISPLAY_FUNC); + + malidp_hw_write(hwdev, fmt_id, base + MALIDP_MW_FORMAT); + switch (num_planes) { + case 2: + malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW); + malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH); + malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE); + /* fall through */ + case 1: + malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW); + malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH); + malidp_hw_write(hwdev, pitches[0], base + MALIDP_MW_P1_STRIDE); + break; + default: + WARN(1, "Invalid number of planes"); + } + + malidp_hw_write(hwdev, MALIDP_DE_H_ACTIVE(w) | MALIDP_DE_V_ACTIVE(h), + MALIDP550_SE_MEMWRITE_OUT_SIZE); + malidp_hw_setbits(hwdev, MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_EN, + MALIDP550_SE_CONTROL); + + return 0; +} + +static void malidp550_disable_memwrite(struct malidp_hw_device *hwdev) +{ + u32 base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); + malidp_hw_clearbits(hwdev, MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_EN, + MALIDP550_SE_CONTROL); + malidp_hw_clearbits(hwdev, MALIDP_SCALE_ENGINE_EN, base + MALIDP_DE_DISPLAY_FUNC); +} + static int malidp650_query_hw(struct malidp_hw_device *hwdev) { u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID); @@ -466,7 +508,8 @@ static int malidp650_query_hw(struct malidp_hw_device *hwdev) MALIDP550_SE_IRQ_AXI_ERR, }, .dc_irq_map = { - .irq_mask = MALIDP550_DC_IRQ_CONF_VALID, + .irq_mask = MALIDP550_DC_IRQ_CONF_VALID | + MALIDP550_DC_IRQ_SE, .vsync_irq = MALIDP550_DC_IRQ_CONF_VALID, }, .pixel_formats = malidp550_de_formats, @@ -480,6 +523,8 @@ static int malidp650_query_hw(struct malidp_hw_device *hwdev) .set_config_valid = malidp550_set_config_valid, .modeset = malidp550_modeset, .rotmem_required = malidp550_rotmem_required, + .enable_memwrite = malidp550_enable_memwrite, + .disable_memwrite = malidp550_disable_memwrite, }, [MALIDP_650] = { .map = { @@ -500,7 +545,8 @@ static int malidp650_query_hw(struct malidp_hw_device *hwdev) MALIDP550_SE_IRQ_AXI_ERR, }, .dc_irq_map = { - .irq_mask = MALIDP550_DC_IRQ_CONF_VALID, + .irq_mask = MALIDP550_DC_IRQ_CONF_VALID | + MALIDP550_DC_IRQ_SE, .vsync_irq = MALIDP550_DC_IRQ_CONF_VALID, }, .pixel_formats = malidp550_de_formats, @@ -514,6 +560,8 @@ static int malidp650_query_hw(struct malidp_hw_device *hwdev) .set_config_valid = malidp550_set_config_valid, .modeset = malidp550_modeset, .rotmem_required = malidp550_rotmem_required, + .enable_memwrite = malidp550_enable_memwrite, + .disable_memwrite = malidp550_disable_memwrite, }, }; diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h index 4f8c884..091171d 100644 --- a/drivers/gpu/drm/arm/malidp_hw.h +++ b/drivers/gpu/drm/arm/malidp_hw.h @@ -146,6 +146,24 @@ struct malidp_hw_device { */ int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt); + /** + * Enable writing to memory the content of the next frame + * @param hwdev - malidp_hw_device structure containing the HW description + * @param addrs - array of addresses for each plane + * @param pitches - array of pitches for each plane + * @param num_planes - number of planes to be written + * @param w - width of the output frame + * @param h - height of the output frame + * @param fmt_id - internal format ID of output buffer + */ + int (*enable_memwrite)(struct malidp_hw_device *hwdev, dma_addr_t *addrs, + s32 *pitches, int num_planes, u16 w, u16 h, u32 fmt_id); + + /* + * Disable the writing to memory of the next frame's content. + */ + void (*disable_memwrite)(struct malidp_hw_device *hwdev); + u8 features; u8 min_line_size; diff --git a/drivers/gpu/drm/arm/malidp_regs.h b/drivers/gpu/drm/arm/malidp_regs.h index 73fecb3..cab086c 100644 --- a/drivers/gpu/drm/arm/malidp_regs.h +++ b/drivers/gpu/drm/arm/malidp_regs.h @@ -64,6 +64,8 @@ /* bit masks that are common between products */ #define MALIDP_CFG_VALID (1 << 0) #define MALIDP_DISP_FUNC_ILACED (1 << 8) +#define MALIDP_SCALE_ENGINE_EN (1 << 16) +#define MALIDP_SE_MEMWRITE_EN (2 << 5) /* register offsets for IRQ management */ #define MALIDP_REG_STATUS 0x00000 @@ -92,6 +94,15 @@ #define MALIDP_DE_H_ACTIVE(x) (((x) & 0x1fff) << 0) #define MALIDP_DE_V_ACTIVE(x) (((x) & 0x1fff) << 16) +/* register offsets relative to MALIDP5x0_SE_MEMWRITE_BASE */ +#define MALIDP_MW_FORMAT 0x00000 +#define MALIDP_MW_P1_STRIDE 0x00004 +#define MALIDP_MW_P2_STRIDE 0x00008 +#define MALIDP_MW_P1_PTR_LOW 0x0000c +#define MALIDP_MW_P1_PTR_HIGH 0x00010 +#define MALIDP_MW_P2_PTR_LOW 0x0002c +#define MALIDP_MW_P2_PTR_HIGH 0x00030 + /* register offsets and bits specific to DP500 */ #define MALIDP500_DC_BASE 0x00000 #define MALIDP500_DC_CONTROL 0x0000c @@ -149,6 +160,10 @@ #define MALIDP550_DE_LS_PTR_BASE 0x0042c #define MALIDP550_DE_PERF_BASE 0x00500 #define MALIDP550_SE_BASE 0x08000 +#define MALIDP550_SE_CONTROL 0x08010 +#define MALIDP550_SE_MEMWRITE_ONESHOT (1 << 7) +#define MALIDP550_SE_MEMWRITE_OUT_SIZE 0x08030 +#define MALIDP550_SE_MEMWRITE_BASE 0x08100 #define MALIDP550_DC_BASE 0x0c000 #define MALIDP550_DC_CONTROL 0x0c010 #define MALIDP550_DC_CONFIG_REQ (1 << 16) -- 1.7.9.5