diff for duplicates of <1480604901.4751.17.camel@redhat.com> diff --git a/a/1.txt b/N1/1.txt index 81b300e..04bcb98 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -13,37 +13,37 @@ On Wed, 2016-11-30 at 15:42 -0800, Duc Dang wrote: > Signed-off-by: Duc Dang <dhdang@apm.com> > --- > v3: -> - Rebase on top of pci/ecam-v6 tree. -> - Use DEFINE_RES_MEM_NAMED to declare controller register space -> with name "PCIe CSR" +> ? - Rebase on top of pci/ecam-v6 tree. +> ? - Use DEFINE_RES_MEM_NAMED to declare controller register space +> ? with name "PCIe CSR" > v2: -> RFC v2: https://patchwork.ozlabs.org/patch/686846/ +> ? RFC v2: https://patchwork.ozlabs.org/patch/686846/ > v1: -> RFC v1: https://patchwork.kernel.org/patch/9337115/ +> ? RFC v1: https://patchwork.kernel.org/patch/9337115/ > -> drivers/acpi/pci_mcfg.c | 31 ++++++++ -> drivers/pci/host/pci-xgene.c | 165 ++++++++++++++++++++++++++++++++++++++++++- -> include/linux/pci-ecam.h | 7 ++ -> 3 files changed, 200 insertions(+), 3 deletions(-) +> ?drivers/acpi/pci_mcfg.c??????|??31 ++++++++ +> ?drivers/pci/host/pci-xgene.c | 165 ++++++++++++++++++++++++++++++++++++++++++- +> ?include/linux/pci-ecam.h?????|???7 ++ +> ?3 files changed, 200 insertions(+), 3 deletions(-) > > diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c > index ac21db3..eb6125b 100644 > --- a/drivers/acpi/pci_mcfg.c > +++ b/drivers/acpi/pci_mcfg.c > @@ -57,6 +57,37 @@ struct mcfg_fixup { -> { "QCOM ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, &pci_32b_ops }, -> { "QCOM ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, &pci_32b_ops }, -> { "QCOM ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, &pci_32b_ops }, +> ? { "QCOM??", "QDF2432 ", 1, 5, MCFG_BUS_ANY, &pci_32b_ops }, +> ? { "QCOM??", "QDF2432 ", 1, 6, MCFG_BUS_ANY, &pci_32b_ops }, +> ? { "QCOM??", "QDF2432 ", 1, 7, MCFG_BUS_ANY, &pci_32b_ops }, > + > +#ifdef CONFIG_PCI_XGENE > +#define XGENE_V1_ECAM_MCFG(rev, seg) \ -> + {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \ +> + {"APM???", "XGENE???", rev, seg, MCFG_BUS_ANY, \ > + &xgene_v1_pcie_ecam_ops } > +#define XGENE_V2_1_ECAM_MCFG(rev, seg) \ -> + {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \ +> + {"APM???", "XGENE???", rev, seg, MCFG_BUS_ANY, \ > + &xgene_v2_1_pcie_ecam_ops } > +#define XGENE_V2_2_ECAM_MCFG(rev, seg) \ -> + {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \ +> + {"APM???", "XGENE???", rev, seg, MCFG_BUS_ANY, \ > + &xgene_v2_2_pcie_ecam_ops } > + > + /* X-Gene SoC with v1 PCIe controller */ @@ -65,34 +65,34 @@ On Wed, 2016-11-30 at 15:42 -0800, Duc Dang wrote: > + XGENE_V2_2_ECAM_MCFG(4, 1), > + XGENE_V2_2_ECAM_MCFG(4, 2), > +#endif -> }; -> -> static char mcfg_oem_id[ACPI_OEM_ID_SIZE]; +> ?}; +> ? +> ?static char mcfg_oem_id[ACPI_OEM_ID_SIZE]; > diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c > index 1de23d7..43d7c69 100644 > --- a/drivers/pci/host/pci-xgene.c > +++ b/drivers/pci/host/pci-xgene.c > @@ -27,6 +27,8 @@ -> #include <linux/of_irq.h> -> #include <linux/of_pci.h> -> #include <linux/pci.h> +> ?#include <linux/of_irq.h> +> ?#include <linux/of_pci.h> +> ?#include <linux/pci.h> > +#include <linux/pci-acpi.h> > +#include <linux/pci-ecam.h> -> #include <linux/platform_device.h> -> #include <linux/slab.h> -> +> ?#include <linux/platform_device.h> +> ?#include <linux/slab.h> +> ? > @@ -64,6 +66,7 @@ -> /* PCIe IP version */ -> #define XGENE_PCIE_IP_VER_UNKN 0 -> #define XGENE_PCIE_IP_VER_1 1 +> ?/* PCIe IP version */ +> ?#define XGENE_PCIE_IP_VER_UNKN 0 +> ?#define XGENE_PCIE_IP_VER_1 1 > +#define XGENE_PCIE_IP_VER_2 2 -> -> struct xgene_pcie_port { -> struct device_node *node; +> ? +> ?struct xgene_pcie_port { +> ? struct device_node *node; > @@ -97,7 +100,15 @@ static inline u32 pcie_bar_low_val(u32 addr, u32 flags) -> */ -> static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus) -> { +> ? */ +> ?static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus) +> ?{ > - struct xgene_pcie_port *port = bus->sysdata; > + struct pci_config_window *cfg; > + struct xgene_pcie_port *port; @@ -103,19 +103,19 @@ On Wed, 2016-11-30 at 15:42 -0800, Duc Dang wrote: > + cfg = bus->sysdata; > + port = cfg->priv; > + } -> -> if (bus->number >= (bus->primary + 1)) -> return port->cfg_base + AXI_EP_CFG_ACCESS; +> ? +> ? if (bus->number >= (bus->primary + 1)) +> ? return port->cfg_base + AXI_EP_CFG_ACCESS; > @@ -111,10 +122,18 @@ static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus) -> */ -> static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn) -> { +> ? */ +> ?static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn) +> ?{ > - struct xgene_pcie_port *port = bus->sysdata; > + struct pci_config_window *cfg; > + struct xgene_pcie_port *port; -> unsigned int b, d, f; -> u32 rtdid_val = 0; -> +> ? unsigned int b, d, f; +> ? u32 rtdid_val = 0; +> ? > + if (acpi_disabled) > + port = bus->sysdata; > + else { @@ -123,13 +123,13 @@ On Wed, 2016-11-30 at 15:42 -0800, Duc Dang wrote: > + port = cfg->priv; > + } > + -> b = bus->number; -> d = PCI_SLOT(devfn); -> f = PCI_FUNC(devfn); +> ? b = bus->number; +> ? d = PCI_SLOT(devfn); +> ? f = PCI_FUNC(devfn); > @@ -158,7 +177,15 @@ static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, -> static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, -> int where, int size, u32 *val) -> { +> ?static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, +> ? ????int where, int size, u32 *val) +> ?{ > - struct xgene_pcie_port *port = bus->sysdata; > + struct pci_config_window *cfg; > + struct xgene_pcie_port *port; @@ -140,13 +140,13 @@ On Wed, 2016-11-30 at 15:42 -0800, Duc Dang wrote: > + cfg = bus->sysdata; > + port = cfg->priv; > + } -> -> if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) != -> PCIBIOS_SUCCESSFUL) +> ? +> ? if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) != +> ? ????PCIBIOS_SUCCESSFUL) > @@ -189,6 +216,138 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, -> .write = pci_generic_config_write32, -> }; -> +> ? .write = pci_generic_config_write32, +> ?}; +> ? > +#ifdef CONFIG_ACPI > +static struct resource xgene_v1_csr_res[] = { > + [0] = DEFINE_RES_MEM_NAMED(0x1f2b0000UL, SZ_64K, "PCIe CSR"), @@ -188,12 +188,12 @@ for m400 where segment 0 is using controller 3. > +} > + > +struct pci_ecam_ops xgene_v1_pcie_ecam_ops = { -> + .bus_shift = 16, -> + .init = xgene_v1_pcie_ecam_init, -> + .pci_ops = { -> + .map_bus = xgene_pcie_map_bus, -> + .read = xgene_pcie_config_read32, -> + .write = pci_generic_config_write, +> + .bus_shift??????= 16, +> + .init???????????= xgene_v1_pcie_ecam_init, +> + .pci_ops????????= { +> + .map_bus????????= xgene_pcie_map_bus, +> + .read???????????= xgene_pcie_config_read32, +> + .write??????????= pci_generic_config_write, > + } > +}; > + @@ -230,12 +230,12 @@ for m400 where segment 0 is using controller 3. > +} > + > +struct pci_ecam_ops xgene_v2_1_pcie_ecam_ops = { -> + .bus_shift = 16, -> + .init = xgene_v2_1_pcie_ecam_init, -> + .pci_ops = { -> + .map_bus = xgene_pcie_map_bus, -> + .read = xgene_pcie_config_read32, -> + .write = pci_generic_config_write, +> + .bus_shift??????= 16, +> + .init???????????= xgene_v2_1_pcie_ecam_init, +> + .pci_ops????????= { +> + .map_bus????????= xgene_pcie_map_bus, +> + .read???????????= xgene_pcie_config_read32, +> + .write??????????= pci_generic_config_write, > + } > +}; > + @@ -273,27 +273,27 @@ for m400 where segment 0 is using controller 3. > +} > + > +struct pci_ecam_ops xgene_v2_2_pcie_ecam_ops = { -> + .bus_shift = 16, -> + .init = xgene_v2_2_pcie_ecam_init, -> + .pci_ops = { -> + .map_bus = xgene_pcie_map_bus, -> + .read = xgene_pcie_config_read32, -> + .write = pci_generic_config_write, +> + .bus_shift??????= 16, +> + .init???????????= xgene_v2_2_pcie_ecam_init, +> + .pci_ops????????= { +> + .map_bus????????= xgene_pcie_map_bus, +> + .read???????????= xgene_pcie_config_read32, +> + .write??????????= pci_generic_config_write, > + } > +}; > +#endif > + -> static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr, -> u32 flags, u64 size) -> { +> ?static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr, +> ? ??u32 flags, u64 size) +> ?{ > diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h > index f5740b7..47ab947 100644 > --- a/include/linux/pci-ecam.h > +++ b/include/linux/pci-ecam.h > @@ -62,6 +62,13 @@ void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn, -> /* ops for buggy ECAM that supports only 32-bit accesses */ -> extern struct pci_ecam_ops pci_32b_ops; -> +> ?/* ops for buggy ECAM that supports only 32-bit accesses */ +> ?extern struct pci_ecam_ops pci_32b_ops; +> ? > +/* ECAM ops for known quirks */ > +#ifdef CONFIG_PCI_XGENE > +extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops; @@ -301,6 +301,6 @@ for m400 where segment 0 is using controller 3. > +extern struct pci_ecam_ops xgene_v2_2_pcie_ecam_ops; > +#endif > + -> #ifdef CONFIG_PCI_HOST_GENERIC -> /* for DT-based PCI controllers that support ECAM */ -> int pci_host_common_probe(struct platform_device *pdev, +> ?#ifdef CONFIG_PCI_HOST_GENERIC +> ?/* for DT-based PCI controllers that support ECAM */ +> ?int pci_host_common_probe(struct platform_device *pdev, diff --git a/a/content_digest b/N1/content_digest index fa340ed..42699d0 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,18 +1,8 @@ "ref\01480549373-2123-1-git-send-email-dhdang@apm.com\0" - "From\0Mark Salter <msalter@redhat.com>\0" - "Subject\0Re: [PATCH v3] PCI/ACPI: xgene: Add ECAM quirk for X-Gene PCIe controller\0" + "From\0msalter@redhat.com (Mark Salter)\0" + "Subject\0[PATCH v3] PCI/ACPI: xgene: Add ECAM quirk for X-Gene PCIe controller\0" "Date\0Thu, 01 Dec 2016 10:08:21 -0500\0" - "To\0Duc Dang <dhdang@apm.com>" - " Bjorn Helgaas <helgaas@kernel.org>\0" - "Cc\0Rafael Wysocki <rafael@kernel.org>" - Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com> - Arnd Bergmann <arnd@arndb.de> - linux-pci@vger.kernel.org - linux-arm <linux-arm-kernel@lists.infradead.org> - Linux Kernel Mailing List <linux-kernel@vger.kernel.org> - Jon Masters <jcm@redhat.com> - Tomasz Nowicki <tn@semihalf.com> - " patches <patches@apm.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Wed, 2016-11-30 at 15:42 -0800, Duc Dang wrote:\n" @@ -30,37 +20,37 @@ "> Signed-off-by: Duc Dang <dhdang@apm.com>\n" "> ---\n" "> v3:\n" - "> \302\240 - Rebase on top of pci/ecam-v6 tree.\n" - "> \302\240 - Use DEFINE_RES_MEM_NAMED to declare controller register space\n" - "> \302\240 with name \"PCIe CSR\"\n" + "> ? - Rebase on top of pci/ecam-v6 tree.\n" + "> ? - Use DEFINE_RES_MEM_NAMED to declare controller register space\n" + "> ? with name \"PCIe CSR\"\n" "> v2:\n" - "> \302\240 RFC v2: https://patchwork.ozlabs.org/patch/686846/\n" + "> ? RFC v2: https://patchwork.ozlabs.org/patch/686846/\n" "> v1:\n" - "> \302\240 RFC v1: https://patchwork.kernel.org/patch/9337115/\n" + "> ? RFC v1: https://patchwork.kernel.org/patch/9337115/\n" "> \n" - "> \302\240drivers/acpi/pci_mcfg.c\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\24031 ++++++++\n" - "> \302\240drivers/pci/host/pci-xgene.c | 165 ++++++++++++++++++++++++++++++++++++++++++-\n" - "> \302\240include/linux/pci-ecam.h\302\240\302\240\302\240\302\240\302\240|\302\240\302\240\302\2407 ++\n" - "> \302\2403 files changed, 200 insertions(+), 3 deletions(-)\n" + "> ?drivers/acpi/pci_mcfg.c??????|??31 ++++++++\n" + "> ?drivers/pci/host/pci-xgene.c | 165 ++++++++++++++++++++++++++++++++++++++++++-\n" + "> ?include/linux/pci-ecam.h?????|???7 ++\n" + "> ?3 files changed, 200 insertions(+), 3 deletions(-)\n" "> \n" "> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c\n" "> index ac21db3..eb6125b 100644\n" "> --- a/drivers/acpi/pci_mcfg.c\n" "> +++ b/drivers/acpi/pci_mcfg.c\n" "> @@ -57,6 +57,37 @@ struct mcfg_fixup {\n" - "> \302\240\t{ \"QCOM\302\240\302\240\", \"QDF2432 \", 1, 5, MCFG_BUS_ANY, &pci_32b_ops },\n" - "> \302\240\t{ \"QCOM\302\240\302\240\", \"QDF2432 \", 1, 6, MCFG_BUS_ANY, &pci_32b_ops },\n" - "> \302\240\t{ \"QCOM\302\240\302\240\", \"QDF2432 \", 1, 7, MCFG_BUS_ANY, &pci_32b_ops },\n" + "> ?\t{ \"QCOM??\", \"QDF2432 \", 1, 5, MCFG_BUS_ANY, &pci_32b_ops },\n" + "> ?\t{ \"QCOM??\", \"QDF2432 \", 1, 6, MCFG_BUS_ANY, &pci_32b_ops },\n" + "> ?\t{ \"QCOM??\", \"QDF2432 \", 1, 7, MCFG_BUS_ANY, &pci_32b_ops },\n" "> +\n" "> +#ifdef CONFIG_PCI_XGENE\n" "> +#define XGENE_V1_ECAM_MCFG(rev, seg) \\\n" - "> +\t{\"APM\302\240\302\240\302\240\", \"XGENE\302\240\302\240\302\240\", rev, seg, MCFG_BUS_ANY, \\\n" + "> +\t{\"APM???\", \"XGENE???\", rev, seg, MCFG_BUS_ANY, \\\n" "> +\t\t&xgene_v1_pcie_ecam_ops }\n" "> +#define XGENE_V2_1_ECAM_MCFG(rev, seg) \\\n" - "> +\t{\"APM\302\240\302\240\302\240\", \"XGENE\302\240\302\240\302\240\", rev, seg, MCFG_BUS_ANY, \\\n" + "> +\t{\"APM???\", \"XGENE???\", rev, seg, MCFG_BUS_ANY, \\\n" "> +\t\t&xgene_v2_1_pcie_ecam_ops }\n" "> +#define XGENE_V2_2_ECAM_MCFG(rev, seg) \\\n" - "> +\t{\"APM\302\240\302\240\302\240\", \"XGENE\302\240\302\240\302\240\", rev, seg, MCFG_BUS_ANY, \\\n" + "> +\t{\"APM???\", \"XGENE???\", rev, seg, MCFG_BUS_ANY, \\\n" "> +\t\t&xgene_v2_2_pcie_ecam_ops }\n" "> +\n" "> +\t/* X-Gene SoC with v1 PCIe controller */\n" @@ -82,34 +72,34 @@ "> +\tXGENE_V2_2_ECAM_MCFG(4, 1),\n" "> +\tXGENE_V2_2_ECAM_MCFG(4, 2),\n" "> +#endif\n" - "> \302\240};\n" - "> \302\240\n" - "> \302\240static char mcfg_oem_id[ACPI_OEM_ID_SIZE];\n" + "> ?};\n" + "> ?\n" + "> ?static char mcfg_oem_id[ACPI_OEM_ID_SIZE];\n" "> diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c\n" "> index 1de23d7..43d7c69 100644\n" "> --- a/drivers/pci/host/pci-xgene.c\n" "> +++ b/drivers/pci/host/pci-xgene.c\n" "> @@ -27,6 +27,8 @@\n" - "> \302\240#include <linux/of_irq.h>\n" - "> \302\240#include <linux/of_pci.h>\n" - "> \302\240#include <linux/pci.h>\n" + "> ?#include <linux/of_irq.h>\n" + "> ?#include <linux/of_pci.h>\n" + "> ?#include <linux/pci.h>\n" "> +#include <linux/pci-acpi.h>\n" "> +#include <linux/pci-ecam.h>\n" - "> \302\240#include <linux/platform_device.h>\n" - "> \302\240#include <linux/slab.h>\n" - "> \302\240\n" + "> ?#include <linux/platform_device.h>\n" + "> ?#include <linux/slab.h>\n" + "> ?\n" "> @@ -64,6 +66,7 @@\n" - "> \302\240/* PCIe IP version */\n" - "> \302\240#define XGENE_PCIE_IP_VER_UNKN\t\t0\n" - "> \302\240#define XGENE_PCIE_IP_VER_1\t\t1\n" + "> ?/* PCIe IP version */\n" + "> ?#define XGENE_PCIE_IP_VER_UNKN\t\t0\n" + "> ?#define XGENE_PCIE_IP_VER_1\t\t1\n" "> +#define XGENE_PCIE_IP_VER_2\t\t2\n" - "> \302\240\n" - "> \302\240struct xgene_pcie_port {\n" - "> \302\240\tstruct device_node\t*node;\n" + "> ?\n" + "> ?struct xgene_pcie_port {\n" + "> ?\tstruct device_node\t*node;\n" "> @@ -97,7 +100,15 @@ static inline u32 pcie_bar_low_val(u32 addr, u32 flags)\n" - "> \302\240 */\n" - "> \302\240static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)\n" - "> \302\240{\n" + "> ? */\n" + "> ?static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)\n" + "> ?{\n" "> -\tstruct xgene_pcie_port *port = bus->sysdata;\n" "> +\tstruct pci_config_window *cfg;\n" "> +\tstruct xgene_pcie_port *port;\n" @@ -120,19 +110,19 @@ "> +\t\tcfg = bus->sysdata;\n" "> +\t\tport = cfg->priv;\n" "> +\t}\n" - "> \302\240\n" - "> \302\240\tif (bus->number >= (bus->primary + 1))\n" - "> \302\240\t\treturn port->cfg_base + AXI_EP_CFG_ACCESS;\n" + "> ?\n" + "> ?\tif (bus->number >= (bus->primary + 1))\n" + "> ?\t\treturn port->cfg_base + AXI_EP_CFG_ACCESS;\n" "> @@ -111,10 +122,18 @@ static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)\n" - "> \302\240 */\n" - "> \302\240static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)\n" - "> \302\240{\n" + "> ? */\n" + "> ?static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)\n" + "> ?{\n" "> -\tstruct xgene_pcie_port *port = bus->sysdata;\n" "> +\tstruct pci_config_window *cfg;\n" "> +\tstruct xgene_pcie_port *port;\n" - "> \302\240\tunsigned int b, d, f;\n" - "> \302\240\tu32 rtdid_val = 0;\n" - "> \302\240\n" + "> ?\tunsigned int b, d, f;\n" + "> ?\tu32 rtdid_val = 0;\n" + "> ?\n" "> +\tif (acpi_disabled)\n" "> +\t\tport = bus->sysdata;\n" "> +\telse {\n" @@ -140,13 +130,13 @@ "> +\t\tport = cfg->priv;\n" "> +\t}\n" "> +\n" - "> \302\240\tb = bus->number;\n" - "> \302\240\td = PCI_SLOT(devfn);\n" - "> \302\240\tf = PCI_FUNC(devfn);\n" + "> ?\tb = bus->number;\n" + "> ?\td = PCI_SLOT(devfn);\n" + "> ?\tf = PCI_FUNC(devfn);\n" "> @@ -158,7 +177,15 @@ static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,\n" - "> \302\240static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,\n" - "> \302\240\t\t\t\t\302\240\302\240\302\240\302\240int where, int size, u32 *val)\n" - "> \302\240{\n" + "> ?static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,\n" + "> ?\t\t\t\t????int where, int size, u32 *val)\n" + "> ?{\n" "> -\tstruct xgene_pcie_port *port = bus->sysdata;\n" "> +\tstruct pci_config_window *cfg;\n" "> +\tstruct xgene_pcie_port *port;\n" @@ -157,13 +147,13 @@ "> +\t\tcfg = bus->sysdata;\n" "> +\t\tport = cfg->priv;\n" "> +\t}\n" - "> \302\240\n" - "> \302\240\tif (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=\n" - "> \302\240\t\302\240\302\240\302\240\302\240PCIBIOS_SUCCESSFUL)\n" + "> ?\n" + "> ?\tif (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=\n" + "> ?\t????PCIBIOS_SUCCESSFUL)\n" "> @@ -189,6 +216,138 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,\n" - "> \302\240\t.write = pci_generic_config_write32,\n" - "> \302\240};\n" - "> \302\240\n" + "> ?\t.write = pci_generic_config_write32,\n" + "> ?};\n" + "> ?\n" "> +#ifdef CONFIG_ACPI\n" "> +static struct resource xgene_v1_csr_res[] = {\n" "> +\t[0] = DEFINE_RES_MEM_NAMED(0x1f2b0000UL, SZ_64K, \"PCIe CSR\"),\n" @@ -205,12 +195,12 @@ "> +}\n" "> +\n" "> +struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {\n" - "> +\t.bus_shift\302\240\302\240\302\240\302\240\302\240\302\240= 16,\n" - "> +\t.init\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= xgene_v1_pcie_ecam_init,\n" - "> +\t.pci_ops\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= {\n" - "> +\t\t.map_bus\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= xgene_pcie_map_bus,\n" - "> +\t\t.read\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= xgene_pcie_config_read32,\n" - "> +\t\t.write\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= pci_generic_config_write,\n" + "> +\t.bus_shift??????= 16,\n" + "> +\t.init???????????= xgene_v1_pcie_ecam_init,\n" + "> +\t.pci_ops????????= {\n" + "> +\t\t.map_bus????????= xgene_pcie_map_bus,\n" + "> +\t\t.read???????????= xgene_pcie_config_read32,\n" + "> +\t\t.write??????????= pci_generic_config_write,\n" "> +\t}\n" "> +};\n" "> +\n" @@ -247,12 +237,12 @@ "> +}\n" "> +\n" "> +struct pci_ecam_ops xgene_v2_1_pcie_ecam_ops = {\n" - "> +\t.bus_shift\302\240\302\240\302\240\302\240\302\240\302\240= 16,\n" - "> +\t.init\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= xgene_v2_1_pcie_ecam_init,\n" - "> +\t.pci_ops\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= {\n" - "> +\t\t.map_bus\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= xgene_pcie_map_bus,\n" - "> +\t\t.read\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= xgene_pcie_config_read32,\n" - "> +\t\t.write\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= pci_generic_config_write,\n" + "> +\t.bus_shift??????= 16,\n" + "> +\t.init???????????= xgene_v2_1_pcie_ecam_init,\n" + "> +\t.pci_ops????????= {\n" + "> +\t\t.map_bus????????= xgene_pcie_map_bus,\n" + "> +\t\t.read???????????= xgene_pcie_config_read32,\n" + "> +\t\t.write??????????= pci_generic_config_write,\n" "> +\t}\n" "> +};\n" "> +\n" @@ -290,27 +280,27 @@ "> +}\n" "> +\n" "> +struct pci_ecam_ops xgene_v2_2_pcie_ecam_ops = {\n" - "> +\t.bus_shift\302\240\302\240\302\240\302\240\302\240\302\240= 16,\n" - "> +\t.init\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= xgene_v2_2_pcie_ecam_init,\n" - "> +\t.pci_ops\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= {\n" - "> +\t\t.map_bus\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= xgene_pcie_map_bus,\n" - "> +\t\t.read\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= xgene_pcie_config_read32,\n" - "> +\t\t.write\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240= pci_generic_config_write,\n" + "> +\t.bus_shift??????= 16,\n" + "> +\t.init???????????= xgene_v2_2_pcie_ecam_init,\n" + "> +\t.pci_ops????????= {\n" + "> +\t\t.map_bus????????= xgene_pcie_map_bus,\n" + "> +\t\t.read???????????= xgene_pcie_config_read32,\n" + "> +\t\t.write??????????= pci_generic_config_write,\n" "> +\t}\n" "> +};\n" "> +#endif\n" "> +\n" - "> \302\240static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,\n" - "> \302\240\t\t\t\t\302\240\302\240u32 flags, u64 size)\n" - "> \302\240{\n" + "> ?static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,\n" + "> ?\t\t\t\t??u32 flags, u64 size)\n" + "> ?{\n" "> diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h\n" "> index f5740b7..47ab947 100644\n" "> --- a/include/linux/pci-ecam.h\n" "> +++ b/include/linux/pci-ecam.h\n" "> @@ -62,6 +62,13 @@ void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn,\n" - "> \302\240/* ops for buggy ECAM that supports only 32-bit accesses */\n" - "> \302\240extern struct pci_ecam_ops pci_32b_ops;\n" - "> \302\240\n" + "> ?/* ops for buggy ECAM that supports only 32-bit accesses */\n" + "> ?extern struct pci_ecam_ops pci_32b_ops;\n" + "> ?\n" "> +/* ECAM ops for known quirks */\n" "> +#ifdef CONFIG_PCI_XGENE\n" "> +extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops;\n" @@ -318,8 +308,8 @@ "> +extern struct pci_ecam_ops xgene_v2_2_pcie_ecam_ops;\n" "> +#endif\n" "> +\n" - "> \302\240#ifdef CONFIG_PCI_HOST_GENERIC\n" - "> \302\240/* for DT-based PCI controllers that support ECAM */\n" - "> \302\240int pci_host_common_probe(struct platform_device *pdev," + "> ?#ifdef CONFIG_PCI_HOST_GENERIC\n" + "> ?/* for DT-based PCI controllers that support ECAM */\n" + > ?int pci_host_common_probe(struct platform_device *pdev, -91ef465c05636d623b6f38f248a35cac9b835a90571d76cc6fdb42a27b92bd9f +71ca8cc69d0799496ba4c1ed35339ed80d7ff615b7a25a0c8b67aa2cc99de2df
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