[U-Boot] [PATCH 09/10] arm: socfpga: arria10: Added drivers for Arria10 pin mux/pins configuration

[Chee, Tien Fong <tien.fong.chee@intel.com>]

On Sel, 2016-12-06 at 16:11 +0800, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Tien Fong <skywindctf@gmail.com>
> ---
> ?arch/arm/mach-socfpga/Makefile??????????????|????2 +-
> ?arch/arm/mach-socfpga/include/mach/pinmux.h |???17 +++++
> ?arch/arm/mach-socfpga/pinmux.c??????????????|??104
> +++++++++++++++++++++++++++
> ?3 files changed, 122 insertions(+), 1 deletions(-)
> ?create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
> ?create mode 100644 arch/arm/mach-socfpga/pinmux.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> socfpga/Makefile
> index 71cf31c..1ab68be 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
Any comments on this patch before i start the version 2?

> @@ -10,7 +10,7 @@
> ?obj-y	+= misc.o timer.o reset_manager.o system_manager.o
> clock_manager.o \
> ?	???fpga_manager.o board.o
> ?obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
> misc_arria10.o \
> -				clock_manager_arria10.o
> +				clock_manager_arria10.o pinmux.o
> ?obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o
> wrap_pll_config.o \
> ?				reset_manager_gen5.o misc_gen5.o \
> ?				clock_manager_gen5.o
> diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h
> b/arch/arm/mach-socfpga/include/mach/pinmux.h
> new file mode 100644
> index 0000000..e7d831d
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
> @@ -0,0 +1,17 @@
> +/*
> + * Copyright (C) 2016 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#ifndef	_PINMUX_H_
> +#define	_PINMUX_H_
> +
> +#ifndef __ASSEMBLY__
> +extern int config_dedicated_pins(const void *blob);
> +extern int config_pins(const void *blob, const char *pin_grp);
> +#endif
> +
> +
> +
> +#endif /* _PINMUX_H_ */
> diff --git a/arch/arm/mach-socfpga/pinmux.c b/arch/arm/mach-
> socfpga/pinmux.c
> new file mode 100644
> index 0000000..d45722f
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/pinmux.c
> @@ -0,0 +1,104 @@
> +/*
> + *??Copyright (C) 2016 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <fdtdec.h>
> +#include <asm/arch/pinmux.h>
> +
> +int config_dedicated_pins(const void *blob);
> +int config_pins(const void *blob, const char *pin_grp);
> +static int __do_pinctr_pins(const void *blob, int child, const char
> *node_name);
> +static int do_pinctrl_pins(const void *blob, int node, const char
> *child_name);
> +
> +static int __do_pinctr_pins(const void *blob, int child, const char
> *node_name)
> +{
> +	int len;
> +	fdt_addr_t base_addr;
> +	fdt_size_t size;
> +	const u32 *cell;
> +	u32 offset, value;
> +
> +	base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
> +	if (base_addr != FDT_ADDR_T_NONE) {
> +		cell = fdt_getprop(blob, child, "pinctrl-
> single,pins",
> +			&len);
> +		if (cell != NULL) {
> +			debug("%p %d\n", cell, len);
> +			for (;len > 0; len -= (2*sizeof(u32))) {
> +				offset = fdt32_to_cpu(*cell++);
> +				value = fdt32_to_cpu(*cell++);
> +				debug("<0x%x 0x%x>\n", offset,
> value);
> +				writel(value, base_addr + offset);
> +			}
> +			return 0;
> +		}
> +	}
> +	return 1;
> +}
> +
> +static int do_pinctrl_pins(const void *blob, int node, const char
> *child_name)
> +{
> +	int child, len;
> +	const char *node_name;
> +
> +	child = fdt_first_subnode(blob, node);
> +
> +	if (child < 0)
> +		return 2;
> +
> +	node_name = fdt_get_name(blob, child, &len);
> +
> +	while (node_name) {
> +		if (!strcmp(child_name, node_name)) {
> +			__do_pinctr_pins(blob, child, node_name);
> +			return(0);
> +		}
> +		child = fdt_next_subnode(blob, child);
> +
> +		if (child < 0)
> +			break;
> +
> +		node_name = fdt_get_name(blob, child, &len);
> +	}
> +
> +	return 1;
> +}
> +
> +int config_dedicated_pins(const void *blob)
> +{
> +	int node;
> +
> +	node = fdtdec_next_compatible(blob, 0,
> +			COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
> +
> +	if (node < 0)
> +		return 1;
> +
> +	if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
> +		return 2;
> +
> +	if (do_pinctrl_pins(blob, node, "dedicated"))
> +		return 3;
> +
> +	return 0;
> +}
> +
> +int config_pins(const void *blob, const char *pin_grp)
> +{
> +	int node;
> +
> +	node = fdtdec_next_compatible(blob, 0,
> +			COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
> +
> +	if (node < 0)
> +		return 1;
> +
> +	if (do_pinctrl_pins(blob, node, pin_grp))
> +		return 2;
> +
> +	return 0;
> +}