From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL
Date: Thu, 29 Dec 2016 04:54:38 +0000 [thread overview]
Message-ID: <1482987275.2665.5.camel@intel.com> (raw)
In-Reply-To: <be15237d-4646-8550-08c3-a0ef62a1a10e@denx.de>
On Kha, 2016-12-29 at 00:51 +0100, Marek Vasut wrote:
> On 12/28/2016 07:34 AM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Enhanced defconfig file for Arria10 to enable SPL build and
> > supporting
> > device tree build for SDMMC.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > Cc: Chin Liang See <chin.liang.see@intel.com>
> > Cc: Tien Fong <skywindctf@gmail.com>
> > ---
> > Changes for V2
> > - Removed boot header info setup since it already fixed in mainline
> > ---
> > ?configs/socfpga_arria10_defconfig | 18 +++++++++++++-----
> > ?1 file changed, 13 insertions(+), 5 deletions(-)
> There's no arria10 defconfig in mainline ?
> I only received patches 18/30 and on ?
>
patch1 to patch17 are?01-arria10 rebase on u-boot.git, i believe those
patches not CC to you orginally. Could you get from?U-Boot Digest, Vol
103, Issue 53, or you want me to edit those patches CC to you?
> >
> > diff --git a/configs/socfpga_arria10_defconfig
> > b/configs/socfpga_arria10_defconfig
> > index 422261b..755bb66 100644
> > --- a/configs/socfpga_arria10_defconfig
> > +++ b/configs/socfpga_arria10_defconfig
> > @@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y
> > ?CONFIG_TARGET_SOCFPGA_ARRIA10=y
> > ?CONFIG_DM_GPIO=y
> > ?CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
> > -CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
> > +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
> > +CONFIG_IDENT_STRING="socfpga_arria10"
> > ?# CONFIG_CMD_IMLS is not set
> > ?# CONFIG_CMD_FLASH is not set
> > ?CONFIG_CMD_GPIO=y
> > ?CONFIG_DWAPB_GPIO=y
> > -CONFIG_DM_ETH=y
> > -CONFIG_ETH_DESIGNWARE=y
> > ?CONFIG_SYS_NS16550=y
> > -CONFIG_CADENCE_QSPI=y
> > -CONFIG_DESIGNWARE_SPI=y
> > ?CONFIG_DM_MMC=y
> > +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > +CONFIG_CMD_MMC=y
> > +CONFIG_USE_TINY_PRINTF=y
> > +CONFIG_SPL=y
> > +CONFIG_SPL_DM=y
> > +CONFIG_SPL_SIMPLE_BUS=y
> > +CONFIG_SPL_DM_SEQ_ALIAS=y
> > +CONFIG_SPL_MMC_SUPPORT=y
> > +CONFIG_SPL_SERIAL_SUPPORT=y
> > +CONFIG_SPL_OF_LIBFDT=y
> > +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
> >
>
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next prev parent reply other threads:[~2016-12-29 4:54 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-28 6:34 [U-Boot] [PATCH v2 01/30] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 02/30] arm: socfpga: arria10: add sdram defines " Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 03/30] arm: socfpga: arria10: add board files for the Arria10 SoCDK Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 04/30] arm: socfpga: arria10: add system manager defines Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 05/30] arm: socfpga: arria10: add misc functions for Arria10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 06/30] arm: socfpga: arria10: add socfpga_arria10_socdk config Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 07/30] arm: socfpga: arria10: add socfpga_arria10_defconfig Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 08/30] arm: socfpga: arria10: add config option build for arria10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 09/30] arm: socfpga: add define for bootinfo bsel bit shift Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 10/30] arm: socfpga: arria10: add reset manager for Arria10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 11/30] arm: socfpga: wrap system manager functions for A5/C5 devices Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 12/30] arm: socfpga: arria10: don't build GEN5 sdram for arria10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 13/30] arm: socfpga: arria10 fpga does not have bridges mapped Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 14/30] arm: socfpga: arria10: remove board_init and s_init Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 15/30] arm: socfpga: combine clrbits/setbits into a single clrsetbits Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 16/30] arm: socfpga: add reset manager defines for Arria10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 17/30] arm: socfpga: arria10: update dwmac reset function to support Arria10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 18/30] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 19/30] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 20/30] arm: socfpga: arria10: Enable SPL for Arria 10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL Chee Tien Fong
2016-12-28 23:51 ` Marek Vasut
2016-12-29 4:54 ` Chee, Tien Fong [this message]
2016-12-30 19:04 ` Marek Vasut
2017-01-03 5:38 ` Chee, Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 22/30] arm: socfpga: arria10: Added clock manager and pin mux compat macro Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 23/30] arm: socfpga: arria10: Added some hardware base address for Arria 10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 24/30] arm: socfpga: arria10: Added support for Arria 10 socdk Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 25/30] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 26/30] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 27/30] arm: socfpga: arria10: Added drivers for Arria10 clock manager Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 28/30] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl Chee Tien Fong
2016-12-30 12:14 ` Dinh Nguyen
2017-01-03 5:43 ` Chee, Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 30/30] arm: socfpga: arria10: Enable fpga driver build for SPL Chee Tien Fong
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