diff for duplicates of <1483697496.28003.40.camel@baylibre.com> diff --git a/a/content_digest b/N1/content_digest index a073ca5..a579a7b 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -4,7 +4,7 @@ "From\0jbrunet@baylibre.com (Jerome Brunet)\0" "Subject\0[PATCH net-next v4 0/4] Fix OdroidC2 Gigabit Tx link issue\0" "Date\0Fri, 06 Jan 2017 11:11:36 +0100\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Thu, 2017-01-05 at 23:25 +0000, Russell King - ARM Linux wrote:\n" @@ -97,4 +97,4 @@ "\n" Jerome -e4fdf7a8e65c3b624d84e855853d290541758fe418eb89eca1e62e9033be700d +71725fb9b46ce47720b091c0619b99864109ebc81d30ebc0920fc0e4d45fbe1d
diff --git a/a/1.txt b/N2/1.txt index d76d489..663f29a 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -11,7 +11,7 @@ On Thu, 2017-01-05 at 23:25 +0000, Russell King - ARM Linux wrote: > Another concern with this patch is that the existing phylib "set_eee" > code is horribly buggy - it just translates the modes from userspace > into the register value and writes them directly to the register with -> no validation.??So it's possible to set modes in the register that +> no validation. So it's possible to set modes in the register that > the > hardware doesn't support, and have them advertised to the link > partner. @@ -69,10 +69,10 @@ The PHY is the Realtek RTL8211F > > On the SolidRun boards, they're using AR8035, and have suffered this -> occasional link drop problem.??What has been found is that it seems +> occasional link drop problem. What has been found is that it seems > to > be to do with the timing parameters, and it seemed to only be 1000bT -> that was affected.??I don't remember off hand exactly which or what +> that was affected. I don't remember off hand exactly which or what > the change was they made to stabilise it though, but I can probabily > find out tomorrow. > @@ -87,3 +87,8 @@ could think of but never found anything worth mentioning. If you have any ideas, I'd be happy to try. Jerome + +_______________________________________________ +linux-arm-kernel mailing list +linux-arm-kernel@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/a/content_digest b/N2/content_digest index a073ca5..6dfba7c 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,10 +1,27 @@ "ref\01480348229-25672-1-git-send-email-jbrunet@baylibre.com\0" "ref\0049b1efc-3bad-92e0-45ef-0563dc5d81de@gmail.com\0" "ref\020170105232508.GU14217@n2100.armlinux.org.uk\0" - "From\0jbrunet@baylibre.com (Jerome Brunet)\0" - "Subject\0[PATCH net-next v4 0/4] Fix OdroidC2 Gigabit Tx link issue\0" + "From\0Jerome Brunet <jbrunet@baylibre.com>\0" + "Subject\0Re: [PATCH net-next v4 0/4] Fix OdroidC2 Gigabit Tx link issue\0" "Date\0Fri, 06 Jan 2017 11:11:36 +0100\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0Russell King - ARM Linux <linux@armlinux.org.uk>" + " Florian Fainelli <f.fainelli@gmail.com>\0" + "Cc\0Andrew Lunn <andrew@lunn.ch>" + Alexandre TORGUE <alexandre.torgue@st.com> + Neil Armstrong <narmstrong@baylibre.com> + Martin Blumenstingl <martin.blumenstingl@googlemail.com> + netdev@vger.kernel.org + Giuseppe Cavallaro <peppe.cavallaro@st.com> + linux-kernel@vger.kernel.org + Yegor Yefremov <yegorslists@googlemail.com> + Julia Lawall <julia.lawall@lip6.fr> + devicetree@vger.kernel.org + Andre Roth <neolynx@gmail.com> + Kevin Hilman <khilman@baylibre.com> + Carlo Caione <carlo@caione.org> + linux-amlogic@lists.infradead.org + " Andreas F\303\244rber <afaerber@suse.de>" + " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Thu, 2017-01-05 at 23:25 +0000, Russell King - ARM Linux wrote:\n" @@ -20,7 +37,7 @@ "> Another concern with this patch is that the existing phylib \"set_eee\"\n" "> code is horribly buggy - it just translates the modes from userspace\n" "> into the register value and writes them directly to the register with\n" - "> no validation.??So it's possible to set modes in the register that\n" + "> no validation.\302\240\302\240So it's possible to set modes in the register that\n" "> the\n" "> hardware doesn't support, and have them advertised to the link\n" "> partner.\n" @@ -78,10 +95,10 @@ "\n" "> \n" "> On the SolidRun boards, they're using AR8035, and have suffered this\n" - "> occasional link drop problem.??What has been found is that it seems\n" + "> occasional link drop problem.\302\240\302\240What has been found is that it seems\n" "> to\n" "> be to do with the timing parameters, and it seemed to only be 1000bT\n" - "> that was affected.??I don't remember off hand exactly which or what\n" + "> that was affected.\302\240\302\240I don't remember off hand exactly which or what\n" "> the change was they made to stabilise it though, but I can probabily\n" "> find out tomorrow.\n" "> \n" @@ -95,6 +112,11 @@ "\n" "If you have any ideas, I'd be happy to try.\n" "\n" - Jerome + "Jerome\n" + "\n" + "_______________________________________________\n" + "linux-arm-kernel mailing list\n" + "linux-arm-kernel@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -e4fdf7a8e65c3b624d84e855853d290541758fe418eb89eca1e62e9033be700d +80e2ba4aee287c44b5220b72c333f6485900126e220d5dac02942d21006bb8e2
diff --git a/a/1.txt b/N3/1.txt index d76d489..b3d0a72 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -11,7 +11,7 @@ On Thu, 2017-01-05 at 23:25 +0000, Russell King - ARM Linux wrote: > Another concern with this patch is that the existing phylib "set_eee" > code is horribly buggy - it just translates the modes from userspace > into the register value and writes them directly to the register with -> no validation.??So it's possible to set modes in the register that +> no validation. So it's possible to set modes in the register that > the > hardware doesn't support, and have them advertised to the link > partner. @@ -69,10 +69,10 @@ The PHY is the Realtek RTL8211F > > On the SolidRun boards, they're using AR8035, and have suffered this -> occasional link drop problem.??What has been found is that it seems +> occasional link drop problem. What has been found is that it seems > to > be to do with the timing parameters, and it seemed to only be 1000bT -> that was affected.??I don't remember off hand exactly which or what +> that was affected. I don't remember off hand exactly which or what > the change was they made to stabilise it though, but I can probabily > find out tomorrow. > diff --git a/a/content_digest b/N3/content_digest index a073ca5..233013b 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -1,10 +1,27 @@ "ref\01480348229-25672-1-git-send-email-jbrunet@baylibre.com\0" "ref\0049b1efc-3bad-92e0-45ef-0563dc5d81de@gmail.com\0" "ref\020170105232508.GU14217@n2100.armlinux.org.uk\0" - "From\0jbrunet@baylibre.com (Jerome Brunet)\0" - "Subject\0[PATCH net-next v4 0/4] Fix OdroidC2 Gigabit Tx link issue\0" + "From\0Jerome Brunet <jbrunet@baylibre.com>\0" + "Subject\0Re: [PATCH net-next v4 0/4] Fix OdroidC2 Gigabit Tx link issue\0" "Date\0Fri, 06 Jan 2017 11:11:36 +0100\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0Russell King - ARM Linux <linux@armlinux.org.uk>" + " Florian Fainelli <f.fainelli@gmail.com>\0" + "Cc\0netdev@vger.kernel.org" + devicetree@vger.kernel.org + Andrew Lunn <andrew@lunn.ch> + Alexandre TORGUE <alexandre.torgue@st.com> + Neil Armstrong <narmstrong@baylibre.com> + Martin Blumenstingl <martin.blumenstingl@googlemail.com> + Kevin Hilman <khilman@baylibre.com> + linux-kernel@vger.kernel.org + Yegor Yefremov <yegorslists@googlemail.com> + Julia Lawall <julia.lawall@lip6.fr> + Andre Roth <neolynx@gmail.com> + linux-amlogic@lists.infradead.org + Carlo Caione <carlo@caione.org> + Giuseppe Cavallaro <peppe.cavallaro@st.com> + " Andreas F\303\244rber <afaerber@suse.de>" + " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Thu, 2017-01-05 at 23:25 +0000, Russell King - ARM Linux wrote:\n" @@ -20,7 +37,7 @@ "> Another concern with this patch is that the existing phylib \"set_eee\"\n" "> code is horribly buggy - it just translates the modes from userspace\n" "> into the register value and writes them directly to the register with\n" - "> no validation.??So it's possible to set modes in the register that\n" + "> no validation.\302\240\302\240So it's possible to set modes in the register that\n" "> the\n" "> hardware doesn't support, and have them advertised to the link\n" "> partner.\n" @@ -78,10 +95,10 @@ "\n" "> \n" "> On the SolidRun boards, they're using AR8035, and have suffered this\n" - "> occasional link drop problem.??What has been found is that it seems\n" + "> occasional link drop problem.\302\240\302\240What has been found is that it seems\n" "> to\n" "> be to do with the timing parameters, and it seemed to only be 1000bT\n" - "> that was affected.??I don't remember off hand exactly which or what\n" + "> that was affected.\302\240\302\240I don't remember off hand exactly which or what\n" "> the change was they made to stabilise it though, but I can probabily\n" "> find out tomorrow.\n" "> \n" @@ -97,4 +114,4 @@ "\n" Jerome -e4fdf7a8e65c3b624d84e855853d290541758fe418eb89eca1e62e9033be700d +0ebbebf386cfa90e6a4b61fa20f80460f8ff67e0e8270a9b068cba5693832c8a
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