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From: Archit Taneja <architt@codeaurora.org>
To: robdclark@gmail.com
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: [PATCH 00/10] drm/msm/dsi: Dual DSI and 8x96 PHY/PLL support
Date: Sat,  7 Jan 2017 18:40:32 +0530	[thread overview]
Message-ID: <1483794642-2184-1-git-send-email-architt@codeaurora.org> (raw)

This set adds 8x96 PHY/PLL with Dual DSI mode supported too.

Dual DSI on 8x96 requires the DSI host/manager drivers to propagate
some usecase info to the PHY/PLL drivers. Hai Li had worked on
some patches in the past to implement this.

Tested on 8996 MTP Dual DSI panel, and with a LeMaker panel (single DSI)
on DB820c.

Archit Taneja (6):
  drm/msm/dsi: Don't error if a DSI host doesn't have a device connected
  drm/msm/dsi: Add 8x96 info in dsi_cfg
  drm/msm/dsi: Add a PHY op that initializes version specific stuff
  drm/msm/dsi: Reset both PHYs before clock operation for dual DSI
  drm/msm/dsi: Udpate generated headers for 14nm PHY and PLL
  drm/msm/dsi: Add PHY/PLL for 8x96

Hai Li (4):
  drm/msm/dsi: Return more timings from PHY to host
  drm/msm/dsi: Pass down use case to PHY
  drm/msm/dsi: Move PHY operations out of host
  drm/msm/dsi: Add new method to calculate 14nm PHY timings

 drivers/gpu/drm/msm/Kconfig                     |    7 +
 drivers/gpu/drm/msm/Makefile                    |    2 +
 drivers/gpu/drm/msm/dsi/dsi.h                   |   46 +-
 drivers/gpu/drm/msm/dsi/dsi.xml.h               |  252 ++++++
 drivers/gpu/drm/msm/dsi/dsi_cfg.c               |   25 +
 drivers/gpu/drm/msm/dsi/dsi_cfg.h               |    1 +
 drivers/gpu/drm/msm/dsi/dsi_host.c              |   95 +-
 drivers/gpu/drm/msm/dsi/dsi_manager.c           |  195 +++--
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c           |  238 ++++-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h           |   20 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c      |  168 ++++
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c      |    5 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c      |    6 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c |    5 +-
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c           |   12 +
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h           |   11 +
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c      | 1067 +++++++++++++++++++++++
 17 files changed, 1985 insertions(+), 170 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
 create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

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             reply	other threads:[~2017-01-07 13:10 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-07 13:10 Archit Taneja [this message]
2017-01-07 13:10 ` [PATCH 01/10] drm/msm/dsi: Don't error if a DSI host doesn't have a device connected Archit Taneja
2017-01-07 13:10 ` [PATCH 02/10] drm/msm/dsi: Add 8x96 info in dsi_cfg Archit Taneja
2017-01-07 13:10 ` [PATCH 03/10] drm/msm/dsi: Add a PHY op that initializes version specific stuff Archit Taneja
2017-01-07 13:10 ` [PATCH 04/10] drm/msm/dsi: Return more timings from PHY to host Archit Taneja
2017-01-07 13:10 ` [PATCH 05/10] drm/msm/dsi: Pass down use case to PHY Archit Taneja
2017-01-07 13:10 ` [PATCH 06/10] drm/msm/dsi: Reset both PHYs before clock operation for dual DSI Archit Taneja
2017-01-07 13:10 ` [PATCH 07/10] drm/msm/dsi: Move PHY operations out of host Archit Taneja
2017-01-07 13:10 ` [PATCH 08/10] drm/msm/dsi: Udpate generated headers for 14nm PHY and PLL Archit Taneja
2017-01-07 13:10 ` [PATCH 09/10] drm/msm/dsi: Add new method to calculate 14nm PHY timings Archit Taneja
2017-01-07 13:10 ` [PATCH 10/10] drm/msm/dsi: Add PHY/PLL for 8x96 Archit Taneja
2017-01-19 20:17   ` Stephen Boyd
2017-01-23  4:06     ` Archit Taneja
2017-01-25  4:09   ` [PATCH v2 " Archit Taneja

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