From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?ISO-8859-1?Q?J=F6rg?= Krause Subject: Re: [PATCH v2] ASoC: mxs-saif: add mclk enable/disable ops Date: Sat, 07 Jan 2017 18:23:48 +0100 Message-ID: <1483809828.2227.2.camel@embedded.rocks> References: <20161222164926.19621-1-mans@mansr.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mout02.posteo.de (mout02.posteo.de [185.67.36.142]) by alsa0.perex.cz (Postfix) with ESMTP id 7EC47261740 for ; Sat, 7 Jan 2017 18:23:55 +0100 (CET) In-Reply-To: <20161222164926.19621-1-mans@mansr.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org To: Mans Rullgard , alsa-devel@alsa-project.org Cc: Mark Brown , Takashi Iwai , Liam Girdwood , linux-kernel@vger.kernel.org List-Id: alsa-devel@alsa-project.org SGkgTWFucywKCk9uIFRodSwgMjAxNi0xMi0yMiBhdCAxNjo0OSArMDAwMCwgTWFucyBSdWxsZ2Fy ZCB3cm90ZToKPiBUaGlzIG1ha2VzIG5vcm1hbCBjbGtfZW5hYmxlL2Rpc2FibGUoKSBjYWxscyBv biBteHNfc2FpZl9tY2xrIHdvcmsgYXMKPiBleHBlY3RlZCwgaS5lLiBhY3R1YWxseSB0dXJuIHRo ZSBtY2xrIG91dHB1dCBvbiBvciAod2hlbiBzYWZlKSBvZmYuCj4gVGhlIGV4aXN0aW5nIG14c19z YWlmX2dldC9wdXRfbWNsaygpIGZ1bmN0aW9ucyBhcmUgcmV3cml0dGVuIHRvIHVzZQo+IGNvbW1v biBjbGsgb3BlcmF0aW9ucyBvbiBteHNfc2FpZl9tY2xrIHJhdGhlciB0aGFuIGFjY2Vzc2luZwo+ IHJlZ2lzdGVycwo+IGRpcmVjdGx5Lgo+IAo+IFdpdGggdGhlc2UgY2hhbmdlcyBteHMtc2FpZiBj YW4gYmUgdXNlZCB0b2dldGhlciB3aXRoIHRoZSBzaW1wbGUtY2FyZAo+IGRyaXZlci4KCkkgY2Fu IGNvbmZpcm0gdGhhdCB0aGlzIHdvcmtzIGZvciBtZSB1c2luZyB0aGUgcGNtNTEwMmEsIHdtODUy NCBhbmQgdGhlCndtODczMSBjb2RlYyBkcml2ZXIuIEJ1dCBJIHdhcyBhYmxlIG9ubHkgdG8gdGVz dCBwbGF5YmFjayBvbiBzYWlmMCBmb3IKdGhvc2UgZHJpdmVycyBhcyBJIGZhaWxlZCB0byBzZXR1 cCB0aGUgc2ltcGxlLWNhcmQgZGV2aWNlIHRyZWUgbm9kZQpib3RoIGZvciBzYWlmMCBhbmQgc2Fp ZjEuCgpIb3dldmVyLCB3aGVuIHVzaW5nIHRoaXMgcGF0Y2ggd2l0aCBhIHBsYXRmb3JtIGRyaXZl ciwgZS5nLiBteHMtd204NTI0LCAKaW5zdGVhZCBvZiB0aGUgc2ltcGxlLWNhcmQgZGV2aWNlIHRy ZWUgbm9kZSBjb25maWd1cmF0aW9uLCBpdCBmYWlscyBmb3IKbWUuIE5vdGUsIHRoYXQgdGhlIHBs YXRmb3JtIGRyaXZlciBteHMtd204NTI0IGlzIGp1c3QgYSBtZXJlIGNvcHkgb2YKdGhlIG14cy1z Z3RsNTAwMCBkcml2ZXIuIFRoZSBlcnJvciBoYXBwZW5zIHdoZW4gcHJvYmluZyB0aGUgcGxhdGZv cm0KZHJpdmVyIGF0IGNhbGxpbmcgbXhzX3NhaWZfZ2V0X21jbGsoKTogImZhaWxlZCB0byBnZXQg bWNsayIuCgpBcyBJIGFtIHRlc3Rpbmcgb24gYSBjdXN0b20gYm9hcmQgbm90IG1haW5saW5lZCB5 ZXQgaXQgaXMgcG9zc2libGUgdGhhdApJIGRpZCBzb21ldGhpbmcgd3JvbmcuIFNvIG1heWJlIHNv bWVvbmUgaGF2aW5nIGFjY2VzcyB0byBhIG14cy1ib2FyZAp3aXRoIGEgc2d0bDUwMDAgY29kZWMg Y2FuIHZlcmlmeSB0aGlzPwoKSsO2cmcKCj4gCj4gU2lnbmVkLW9mZi1ieTogTWFucyBSdWxsZ2Fy ZCA8bWFuc0BtYW5zci5jb20+Cj4gLS0tCj4gdjI6IGFkZCAjaW5jbHVkZSA8bGludXgvY2xrLXBy b3ZpZGVyLmg+IG5lZWRlZCBieSBzb21lIGNvbmZpZ3MKPiAtLS0KPiDCoHNvdW5kL3NvYy9teHMv bXhzLXNhaWYuYyB8IDE0NCArKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrLS0tLQo+IC0t LS0tLS0tLS0tLQo+IMKgc291bmQvc29jL214cy9teHMtc2FpZi5oIHzCoMKgwqAzICsKPiDCoDIg ZmlsZXMgY2hhbmdlZCwgOTkgaW5zZXJ0aW9ucygrKSwgNDggZGVsZXRpb25zKC0pCj4gCj4gZGlm ZiAtLWdpdCBhL3NvdW5kL3NvYy9teHMvbXhzLXNhaWYuYyBiL3NvdW5kL3NvYy9teHMvbXhzLXNh aWYuYwo+IGluZGV4IGEwMDJhYjg5Mjc3Mi4uN2M2MjAzOTlmOTZiIDEwMDY0NAo+IC0tLSBhL3Nv dW5kL3NvYy9teHMvbXhzLXNhaWYuYwo+ICsrKyBiL3NvdW5kL3NvYy9teHMvbXhzLXNhaWYuYwo+ IEBAIC0yMDQsMjcgKzIwNCwxNSBAQCBzdGF0aWMgaW50IG14c19zYWlmX3NldF9jbGsoc3RydWN0 IG14c19zYWlmCj4gKnNhaWYsCj4gwqAgKi8KPiDCoGludCBteHNfc2FpZl9wdXRfbWNsayh1bnNp Z25lZCBpbnQgc2FpZl9pZCkKPiDCoHsKPiAtCXN0cnVjdCBteHNfc2FpZiAqc2FpZiA9IG14c19z YWlmW3NhaWZfaWRdOwo+IC0JdTMyIHN0YXQ7Cj4gKwlzdHJ1Y3QgY2xrICpjbGs7Cj4gwqAKPiAt CWlmICghc2FpZikKPiAtCQlyZXR1cm4gLUVJTlZBTDsKPiArCWNsayA9IGNsa19nZXQoTlVMTCwg Im14c19zYWlmX21jbGsiKTsKPiArCWlmIChJU19FUlIoY2xrKSkKPiArCQlyZXR1cm4gUFRSX0VS UihjbGspOwo+IMKgCj4gLQlzdGF0ID0gX19yYXdfcmVhZGwoc2FpZi0+YmFzZSArIFNBSUZfU1RB VCk7Cj4gLQlpZiAoc3RhdCAmIEJNX1NBSUZfU1RBVF9CVVNZKSB7Cj4gLQkJZGV2X2VycihzYWlm LT5kZXYsICJlcnJvcjogYnVzeVxuIik7Cj4gLQkJcmV0dXJuIC1FQlVTWTsKPiAtCX0KPiArCWNs a19kaXNhYmxlX3VucHJlcGFyZShjbGspOwo+ICsJY2xrX3B1dChjbGspOwo+IMKgCj4gLQljbGtf ZGlzYWJsZV91bnByZXBhcmUoc2FpZi0+Y2xrKTsKPiAtCj4gLQkvKiBkaXNhYmxlIE1DTEsgb3V0 cHV0ICovCj4gLQlfX3Jhd193cml0ZWwoQk1fU0FJRl9DVFJMX0NMS0dBVEUsCj4gLQkJc2FpZi0+ YmFzZSArIFNBSUZfQ1RSTCArIE1YU19TRVRfQUREUik7Cj4gLQlfX3Jhd193cml0ZWwoQk1fU0FJ Rl9DVFJMX1JVTiwKPiAtCQlzYWlmLT5iYXNlICsgU0FJRl9DVFJMICsgTVhTX0NMUl9BRERSKTsK PiAtCj4gLQlzYWlmLT5tY2xrX2luX3VzZSA9IDA7Cj4gwqAJcmV0dXJuIDA7Cj4gwqB9Cj4gwqBF WFBPUlRfU1lNQk9MX0dQTChteHNfc2FpZl9wdXRfbWNsayk7Cj4gQEAgLTIzOSw0NyArMjI3LDMz IEBAIGludCBteHNfc2FpZl9nZXRfbWNsayh1bnNpZ25lZCBpbnQgc2FpZl9pZCwKPiB1bnNpZ25l ZCBpbnQgbWNsaywKPiDCoAkJCQkJdW5zaWduZWQgaW50IHJhdGUpCj4gwqB7Cj4gwqAJc3RydWN0 IG14c19zYWlmICpzYWlmID0gbXhzX3NhaWZbc2FpZl9pZF07Cj4gLQl1MzIgc3RhdDsKPiDCoAlp bnQgcmV0Owo+IMKgCXN0cnVjdCBteHNfc2FpZiAqbWFzdGVyX3NhaWY7Cj4gKwlzdHJ1Y3QgY2xr ICpjbGs7Cj4gwqAKPiDCoAlpZiAoIXNhaWYpCj4gwqAJCXJldHVybiAtRUlOVkFMOwo+IMKgCj4g LQkvKiBDbGVhciBSZXNldCAqLwo+IC0JX19yYXdfd3JpdGVsKEJNX1NBSUZfQ1RSTF9TRlRSU1Qs Cj4gLQkJc2FpZi0+YmFzZSArIFNBSUZfQ1RSTCArIE1YU19DTFJfQUREUik7Cj4gLQo+IC0JLyog RklYTUU6IG5lZWQgY2xlYXIgY2xrIGdhdGUgZm9yIHJlZ2lzdGVyIHIvdyAqLwo+IC0JX19yYXdf d3JpdGVsKEJNX1NBSUZfQ1RSTF9DTEtHQVRFLAo+IC0JCXNhaWYtPmJhc2UgKyBTQUlGX0NUUkwg KyBNWFNfQ0xSX0FERFIpOwo+IC0KPiDCoAltYXN0ZXJfc2FpZiA9IG14c19zYWlmX2dldF9tYXN0 ZXIoc2FpZik7Cj4gwqAJaWYgKHNhaWYgIT0gbWFzdGVyX3NhaWYpIHsKPiDCoAkJZGV2X2Vycihz YWlmLT5kZXYsICJjYW4gbm90IGdldCBtY2xrIGZyb20gYSBub24tCj4gbWFzdGVyIHNhaWZcbiIp Owo+IMKgCQlyZXR1cm4gLUVJTlZBTDsKPiDCoAl9Cj4gwqAKPiAtCXN0YXQgPSBfX3Jhd19yZWFk bChzYWlmLT5iYXNlICsgU0FJRl9TVEFUKTsKPiAtCWlmIChzdGF0ICYgQk1fU0FJRl9TVEFUX0JV U1kpIHsKPiAtCQlkZXZfZXJyKHNhaWYtPmRldiwgImVycm9yOiBidXN5XG4iKTsKPiAtCQlyZXR1 cm4gLUVCVVNZOwo+IC0JfQo+ICsJY2xrID0gY2xrX2dldChOVUxMLCAibXhzX3NhaWZfbWNsayIp Owo+ICsJaWYgKElTX0VSUihjbGspKQo+ICsJCXJldHVybiBQVFJfRVJSKGNsayk7Cj4gKwo+ICsJ cmV0ID0gY2xrX3ByZXBhcmVfZW5hYmxlKGNsayk7Cj4gKwlpZiAocmV0KQo+ICsJCWdvdG8gb3V0 Owo+IMKgCj4gLQlzYWlmLT5tY2xrX2luX3VzZSA9IDE7Cj4gwqAJcmV0ID0gbXhzX3NhaWZfc2V0 X2NsayhzYWlmLCBtY2xrLCByYXRlKTsKPiAtCWlmIChyZXQpCj4gLQkJcmV0dXJuIHJldDsKPiDC oAo+IC0JcmV0ID0gY2xrX3ByZXBhcmVfZW5hYmxlKHNhaWYtPmNsayk7Cj4gLQlpZiAocmV0KQo+ IC0JCXJldHVybiByZXQ7Cj4gK291dDoKPiArCWNsa19wdXQoY2xrKTsKPiDCoAo+IC0JLyogZW5h YmxlIE1DTEsgb3V0cHV0ICovCj4gLQlfX3Jhd193cml0ZWwoQk1fU0FJRl9DVFJMX1JVTiwKPiAt CQlzYWlmLT5iYXNlICsgU0FJRl9DVFJMICsgTVhTX1NFVF9BRERSKTsKPiAtCj4gLQlyZXR1cm4g MDsKPiArCXJldHVybiByZXQ7Cj4gwqB9Cj4gwqBFWFBPUlRfU1lNQk9MX0dQTChteHNfc2FpZl9n ZXRfbWNsayk7Cj4gwqAKPiBAQCAtNjg3LDE4ICs2NjEsOTIgQEAgc3RhdGljIGlycXJldHVybl90 IG14c19zYWlmX2lycShpbnQgaXJxLCB2b2lkCj4gKmRldl9pZCkKPiDCoAlyZXR1cm4gSVJRX0hB TkRMRUQ7Cj4gwqB9Cj4gwqAKPiArI2RlZmluZSB0b19teHNfc2FpZihjKSBjb250YWluZXJfb2Yo Yywgc3RydWN0IG14c19zYWlmLCBkaXZfY2xrLmh3KQo+ICsKPiArc3RhdGljIGludCBteHNfc2Fp Zl9tY2xrX2VuYWJsZShzdHJ1Y3QgY2xrX2h3ICpodykKPiArewo+ICsJc3RydWN0IG14c19zYWlm ICpzYWlmID0gdG9fbXhzX3NhaWYoaHcpOwo+ICsKPiArCS8qIENsZWFyIFJlc2V0ICovCj4gKwlf X3Jhd193cml0ZWwoQk1fU0FJRl9DVFJMX1NGVFJTVCwKPiArCQlzYWlmLT5iYXNlICsgU0FJRl9D VFJMICsgTVhTX0NMUl9BRERSKTsKPiArCj4gKwkvKiBDbGVhciBjbGsgZ2F0ZSAqLwo+ICsJX19y YXdfd3JpdGVsKEJNX1NBSUZfQ1RSTF9DTEtHQVRFLAo+ICsJCXNhaWYtPmJhc2UgKyBTQUlGX0NU UkwgKyBNWFNfQ0xSX0FERFIpOwo+ICsKPiArCS8qIGVuYWJsZSBNQ0xLIG91dHB1dCAqLwo+ICsJ X19yYXdfd3JpdGVsKEJNX1NBSUZfQ1RSTF9SVU4sCj4gKwkJc2FpZi0+YmFzZSArIFNBSUZfQ1RS TCArIE1YU19TRVRfQUREUik7Cj4gKwo+ICsJc2FpZi0+bWNsa19pbl91c2UgPSAxOwo+ICsKPiAr CXJldHVybiAwOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCBteHNfc2FpZl9tY2xrX2Rpc2FibGUo c3RydWN0IGNsa19odyAqaHcpCj4gK3sKPiArCXN0cnVjdCBteHNfc2FpZiAqc2FpZiA9IHRvX214 c19zYWlmKGh3KTsKPiArCj4gKwlpZiAoIXNhaWYtPm9uZ29pbmcpCj4gKwkJX19yYXdfd3JpdGVs KEJNX1NBSUZfQ1RSTF9SVU4sCj4gKwkJCcKgwqDCoMKgwqBzYWlmLT5iYXNlICsgU0FJRl9DVFJM ICsgTVhTX0NMUl9BRERSKTsKPiArCj4gKwlzYWlmLT5tY2xrX2luX3VzZSA9IDA7Cj4gK30KPiAr Cj4gK3N0YXRpYyB1bnNpZ25lZCBsb25nIG14c19zYWlmX21jbGtfcmVjYWxjX3JhdGUoc3RydWN0 IGNsa19odyAqaHcsCj4gKwkJCQkJwqDCoMKgwqDCoMKgwqB1bnNpZ25lZCBsb25nCj4gcGFyZW50 X3JhdGUpCj4gK3sKPiArCXJldHVybiBjbGtfZGl2aWRlcl9vcHMucmVjYWxjX3JhdGUoaHcsIHBh cmVudF9yYXRlKTsKPiArfQo+ICsKPiArc3RhdGljIGxvbmcgbXhzX3NhaWZfbWNsa19yb3VuZF9y YXRlKHN0cnVjdCBjbGtfaHcgKmh3LCB1bnNpZ25lZAo+IGxvbmcgcmF0ZSwKPiArCQkJCcKgwqDC oMKgwqB1bnNpZ25lZCBsb25nICpwYXJlbnRfcmF0ZSkKPiArewo+ICsJcmV0dXJuIGNsa19kaXZp ZGVyX29wcy5yb3VuZF9yYXRlKGh3LCByYXRlLCBwYXJlbnRfcmF0ZSk7Cj4gK30KPiArCj4gK3N0 YXRpYyBpbnQgbXhzX3NhaWZfbWNsa19zZXRfcmF0ZShzdHJ1Y3QgY2xrX2h3ICpodywgdW5zaWdu ZWQgbG9uZwo+IHJhdGUsCj4gKwkJCQnCoMKgdW5zaWduZWQgbG9uZyBwYXJlbnRfcmF0ZSkKPiAr ewo+ICsJcmV0dXJuIGNsa19kaXZpZGVyX29wcy5zZXRfcmF0ZShodywgcmF0ZSwgcGFyZW50X3Jh dGUpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IGNsa19vcHMgbXhzX3NhaWZfbWNs a19vcHMgPSB7Cj4gKwkuZW5hYmxlCQk9IG14c19zYWlmX21jbGtfZW5hYmxlLAo+ICsJLmRpc2Fi bGUJPSBteHNfc2FpZl9tY2xrX2Rpc2FibGUsCj4gKwkucmVjYWxjX3JhdGUJPSBteHNfc2FpZl9t Y2xrX3JlY2FsY19yYXRlLAo+ICsJLnJvdW5kX3JhdGUJPSBteHNfc2FpZl9tY2xrX3JvdW5kX3Jh dGUsCj4gKwkuc2V0X3JhdGUJPSBteHNfc2FpZl9tY2xrX3NldF9yYXRlLAo+ICt9Owo+ICsKPiDC oHN0YXRpYyBpbnQgbXhzX3NhaWZfbWNsa19pbml0KHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBk ZXYpCj4gwqB7Cj4gwqAJc3RydWN0IG14c19zYWlmICpzYWlmID0gcGxhdGZvcm1fZ2V0X2RydmRh dGEocGRldik7Cj4gwqAJc3RydWN0IGRldmljZV9ub2RlICpucCA9IHBkZXYtPmRldi5vZl9ub2Rl Owo+ICsJc3RydWN0IGNsa19pbml0X2RhdGEgaW5pdDsKPiArCXN0cnVjdCBjbGtfZGl2aWRlciAq ZGl2Owo+IMKgCXN0cnVjdCBjbGsgKmNsazsKPiArCWNvbnN0IGNoYXIgKnBhcmVudF9uYW1lOwo+ IMKgCWludCByZXQ7Cj4gwqAKPiAtCWNsayA9IGNsa19yZWdpc3Rlcl9kaXZpZGVyKCZwZGV2LT5k ZXYsICJteHNfc2FpZl9tY2xrIiwKPiAtCQkJCcKgwqDCoF9fY2xrX2dldF9uYW1lKHNhaWYtPmNs ayksIDAsCj4gLQkJCQnCoMKgwqBzYWlmLT5iYXNlICsgU0FJRl9DVFJMLAo+IC0JCQkJwqDCoMKg QlBfU0FJRl9DVFJMX0JJVENMS19NVUxUX1JBVEUsIDMsCj4gLQkJCQnCoMKgwqAwLCBOVUxMKTsK PiArCXBhcmVudF9uYW1lID0gX19jbGtfZ2V0X25hbWUoc2FpZi0+Y2xrKTsKPiArCj4gKwlpbml0 Lm5hbWUgPSAibXhzX3NhaWZfbWNsayI7Cj4gKwlpbml0Lm9wcyA9ICZteHNfc2FpZl9tY2xrX29w czsKPiArCWluaXQuZmxhZ3MgPSBDTEtfR0VUX1JBVEVfTk9DQUNIRSB8IENMS19JU19CQVNJQzsK PiArCWluaXQucGFyZW50X25hbWVzID0gJnBhcmVudF9uYW1lOwo+ICsJaW5pdC5udW1fcGFyZW50 cyA9IDE7Cj4gKwo+ICsJZGl2ID0gJnNhaWYtPmRpdl9jbGs7Cj4gKwlkaXYtPnJlZyA9IHNhaWYt PmJhc2UgKyBTQUlGX0NUUkw7Cj4gKwlkaXYtPnNoaWZ0ID0gQlBfU0FJRl9DVFJMX0JJVENMS19N VUxUX1JBVEU7Cj4gKwlkaXYtPndpZHRoID0gMzsKPiArCWRpdi0+ZmxhZ3MgPSBDTEtfRElWSURF Ul9QT1dFUl9PRl9UV087Cj4gKwlkaXYtPmh3LmluaXQgPSAmaW5pdDsKPiArCj4gKwljbGsgPSBj bGtfcmVnaXN0ZXIoJnBkZXYtPmRldiwgJmRpdi0+aHcpOwo+IMKgCWlmIChJU19FUlIoY2xrKSkg ewo+IMKgCQlyZXQgPSBQVFJfRVJSKGNsayk7Cj4gwqAJCWlmIChyZXQgPT0gLUVFWElTVCkKPiBk aWZmIC0tZ2l0IGEvc291bmQvc29jL214cy9teHMtc2FpZi5oIGIvc291bmQvc29jL214cy9teHMt c2FpZi5oCj4gaW5kZXggOWE0YzBiMjkxYjllLi5lMWJiNWNiMDBlYzAgMTAwNjQ0Cj4gLS0tIGEv c291bmQvc29jL214cy9teHMtc2FpZi5oCj4gKysrIGIvc291bmQvc29jL214cy9teHMtc2FpZi5o Cj4gQEAgLTEwOCw2ICsxMDgsNyBAQAo+IMKgCj4gwqAjZGVmaW5lIE1YU19TQUlGX01DTEsJCTAK PiDCoAo+ICsjaW5jbHVkZSA8bGludXgvY2xrLXByb3ZpZGVyLmg+Cj4gwqAjaW5jbHVkZSAibXhz LXBjbS5oIgo+IMKgCj4gwqBzdHJ1Y3QgbXhzX3NhaWYgewo+IEBAIC0xMjgsNiArMTI5LDggQEAg c3RydWN0IG14c19zYWlmIHsKPiDCoAkJTVhTX1NBSUZfU1RBVEVfU1RPUFBFRCwKPiDCoAkJTVhT X1NBSUZfU1RBVEVfUlVOTklORywKPiDCoAl9IHN0YXRlOwo+ICsKPiArCXN0cnVjdCBjbGtfZGl2 aWRlciBkaXZfY2xrOwo+IMKgfTsKPiDCoAo+IMKgZXh0ZXJuIGludCBteHNfc2FpZl9wdXRfbWNs ayh1bnNpZ25lZCBpbnQgc2FpZl9pZCk7Cl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fCkFsc2EtZGV2ZWwgbWFpbGluZyBsaXN0CkFsc2EtZGV2ZWxAYWxzYS1w cm9qZWN0Lm9yZwpodHRwOi8vbWFpbG1hbi5hbHNhLXByb2plY3Qub3JnL21haWxtYW4vbGlzdGlu Zm8vYWxzYS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933714AbdAGRbL (ORCPT ); Sat, 7 Jan 2017 12:31:11 -0500 Received: from mout02.posteo.de ([185.67.36.142]:45166 "EHLO mout02.posteo.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755996AbdAGRbC (ORCPT ); Sat, 7 Jan 2017 12:31:02 -0500 X-Greylist: delayed 428 seconds by postgrey-1.27 at vger.kernel.org; Sat, 07 Jan 2017 12:31:02 EST Message-ID: <1483809828.2227.2.camel@embedded.rocks> Subject: Re: [alsa-devel] [PATCH v2] ASoC: mxs-saif: add mclk enable/disable ops From: =?ISO-8859-1?Q?J=F6rg?= Krause To: Mans Rullgard , alsa-devel@alsa-project.org Cc: Liam Girdwood , linux-kernel@vger.kernel.org, Takashi Iwai , Mark Brown Date: Sat, 07 Jan 2017 18:23:48 +0100 In-Reply-To: <20161222164926.19621-1-mans@mansr.com> References: <20161222164926.19621-1-mans@mansr.com> Organization: Embedded Rocks Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.3 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mans, On Thu, 2016-12-22 at 16:49 +0000, Mans Rullgard wrote: > This makes normal clk_enable/disable() calls on mxs_saif_mclk work as > expected, i.e. actually turn the mclk output on or (when safe) off. > The existing mxs_saif_get/put_mclk() functions are rewritten to use > common clk operations on mxs_saif_mclk rather than accessing > registers > directly. > > With these changes mxs-saif can be used together with the simple-card > driver. I can confirm that this works for me using the pcm5102a, wm8524 and the wm8731 codec driver. But I was able only to test playback on saif0 for those drivers as I failed to setup the simple-card device tree node both for saif0 and saif1. However, when using this patch with a platform driver, e.g. mxs-wm8524, instead of the simple-card device tree node configuration, it fails for me. Note, that the platform driver mxs-wm8524 is just a mere copy of the mxs-sgtl5000 driver. The error happens when probing the platform driver at calling mxs_saif_get_mclk(): "failed to get mclk". As I am testing on a custom board not mainlined yet it is possible that I did something wrong. So maybe someone having access to a mxs-board with a sgtl5000 codec can verify this? Jörg > > Signed-off-by: Mans Rullgard > --- > v2: add #include needed by some configs > --- >  sound/soc/mxs/mxs-saif.c | 144 +++++++++++++++++++++++++++++++---- > ------------ >  sound/soc/mxs/mxs-saif.h |   3 + >  2 files changed, 99 insertions(+), 48 deletions(-) > > diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c > index a002ab892772..7c620399f96b 100644 > --- a/sound/soc/mxs/mxs-saif.c > +++ b/sound/soc/mxs/mxs-saif.c > @@ -204,27 +204,15 @@ static int mxs_saif_set_clk(struct mxs_saif > *saif, >   */ >  int mxs_saif_put_mclk(unsigned int saif_id) >  { > - struct mxs_saif *saif = mxs_saif[saif_id]; > - u32 stat; > + struct clk *clk; >   > - if (!saif) > - return -EINVAL; > + clk = clk_get(NULL, "mxs_saif_mclk"); > + if (IS_ERR(clk)) > + return PTR_ERR(clk); >   > - stat = __raw_readl(saif->base + SAIF_STAT); > - if (stat & BM_SAIF_STAT_BUSY) { > - dev_err(saif->dev, "error: busy\n"); > - return -EBUSY; > - } > + clk_disable_unprepare(clk); > + clk_put(clk); >   > - clk_disable_unprepare(saif->clk); > - > - /* disable MCLK output */ > - __raw_writel(BM_SAIF_CTRL_CLKGATE, > - saif->base + SAIF_CTRL + MXS_SET_ADDR); > - __raw_writel(BM_SAIF_CTRL_RUN, > - saif->base + SAIF_CTRL + MXS_CLR_ADDR); > - > - saif->mclk_in_use = 0; >   return 0; >  } >  EXPORT_SYMBOL_GPL(mxs_saif_put_mclk); > @@ -239,47 +227,33 @@ int mxs_saif_get_mclk(unsigned int saif_id, > unsigned int mclk, >   unsigned int rate) >  { >   struct mxs_saif *saif = mxs_saif[saif_id]; > - u32 stat; >   int ret; >   struct mxs_saif *master_saif; > + struct clk *clk; >   >   if (!saif) >   return -EINVAL; >   > - /* Clear Reset */ > - __raw_writel(BM_SAIF_CTRL_SFTRST, > - saif->base + SAIF_CTRL + MXS_CLR_ADDR); > - > - /* FIXME: need clear clk gate for register r/w */ > - __raw_writel(BM_SAIF_CTRL_CLKGATE, > - saif->base + SAIF_CTRL + MXS_CLR_ADDR); > - >   master_saif = mxs_saif_get_master(saif); >   if (saif != master_saif) { >   dev_err(saif->dev, "can not get mclk from a non- > master saif\n"); >   return -EINVAL; >   } >   > - stat = __raw_readl(saif->base + SAIF_STAT); > - if (stat & BM_SAIF_STAT_BUSY) { > - dev_err(saif->dev, "error: busy\n"); > - return -EBUSY; > - } > + clk = clk_get(NULL, "mxs_saif_mclk"); > + if (IS_ERR(clk)) > + return PTR_ERR(clk); > + > + ret = clk_prepare_enable(clk); > + if (ret) > + goto out; >   > - saif->mclk_in_use = 1; >   ret = mxs_saif_set_clk(saif, mclk, rate); > - if (ret) > - return ret; >   > - ret = clk_prepare_enable(saif->clk); > - if (ret) > - return ret; > +out: > + clk_put(clk); >   > - /* enable MCLK output */ > - __raw_writel(BM_SAIF_CTRL_RUN, > - saif->base + SAIF_CTRL + MXS_SET_ADDR); > - > - return 0; > + return ret; >  } >  EXPORT_SYMBOL_GPL(mxs_saif_get_mclk); >   > @@ -687,18 +661,92 @@ static irqreturn_t mxs_saif_irq(int irq, void > *dev_id) >   return IRQ_HANDLED; >  } >   > +#define to_mxs_saif(c) container_of(c, struct mxs_saif, div_clk.hw) > + > +static int mxs_saif_mclk_enable(struct clk_hw *hw) > +{ > + struct mxs_saif *saif = to_mxs_saif(hw); > + > + /* Clear Reset */ > + __raw_writel(BM_SAIF_CTRL_SFTRST, > + saif->base + SAIF_CTRL + MXS_CLR_ADDR); > + > + /* Clear clk gate */ > + __raw_writel(BM_SAIF_CTRL_CLKGATE, > + saif->base + SAIF_CTRL + MXS_CLR_ADDR); > + > + /* enable MCLK output */ > + __raw_writel(BM_SAIF_CTRL_RUN, > + saif->base + SAIF_CTRL + MXS_SET_ADDR); > + > + saif->mclk_in_use = 1; > + > + return 0; > +} > + > +static void mxs_saif_mclk_disable(struct clk_hw *hw) > +{ > + struct mxs_saif *saif = to_mxs_saif(hw); > + > + if (!saif->ongoing) > + __raw_writel(BM_SAIF_CTRL_RUN, > +      saif->base + SAIF_CTRL + MXS_CLR_ADDR); > + > + saif->mclk_in_use = 0; > +} > + > +static unsigned long mxs_saif_mclk_recalc_rate(struct clk_hw *hw, > +        unsigned long > parent_rate) > +{ > + return clk_divider_ops.recalc_rate(hw, parent_rate); > +} > + > +static long mxs_saif_mclk_round_rate(struct clk_hw *hw, unsigned > long rate, > +      unsigned long *parent_rate) > +{ > + return clk_divider_ops.round_rate(hw, rate, parent_rate); > +} > + > +static int mxs_saif_mclk_set_rate(struct clk_hw *hw, unsigned long > rate, > +   unsigned long parent_rate) > +{ > + return clk_divider_ops.set_rate(hw, rate, parent_rate); > +} > + > +static const struct clk_ops mxs_saif_mclk_ops = { > + .enable = mxs_saif_mclk_enable, > + .disable = mxs_saif_mclk_disable, > + .recalc_rate = mxs_saif_mclk_recalc_rate, > + .round_rate = mxs_saif_mclk_round_rate, > + .set_rate = mxs_saif_mclk_set_rate, > +}; > + >  static int mxs_saif_mclk_init(struct platform_device *pdev) >  { >   struct mxs_saif *saif = platform_get_drvdata(pdev); >   struct device_node *np = pdev->dev.of_node; > + struct clk_init_data init; > + struct clk_divider *div; >   struct clk *clk; > + const char *parent_name; >   int ret; >   > - clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk", > -    __clk_get_name(saif->clk), 0, > -    saif->base + SAIF_CTRL, > -    BP_SAIF_CTRL_BITCLK_MULT_RATE, 3, > -    0, NULL); > + parent_name = __clk_get_name(saif->clk); > + > + init.name = "mxs_saif_mclk"; > + init.ops = &mxs_saif_mclk_ops; > + init.flags = CLK_GET_RATE_NOCACHE | CLK_IS_BASIC; > + init.parent_names = &parent_name; > + init.num_parents = 1; > + > + div = &saif->div_clk; > + div->reg = saif->base + SAIF_CTRL; > + div->shift = BP_SAIF_CTRL_BITCLK_MULT_RATE; > + div->width = 3; > + div->flags = CLK_DIVIDER_POWER_OF_TWO; > + div->hw.init = &init; > + > + clk = clk_register(&pdev->dev, &div->hw); >   if (IS_ERR(clk)) { >   ret = PTR_ERR(clk); >   if (ret == -EEXIST) > diff --git a/sound/soc/mxs/mxs-saif.h b/sound/soc/mxs/mxs-saif.h > index 9a4c0b291b9e..e1bb5cb00ec0 100644 > --- a/sound/soc/mxs/mxs-saif.h > +++ b/sound/soc/mxs/mxs-saif.h > @@ -108,6 +108,7 @@ >   >  #define MXS_SAIF_MCLK 0 >   > +#include >  #include "mxs-pcm.h" >   >  struct mxs_saif { > @@ -128,6 +129,8 @@ struct mxs_saif { >   MXS_SAIF_STATE_STOPPED, >   MXS_SAIF_STATE_RUNNING, >   } state; > + > + struct clk_divider div_clk; >  }; >   >  extern int mxs_saif_put_mclk(unsigned int saif_id);